Commit ac2e8522857ccf0977a91faae185d533b3812216
1 parent
d2c639d6
sh4: sh_pci. Register resouces both at A7 and P4.
Add resource registration both for P4 and A7. This is needed because of #5935 SH4: Eliminate P4 to A7 mangling. Additionally, {reg,iop,mem}base which is no longer used are removed. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6433 c046a42c-6fe2-441c-8c8c-71466251a162
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7 additions
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10 deletions
hw/sh_pci.c
@@ -29,9 +29,6 @@ | @@ -29,9 +29,6 @@ | ||
29 | typedef struct { | 29 | typedef struct { |
30 | PCIBus *bus; | 30 | PCIBus *bus; |
31 | PCIDevice *dev; | 31 | PCIDevice *dev; |
32 | - uint32_t regbase; | ||
33 | - uint32_t iopbase; | ||
34 | - uint32_t membase; | ||
35 | uint32_t par; | 32 | uint32_t par; |
36 | uint32_t mbr; | 33 | uint32_t mbr; |
37 | uint32_t iobr; | 34 | uint32_t iobr; |
@@ -181,15 +178,15 @@ PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | @@ -181,15 +178,15 @@ PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | ||
181 | 178 | ||
182 | p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice), | 179 | p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice), |
183 | -1, NULL, NULL); | 180 | -1, NULL, NULL); |
184 | - p->regbase = 0x1e200000; | ||
185 | - p->iopbase = 0x1e240000; | ||
186 | - p->membase = 0xfd000000; | ||
187 | reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p); | 181 | reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p); |
188 | - mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p); | ||
189 | iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p); | 182 | iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p); |
190 | - cpu_register_physical_memory(p->regbase, 0x224, reg); | ||
191 | - cpu_register_physical_memory(p->iopbase, 0x40000, iop); | ||
192 | - cpu_register_physical_memory(p->membase, 0x1000000, mem); | 183 | + mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p); |
184 | + cpu_register_physical_memory(0x1e200000, 0x224, reg); | ||
185 | + cpu_register_physical_memory(0x1e240000, 0x40000, iop); | ||
186 | + cpu_register_physical_memory(0x1d000000, 0x1000000, mem); | ||
187 | + cpu_register_physical_memory(0xfe200000, 0x224, reg); | ||
188 | + cpu_register_physical_memory(0xfe240000, 0x40000, iop); | ||
189 | + cpu_register_physical_memory(0xfd000000, 0x1000000, mem); | ||
193 | 190 | ||
194 | p->dev->config[0x00] = 0x54; // HITACHI | 191 | p->dev->config[0x00] = 0x54; // HITACHI |
195 | p->dev->config[0x01] = 0x10; // | 192 | p->dev->config[0x01] = 0x10; // |