gwj / at91sam9263 · Commits

Commit a993ba85cf50932cca8d697e2d45145fb21afafe

Authored by bellard
1 parent 226c9132

alpha disas (Falk Hueffner) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@155 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 1987 additions and 3 deletions
Makefile
  View file @a993ba8
@@ -30,10 +30,11 @@ LDFLAGS+=-Wl,-T,s390.ld @@ -30,10 +30,11 @@ LDFLAGS+=-Wl,-T,s390.ld
30 endif 30 endif
31 31
32 ifeq ($(ARCH),alpha) 32 ifeq ($(ARCH),alpha)
  33 +# -msmall-data is not used because we want two-instruction relocations
  34 +# for the constant constructions
  35 +OP_CFLAGS=-Wall -O2 -g
33 # Ensure there's only a single GP 36 # Ensure there's only a single GP
34 CFLAGS += -msmall-data -msmall-text 37 CFLAGS += -msmall-data -msmall-text
35 -# FIXME Too lazy to deal with gprelhigh/gprellow for now, inhibit them  
36 -OP_CFLAGS=$(CFLAGS) -mno-explicit-relocs  
37 LDFLAGS+=-Wl,-T,alpha.ld 38 LDFLAGS+=-Wl,-T,alpha.ld
38 endif 39 endif
39 40
@@ -63,7 +64,7 @@ OBJS+= libqemu.a @@ -63,7 +64,7 @@ OBJS+= libqemu.a
63 64
64 LIBOBJS+=thunk.o translate-i386.o op-i386.o exec-i386.o 65 LIBOBJS+=thunk.o translate-i386.o op-i386.o exec-i386.o
65 # NOTE: the disassembler code is only needed for debugging 66 # NOTE: the disassembler code is only needed for debugging
66 -LIBOBJS+=disas.o ppc-dis.o i386-dis.o dis-buf.o 67 +LIBOBJS+=disas.o ppc-dis.o i386-dis.o alpha-dis.o dis-buf.o
67 68
68 ifeq ($(ARCH),ia64) 69 ifeq ($(ARCH),ia64)
69 OBJS += ia64-syscall.o 70 OBJS += ia64-syscall.o
@@ -73,6 +74,11 @@ all: qemu qemu-doc.html @@ -73,6 +74,11 @@ all: qemu qemu-doc.html
73 74
74 qemu: $(OBJS) 75 qemu: $(OBJS)
75 $(CC) $(LDFLAGS) -o $@ $^ $(LIBS) 76 $(CC) $(LDFLAGS) -o $@ $^ $(LIBS)
  77 +ifeq ($(ARCH),alpha)
  78 +# Mark as 32 bit binary, i. e. it will be mapped into the low 31 bit of
  79 +# the address space (31 bit so sign extending doesn't matter)
  80 + echo -ne '\001\000\000\000' | dd of=qemu bs=1 seek=48 count=4 conv=notrunc
  81 +endif
76 82
77 depend: $(SRCS) 83 depend: $(SRCS)
78 $(CC) -MM $(CFLAGS) $^ 1>.depend 84 $(CC) -MM $(CFLAGS) $^ 1>.depend
alpha-dis.c 0 → 100644
  View file @a993ba8
  1 +/* alpha-dis.c -- Disassemble Alpha AXP instructions
  2 + Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
  3 + Contributed by Richard Henderson <rth@tamu.edu>,
  4 + patterned after the PPC opcode handling written by Ian Lance Taylor.
  5 +
  6 +This file is part of GDB, GAS, and the GNU binutils.
  7 +
  8 +GDB, GAS, and the GNU binutils are free software; you can redistribute
  9 +them and/or modify them under the terms of the GNU General Public
  10 +License as published by the Free Software Foundation; either version
  11 +2, or (at your option) any later version.
  12 +
  13 +GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 +will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
  16 +the GNU General Public License for more details.
  17 +
  18 +You should have received a copy of the GNU General Public License
  19 +along with this file; see the file COPYING. If not, write to the Free
  20 +Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21 +02111-1307, USA. */
  22 +
  23 +#include <stdio.h>
  24 +#include "dis-asm.h"
  25 +
  26 +#define ATTRIBUTE_UNUSED __attribute__((unused))
  27 +#define _(x) x
  28 +
  29 +/* The opcode table is an array of struct alpha_opcode. */
  30 +
  31 +struct alpha_opcode
  32 +{
  33 + /* The opcode name. */
  34 + const char *name;
  35 +
  36 + /* The opcode itself. Those bits which will be filled in with
  37 + operands are zeroes. */
  38 + unsigned opcode;
  39 +
  40 + /* The opcode mask. This is used by the disassembler. This is a
  41 + mask containing ones indicating those bits which must match the
  42 + opcode field, and zeroes indicating those bits which need not
  43 + match (and are presumably filled in by operands). */
  44 + unsigned mask;
  45 +
  46 + /* One bit flags for the opcode. These are primarily used to
  47 + indicate specific processors and environments support the
  48 + instructions. The defined values are listed below. */
  49 + unsigned flags;
  50 +
  51 + /* An array of operand codes. Each code is an index into the
  52 + operand table. They appear in the order which the operands must
  53 + appear in assembly code, and are terminated by a zero. */
  54 + unsigned char operands[4];
  55 +};
  56 +
  57 +/* The table itself is sorted by major opcode number, and is otherwise
  58 + in the order in which the disassembler should consider
  59 + instructions. */
  60 +extern const struct alpha_opcode alpha_opcodes[];
  61 +extern const unsigned alpha_num_opcodes;
  62 +
  63 +/* Values defined for the flags field of a struct alpha_opcode. */
  64 +
  65 +/* CPU Availability */
  66 +#define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */
  67 +#define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */
  68 +#define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */
  69 +#define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */
  70 +#define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */
  71 +#define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */
  72 +#define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */
  73 +
  74 +#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
  75 +
  76 +/* A macro to extract the major opcode from an instruction. */
  77 +#define AXP_OP(i) (((i) >> 26) & 0x3F)
  78 +
  79 +/* The total number of major opcodes. */
  80 +#define AXP_NOPS 0x40
  81 +
  82 +
  83 +/* The operands table is an array of struct alpha_operand. */
  84 +
  85 +struct alpha_operand
  86 +{
  87 + /* The number of bits in the operand. */
  88 + unsigned int bits : 5;
  89 +
  90 + /* How far the operand is left shifted in the instruction. */
  91 + unsigned int shift : 5;
  92 +
  93 + /* The default relocation type for this operand. */
  94 + signed int default_reloc : 16;
  95 +
  96 + /* One bit syntax flags. */
  97 + unsigned int flags : 16;
  98 +
  99 + /* Insertion function. This is used by the assembler. To insert an
  100 + operand value into an instruction, check this field.
  101 +
  102 + If it is NULL, execute
  103 + i |= (op & ((1 << o->bits) - 1)) << o->shift;
  104 + (i is the instruction which we are filling in, o is a pointer to
  105 + this structure, and op is the opcode value; this assumes twos
  106 + complement arithmetic).
  107 +
  108 + If this field is not NULL, then simply call it with the
  109 + instruction and the operand value. It will return the new value
  110 + of the instruction. If the ERRMSG argument is not NULL, then if
  111 + the operand value is illegal, *ERRMSG will be set to a warning
  112 + string (the operand will be inserted in any case). If the
  113 + operand value is legal, *ERRMSG will be unchanged (most operands
  114 + can accept any value). */
  115 + unsigned (*insert) PARAMS ((unsigned instruction, int op,
  116 + const char **errmsg));
  117 +
  118 + /* Extraction function. This is used by the disassembler. To
  119 + extract this operand type from an instruction, check this field.
  120 +
  121 + If it is NULL, compute
  122 + op = ((i) >> o->shift) & ((1 << o->bits) - 1);
  123 + if ((o->flags & AXP_OPERAND_SIGNED) != 0
  124 + && (op & (1 << (o->bits - 1))) != 0)
  125 + op -= 1 << o->bits;
  126 + (i is the instruction, o is a pointer to this structure, and op
  127 + is the result; this assumes twos complement arithmetic).
  128 +
  129 + If this field is not NULL, then simply call it with the
  130 + instruction value. It will return the value of the operand. If
  131 + the INVALID argument is not NULL, *INVALID will be set to
  132 + non-zero if this operand type can not actually be extracted from
  133 + this operand (i.e., the instruction does not match). If the
  134 + operand is valid, *INVALID will not be changed. */
  135 + int (*extract) PARAMS ((unsigned instruction, int *invalid));
  136 +};
  137 +
  138 +/* Elements in the table are retrieved by indexing with values from
  139 + the operands field of the alpha_opcodes table. */
  140 +
  141 +extern const struct alpha_operand alpha_operands[];
  142 +extern const unsigned alpha_num_operands;
  143 +
  144 +/* Values defined for the flags field of a struct alpha_operand. */
  145 +
  146 +/* Mask for selecting the type for typecheck purposes */
  147 +#define AXP_OPERAND_TYPECHECK_MASK \
  148 + (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \
  149 + AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \
  150 + AXP_OPERAND_UNSIGNED)
  151 +
  152 +/* This operand does not actually exist in the assembler input. This
  153 + is used to support extended mnemonics, for which two operands fields
  154 + are identical. The assembler should call the insert function with
  155 + any op value. The disassembler should call the extract function,
  156 + ignore the return value, and check the value placed in the invalid
  157 + argument. */
  158 +#define AXP_OPERAND_FAKE 01
  159 +
  160 +/* The operand should be wrapped in parentheses rather than separated
  161 + from the previous by a comma. This is used for the load and store
  162 + instructions which want their operands to look like "Ra,disp(Rb)". */
  163 +#define AXP_OPERAND_PARENS 02
  164 +
  165 +/* Used in combination with PARENS, this supresses the supression of
  166 + the comma. This is used for "jmp Ra,(Rb),hint". */
  167 +#define AXP_OPERAND_COMMA 04
  168 +
  169 +/* This operand names an integer register. */
  170 +#define AXP_OPERAND_IR 010
  171 +
  172 +/* This operand names a floating point register. */
  173 +#define AXP_OPERAND_FPR 020
  174 +
  175 +/* This operand is a relative branch displacement. The disassembler
  176 + prints these symbolically if possible. */
  177 +#define AXP_OPERAND_RELATIVE 040
  178 +
  179 +/* This operand takes signed values. */
  180 +#define AXP_OPERAND_SIGNED 0100
  181 +
  182 +/* This operand takes unsigned values. This exists primarily so that
  183 + a flags value of 0 can be treated as end-of-arguments. */
  184 +#define AXP_OPERAND_UNSIGNED 0200
  185 +
  186 +/* Supress overflow detection on this field. This is used for hints. */
  187 +#define AXP_OPERAND_NOOVERFLOW 0400
  188 +
  189 +/* Mask for optional argument default value. */
  190 +#define AXP_OPERAND_OPTIONAL_MASK 07000
  191 +
  192 +/* This operand defaults to zero. This is used for jump hints. */
  193 +#define AXP_OPERAND_DEFAULT_ZERO 01000
  194 +
  195 +/* This operand should default to the first (real) operand and is used
  196 + in conjunction with AXP_OPERAND_OPTIONAL. This allows
  197 + "and $0,3,$0" to be written as "and $0,3", etc. I don't like
  198 + it, but it's what DEC does. */
  199 +#define AXP_OPERAND_DEFAULT_FIRST 02000
  200 +
  201 +/* Similarly, this operand should default to the second (real) operand.
  202 + This allows "negl $0" instead of "negl $0,$0". */
  203 +#define AXP_OPERAND_DEFAULT_SECOND 04000
  204 +
  205 +
  206 +/* Register common names */
  207 +
  208 +#define AXP_REG_V0 0
  209 +#define AXP_REG_T0 1
  210 +#define AXP_REG_T1 2
  211 +#define AXP_REG_T2 3
  212 +#define AXP_REG_T3 4
  213 +#define AXP_REG_T4 5
  214 +#define AXP_REG_T5 6
  215 +#define AXP_REG_T6 7
  216 +#define AXP_REG_T7 8
  217 +#define AXP_REG_S0 9
  218 +#define AXP_REG_S1 10
  219 +#define AXP_REG_S2 11
  220 +#define AXP_REG_S3 12
  221 +#define AXP_REG_S4 13
  222 +#define AXP_REG_S5 14
  223 +#define AXP_REG_FP 15
  224 +#define AXP_REG_A0 16
  225 +#define AXP_REG_A1 17
  226 +#define AXP_REG_A2 18
  227 +#define AXP_REG_A3 19
  228 +#define AXP_REG_A4 20
  229 +#define AXP_REG_A5 21
  230 +#define AXP_REG_T8 22
  231 +#define AXP_REG_T9 23
  232 +#define AXP_REG_T10 24
  233 +#define AXP_REG_T11 25
  234 +#define AXP_REG_RA 26
  235 +#define AXP_REG_PV 27
  236 +#define AXP_REG_T12 27
  237 +#define AXP_REG_AT 28
  238 +#define AXP_REG_GP 29
  239 +#define AXP_REG_SP 30
  240 +#define AXP_REG_ZERO 31
  241 +
  242 +#define bfd_mach_alpha_ev4 0x10
  243 +#define bfd_mach_alpha_ev5 0x20
  244 +#define bfd_mach_alpha_ev6 0x30
  245 +
  246 +enum bfd_reloc_code_real {
  247 + BFD_RELOC_23_PCREL_S2,
  248 + BFD_RELOC_ALPHA_HINT
  249 +};
  250 +
  251 +bfd_vma
  252 +bfd_getl32 (addr)
  253 + register const bfd_byte *addr;
  254 +{
  255 + unsigned long v;
  256 +
  257 + v = (unsigned long) addr[0];
  258 + v |= (unsigned long) addr[1] << 8;
  259 + v |= (unsigned long) addr[2] << 16;
  260 + v |= (unsigned long) addr[3] << 24;
  261 + return (bfd_vma) v;
  262 +}
  263 +
  264 +/* This file holds the Alpha AXP opcode table. The opcode table includes
  265 + almost all of the extended instruction mnemonics. This permits the
  266 + disassembler to use them, and simplifies the assembler logic, at the
  267 + cost of increasing the table size. The table is strictly constant
  268 + data, so the compiler should be able to put it in the text segment.
  269 +
  270 + This file also holds the operand table. All knowledge about inserting
  271 + and extracting operands from instructions is kept in this file.
  272 +
  273 + The information for the base instruction set was compiled from the
  274 + _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
  275 + version 2.
  276 +
  277 + The information for the post-ev5 architecture extensions BWX, CIX and
  278 + MAX came from version 3 of this same document, which is also available
  279 + on-line at http://ftp.digital.com/pub/Digital/info/semiconductor
  280 + /literature/alphahb2.pdf
  281 +
  282 + The information for the EV4 PALcode instructions was compiled from
  283 + _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware
  284 + Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary
  285 + revision dated June 1994.
  286 +
  287 + The information for the EV5 PALcode instructions was compiled from
  288 + _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
  289 + Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */
  290 +
  291 +/* Local insertion and extraction functions */
  292 +
  293 +static unsigned insert_rba PARAMS((unsigned, int, const char **));
  294 +static unsigned insert_rca PARAMS((unsigned, int, const char **));
  295 +static unsigned insert_za PARAMS((unsigned, int, const char **));
  296 +static unsigned insert_zb PARAMS((unsigned, int, const char **));
  297 +static unsigned insert_zc PARAMS((unsigned, int, const char **));
  298 +static unsigned insert_bdisp PARAMS((unsigned, int, const char **));
  299 +static unsigned insert_jhint PARAMS((unsigned, int, const char **));
  300 +static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **));
  301 +
  302 +static int extract_rba PARAMS((unsigned, int *));
  303 +static int extract_rca PARAMS((unsigned, int *));
  304 +static int extract_za PARAMS((unsigned, int *));
  305 +static int extract_zb PARAMS((unsigned, int *));
  306 +static int extract_zc PARAMS((unsigned, int *));
  307 +static int extract_bdisp PARAMS((unsigned, int *));
  308 +static int extract_jhint PARAMS((unsigned, int *));
  309 +static int extract_ev6hwjhint PARAMS((unsigned, int *));
  310 +
  311 +
  312 +/* The operands table */
  313 +
  314 +const struct alpha_operand alpha_operands[] =
  315 +{
  316 + /* The fields are bits, shift, insert, extract, flags */
  317 + /* The zero index is used to indicate end-of-list */
  318 +#define UNUSED 0
  319 + { 0, 0, 0, 0, 0, 0 },
  320 +
  321 + /* The plain integer register fields */
  322 +#define RA (UNUSED + 1)
  323 + { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
  324 +#define RB (RA + 1)
  325 + { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
  326 +#define RC (RB + 1)
  327 + { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
  328 +
  329 + /* The plain fp register fields */
  330 +#define FA (RC + 1)
  331 + { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
  332 +#define FB (FA + 1)
  333 + { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
  334 +#define FC (FB + 1)
  335 + { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
  336 +
  337 + /* The integer registers when they are ZERO */
  338 +#define ZA (FC + 1)
  339 + { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
  340 +#define ZB (ZA + 1)
  341 + { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
  342 +#define ZC (ZB + 1)
  343 + { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
  344 +
  345 + /* The RB field when it needs parentheses */
  346 +#define PRB (ZC + 1)
  347 + { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
  348 +
  349 + /* The RB field when it needs parentheses _and_ a preceding comma */
  350 +#define CPRB (PRB + 1)
  351 + { 5, 16, 0,
  352 + AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
  353 +
  354 + /* The RB field when it must be the same as the RA field */
  355 +#define RBA (CPRB + 1)
  356 + { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
  357 +
  358 + /* The RC field when it must be the same as the RB field */
  359 +#define RCA (RBA + 1)
  360 + { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
  361 +
  362 + /* The RC field when it can *default* to RA */
  363 +#define DRC1 (RCA + 1)
  364 + { 5, 0, 0,
  365 + AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
  366 +
  367 + /* The RC field when it can *default* to RB */
  368 +#define DRC2 (DRC1 + 1)
  369 + { 5, 0, 0,
  370 + AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
  371 +
  372 + /* The FC field when it can *default* to RA */
  373 +#define DFC1 (DRC2 + 1)
  374 + { 5, 0, 0,
  375 + AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
  376 +
  377 + /* The FC field when it can *default* to RB */
  378 +#define DFC2 (DFC1 + 1)
  379 + { 5, 0, 0,
  380 + AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
  381 +
  382 + /* The unsigned 8-bit literal of Operate format insns */
  383 +#define LIT (DFC2 + 1)
  384 + { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
  385 +
  386 + /* The signed 16-bit displacement of Memory format insns. From here
  387 + we can't tell what relocation should be used, so don't use a default. */
  388 +#define MDISP (LIT + 1)
  389 + { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
  390 +
  391 + /* The signed "23-bit" aligned displacement of Branch format insns */
  392 +#define BDISP (MDISP + 1)
  393 + { 21, 0, BFD_RELOC_23_PCREL_S2,
  394 + AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
  395 +
  396 + /* The 26-bit PALcode function */
  397 +#define PALFN (BDISP + 1)
  398 + { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
  399 +
  400 + /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
  401 +#define JMPHINT (PALFN + 1)
  402 + { 14, 0, BFD_RELOC_ALPHA_HINT,
  403 + AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
  404 + insert_jhint, extract_jhint },
  405 +
  406 + /* The optional hint to RET/JSR_COROUTINE */
  407 +#define RETHINT (JMPHINT + 1)
  408 + { 14, 0, -RETHINT,
  409 + AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
  410 +
  411 + /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
  412 +#define EV4HWDISP (RETHINT + 1)
  413 +#define EV6HWDISP (EV4HWDISP)
  414 + { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
  415 +
  416 + /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
  417 +#define EV4HWINDEX (EV4HWDISP + 1)
  418 + { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
  419 +
  420 + /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
  421 + that occur in DEC PALcode. */
  422 +#define EV4EXTHWINDEX (EV4HWINDEX + 1)
  423 + { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
  424 +
  425 + /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
  426 +#define EV5HWDISP (EV4EXTHWINDEX + 1)
  427 + { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
  428 +
  429 + /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
  430 +#define EV5HWINDEX (EV5HWDISP + 1)
  431 + { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
  432 +
  433 + /* The 16-bit combined index/scoreboard mask for the ev6
  434 + hw_m[ft]pr (pal19/pal1d) insns */
  435 +#define EV6HWINDEX (EV5HWINDEX + 1)
  436 + { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
  437 +
  438 + /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
  439 +#define EV6HWJMPHINT (EV6HWINDEX+ 1)
  440 + { 8, 0, -EV6HWJMPHINT,
  441 + AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
  442 + insert_ev6hwjhint, extract_ev6hwjhint }
  443 +};
  444 +
  445 +const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
  446 +
  447 +/* The RB field when it is the same as the RA field in the same insn.
  448 + This operand is marked fake. The insertion function just copies
  449 + the RA field into the RB field, and the extraction function just
  450 + checks that the fields are the same. */
  451 +
  452 +/*ARGSUSED*/
  453 +static unsigned
  454 +insert_rba(insn, value, errmsg)
  455 + unsigned insn;
  456 + int value ATTRIBUTE_UNUSED;
  457 + const char **errmsg ATTRIBUTE_UNUSED;
  458 +{
  459 + return insn | (((insn >> 21) & 0x1f) << 16);
  460 +}
  461 +
  462 +static int
  463 +extract_rba(insn, invalid)
  464 + unsigned insn;
  465 + int *invalid;
  466 +{
  467 + if (invalid != (int *) NULL
  468 + && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
  469 + *invalid = 1;
  470 + return 0;
  471 +}
  472 +
  473 +
  474 +/* The same for the RC field */
  475 +
  476 +/*ARGSUSED*/
  477 +static unsigned
  478 +insert_rca(insn, value, errmsg)
  479 + unsigned insn;
  480 + int value ATTRIBUTE_UNUSED;
  481 + const char **errmsg ATTRIBUTE_UNUSED;
  482 +{
  483 + return insn | ((insn >> 21) & 0x1f);
  484 +}
  485 +
  486 +static int
  487 +extract_rca(insn, invalid)
  488 + unsigned insn;
  489 + int *invalid;
  490 +{
  491 + if (invalid != (int *) NULL
  492 + && ((insn >> 21) & 0x1f) != (insn & 0x1f))
  493 + *invalid = 1;
  494 + return 0;
  495 +}
  496 +
  497 +
  498 +/* Fake arguments in which the registers must be set to ZERO */
  499 +
  500 +/*ARGSUSED*/
  501 +static unsigned
  502 +insert_za(insn, value, errmsg)
  503 + unsigned insn;
  504 + int value ATTRIBUTE_UNUSED;
  505 + const char **errmsg ATTRIBUTE_UNUSED;
  506 +{
  507 + return insn | (31 << 21);
  508 +}
  509 +
  510 +static int
  511 +extract_za(insn, invalid)
  512 + unsigned insn;
  513 + int *invalid;
  514 +{
  515 + if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
  516 + *invalid = 1;
  517 + return 0;
  518 +}
  519 +
  520 +/*ARGSUSED*/
  521 +static unsigned
  522 +insert_zb(insn, value, errmsg)
  523 + unsigned insn;
  524 + int value ATTRIBUTE_UNUSED;
  525 + const char **errmsg ATTRIBUTE_UNUSED;
  526 +{
  527 + return insn | (31 << 16);
  528 +}
  529 +
  530 +static int
  531 +extract_zb(insn, invalid)
  532 + unsigned insn;
  533 + int *invalid;
  534 +{
  535 + if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
  536 + *invalid = 1;
  537 + return 0;
  538 +}
  539 +
  540 +/*ARGSUSED*/
  541 +static unsigned
  542 +insert_zc(insn, value, errmsg)
  543 + unsigned insn;
  544 + int value ATTRIBUTE_UNUSED;
  545 + const char **errmsg ATTRIBUTE_UNUSED;
  546 +{
  547 + return insn | 31;
  548 +}
  549 +
  550 +static int
  551 +extract_zc(insn, invalid)
  552 + unsigned insn;
  553 + int *invalid;
  554 +{
  555 + if (invalid != (int *) NULL && (insn & 0x1f) != 31)
  556 + *invalid = 1;
  557 + return 0;
  558 +}
  559 +
  560 +
  561 +/* The displacement field of a Branch format insn. */
  562 +
  563 +static unsigned
  564 +insert_bdisp(insn, value, errmsg)
  565 + unsigned insn;
  566 + int value;
  567 + const char **errmsg;
  568 +{
  569 + if (errmsg != (const char **)NULL && (value & 3))
  570 + *errmsg = _("branch operand unaligned");
  571 + return insn | ((value / 4) & 0x1FFFFF);
  572 +}
  573 +
  574 +/*ARGSUSED*/
  575 +static int
  576 +extract_bdisp(insn, invalid)
  577 + unsigned insn;
  578 + int *invalid ATTRIBUTE_UNUSED;
  579 +{
  580 + return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
  581 +}
  582 +
  583 +
  584 +/* The hint field of a JMP/JSR insn. */
  585 +
  586 +static unsigned
  587 +insert_jhint(insn, value, errmsg)
  588 + unsigned insn;
  589 + int value;
  590 + const char **errmsg;
  591 +{
  592 + if (errmsg != (const char **)NULL && (value & 3))
  593 + *errmsg = _("jump hint unaligned");
  594 + return insn | ((value / 4) & 0x3FFF);
  595 +}
  596 +
  597 +/*ARGSUSED*/
  598 +static int
  599 +extract_jhint(insn, invalid)
  600 + unsigned insn;
  601 + int *invalid ATTRIBUTE_UNUSED;
  602 +{
  603 + return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
  604 +}
  605 +
  606 +/* The hint field of an EV6 HW_JMP/JSR insn. */
  607 +
  608 +static unsigned
  609 +insert_ev6hwjhint(insn, value, errmsg)
  610 + unsigned insn;
  611 + int value;
  612 + const char **errmsg;
  613 +{
  614 + if (errmsg != (const char **)NULL && (value & 3))
  615 + *errmsg = _("jump hint unaligned");
  616 + return insn | ((value / 4) & 0x1FFF);
  617 +}
  618 +
  619 +/*ARGSUSED*/
  620 +static int
  621 +extract_ev6hwjhint(insn, invalid)
  622 + unsigned insn;
  623 + int *invalid ATTRIBUTE_UNUSED;
  624 +{
  625 + return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
  626 +}
  627 +
  628 +
  629 +/* Macros used to form opcodes */
  630 +
  631 +/* The main opcode */
  632 +#define OP(x) (((x) & 0x3F) << 26)
  633 +#define OP_MASK 0xFC000000
  634 +
  635 +/* Branch format instructions */
  636 +#define BRA_(oo) OP(oo)
  637 +#define BRA_MASK OP_MASK
  638 +#define BRA(oo) BRA_(oo), BRA_MASK
  639 +
  640 +/* Floating point format instructions */
  641 +#define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5))
  642 +#define FP_MASK (OP_MASK | 0xFFE0)
  643 +#define FP(oo,fff) FP_(oo,fff), FP_MASK
  644 +
  645 +/* Memory format instructions */
  646 +#define MEM_(oo) OP(oo)
  647 +#define MEM_MASK OP_MASK
  648 +#define MEM(oo) MEM_(oo), MEM_MASK
  649 +
  650 +/* Memory/Func Code format instructions */
  651 +#define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF))
  652 +#define MFC_MASK (OP_MASK | 0xFFFF)
  653 +#define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK
  654 +
  655 +/* Memory/Branch format instructions */
  656 +#define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14))
  657 +#define MBR_MASK (OP_MASK | 0xC000)
  658 +#define MBR(oo,h) MBR_(oo,h), MBR_MASK
  659 +
  660 +/* Operate format instructions. The OPRL variant specifies a
  661 + literal second argument. */
  662 +#define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5))
  663 +#define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000)
  664 +#define OPR_MASK (OP_MASK | 0x1FE0)
  665 +#define OPR(oo,ff) OPR_(oo,ff), OPR_MASK
  666 +#define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK
  667 +
  668 +/* Generic PALcode format instructions */
  669 +#define PCD_(oo) OP(oo)
  670 +#define PCD_MASK OP_MASK
  671 +#define PCD(oo) PCD_(oo), PCD_MASK
  672 +
  673 +/* Specific PALcode instructions */
  674 +#define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF))
  675 +#define SPCD_MASK 0xFFFFFFFF
  676 +#define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK
  677 +
  678 +/* Hardware memory (hw_{ld,st}) instructions */
  679 +#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
  680 +#define EV4HWMEM_MASK (OP_MASK | 0xF000)
  681 +#define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK
  682 +
  683 +#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10))
  684 +#define EV5HWMEM_MASK (OP_MASK | 0xF800)
  685 +#define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK
  686 +
  687 +#define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
  688 +#define EV6HWMEM_MASK (OP_MASK | 0xF000)
  689 +#define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK
  690 +
  691 +#define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13))
  692 +#define EV6HWMBR_MASK (OP_MASK | 0xE000)
  693 +#define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK
  694 +
  695 +/* Abbreviations for instruction subsets. */
  696 +#define BASE AXP_OPCODE_BASE
  697 +#define EV4 AXP_OPCODE_EV4
  698 +#define EV5 AXP_OPCODE_EV5
  699 +#define EV6 AXP_OPCODE_EV6
  700 +#define BWX AXP_OPCODE_BWX
  701 +#define CIX AXP_OPCODE_CIX
  702 +#define MAX AXP_OPCODE_MAX
  703 +
  704 +/* Common combinations of arguments */
  705 +#define ARG_NONE { 0 }
  706 +#define ARG_BRA { RA, BDISP }
  707 +#define ARG_FBRA { FA, BDISP }
  708 +#define ARG_FP { FA, FB, DFC1 }
  709 +#define ARG_FPZ1 { ZA, FB, DFC1 }
  710 +#define ARG_MEM { RA, MDISP, PRB }
  711 +#define ARG_FMEM { FA, MDISP, PRB }
  712 +#define ARG_OPR { RA, RB, DRC1 }
  713 +#define ARG_OPRL { RA, LIT, DRC1 }
  714 +#define ARG_OPRZ1 { ZA, RB, DRC1 }
  715 +#define ARG_OPRLZ1 { ZA, LIT, RC }
  716 +#define ARG_PCD { PALFN }
  717 +#define ARG_EV4HWMEM { RA, EV4HWDISP, PRB }
  718 +#define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX }
  719 +#define ARG_EV5HWMEM { RA, EV5HWDISP, PRB }
  720 +#define ARG_EV6HWMEM { RA, EV6HWDISP, PRB }
  721 +
  722 +/* The opcode table.
  723 +
  724 + The format of the opcode table is:
  725 +
  726 + NAME OPCODE MASK { OPERANDS }
  727 +
  728 + NAME is the name of the instruction.
  729 +
  730 + OPCODE is the instruction opcode.
  731 +
  732 + MASK is the opcode mask; this is used to tell the disassembler
  733 + which bits in the actual opcode must match OPCODE.
  734 +
  735 + OPERANDS is the list of operands.
  736 +
  737 + The preceding macros merge the text of the OPCODE and MASK fields.
  738 +
  739 + The disassembler reads the table in order and prints the first
  740 + instruction which matches, so this table is sorted to put more
  741 + specific instructions before more general instructions.
  742 +
  743 + Otherwise, it is sorted by major opcode and minor function code.
  744 +
  745 + There are three classes of not-really-instructions in this table:
  746 +
  747 + ALIAS is another name for another instruction. Some of
  748 + these come from the Architecture Handbook, some
  749 + come from the original gas opcode tables. In all
  750 + cases, the functionality of the opcode is unchanged.
  751 +
  752 + PSEUDO a stylized code form endorsed by Chapter A.4 of the
  753 + Architecture Handbook.
  754 +
  755 + EXTRA a stylized code form found in the original gas tables.
  756 +
  757 + And two annotations:
  758 +
  759 + EV56 BUT opcodes that are officially introduced as of the ev56,
  760 + but with defined results on previous implementations.
  761 +
  762 + EV56 UNA opcodes that were introduced as of the ev56 with
  763 + presumably undefined results on previous implementations
  764 + that were not assigned to a particular extension.
  765 +*/
  766 +
  767 +const struct alpha_opcode alpha_opcodes[] = {
  768 + { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE },
  769 + { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE },
  770 + { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE },
  771 + { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE },
  772 + { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE },
  773 + { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE },
  774 + { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE },
  775 + { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE },
  776 + { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE },
  777 + { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE },
  778 + { "call_pal", PCD(0x00), BASE, ARG_PCD },
  779 + { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */
  780 +
  781 + { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */
  782 + { "lda", MEM(0x08), BASE, ARG_MEM },
  783 + { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */
  784 + { "ldah", MEM(0x09), BASE, ARG_MEM },
  785 + { "ldbu", MEM(0x0A), BWX, ARG_MEM },
  786 + { "unop", MEM_(0x0B) | (30 << 16),
  787 + MEM_MASK, BASE, { ZA } }, /* pseudo */
  788 + { "ldq_u", MEM(0x0B), BASE, ARG_MEM },
  789 + { "ldwu", MEM(0x0C), BWX, ARG_MEM },
  790 + { "stw", MEM(0x0D), BWX, ARG_MEM },
  791 + { "stb", MEM(0x0E), BWX, ARG_MEM },
  792 + { "stq_u", MEM(0x0F), BASE, ARG_MEM },
  793 +
  794 + { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */
  795 + { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */
  796 + { "addl", OPR(0x10,0x00), BASE, ARG_OPR },
  797 + { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL },
  798 + { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR },
  799 + { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL },
  800 + { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */
  801 + { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */
  802 + { "subl", OPR(0x10,0x09), BASE, ARG_OPR },
  803 + { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL },
  804 + { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR },
  805 + { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL },
  806 + { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR },
  807 + { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL },
  808 + { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR },
  809 + { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL },
  810 + { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR },
  811 + { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL },
  812 + { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR },
  813 + { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL },
  814 + { "addq", OPR(0x10,0x20), BASE, ARG_OPR },
  815 + { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL },
  816 + { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR },
  817 + { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL },
  818 + { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */
  819 + { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */
  820 + { "subq", OPR(0x10,0x29), BASE, ARG_OPR },
  821 + { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL },
  822 + { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR },
  823 + { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL },
  824 + { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR },
  825 + { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL },
  826 + { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR },
  827 + { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL },
  828 + { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR },
  829 + { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL },
  830 + { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR },
  831 + { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL },
  832 + { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR },
  833 + { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL },
  834 + { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */
  835 + { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */
  836 + { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR },
  837 + { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL },
  838 + { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR },
  839 + { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL },
  840 + { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR },
  841 + { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL },
  842 + { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */
  843 + { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */
  844 + { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR },
  845 + { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL },
  846 + { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR },
  847 + { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL },
  848 +
  849 + { "and", OPR(0x11,0x00), BASE, ARG_OPR },
  850 + { "and", OPRL(0x11,0x00), BASE, ARG_OPRL },
  851 + { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */
  852 + { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */
  853 + { "bic", OPR(0x11,0x08), BASE, ARG_OPR },
  854 + { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL },
  855 + { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR },
  856 + { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL },
  857 + { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR },
  858 + { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL },
  859 + { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
  860 + { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
  861 + { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
  862 + { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */
  863 + { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
  864 + { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */
  865 + { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */
  866 + { "bis", OPR(0x11,0x20), BASE, ARG_OPR },
  867 + { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL },
  868 + { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR },
  869 + { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL },
  870 + { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR },
  871 + { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL },
  872 + { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */
  873 + { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */
  874 + { "ornot", OPR(0x11,0x28), BASE, ARG_OPR },
  875 + { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL },
  876 + { "xor", OPR(0x11,0x40), BASE, ARG_OPR },
  877 + { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL },
  878 + { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR },
  879 + { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL },
  880 + { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR },
  881 + { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL },
  882 + { "eqv", OPR(0x11,0x48), BASE, ARG_OPR },
  883 + { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL },
  884 + { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */
  885 + { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */
  886 + { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */
  887 + { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */
  888 + { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR },
  889 + { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL },
  890 + { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR },
  891 + { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL },
  892 + { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13),
  893 + 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */
  894 +
  895 + { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR },
  896 + { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL },
  897 + { "extbl", OPR(0x12,0x06), BASE, ARG_OPR },
  898 + { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL },
  899 + { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR },
  900 + { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL },
  901 + { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR },
  902 + { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL },
  903 + { "extwl", OPR(0x12,0x16), BASE, ARG_OPR },
  904 + { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL },
  905 + { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR },
  906 + { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL },
  907 + { "mskll", OPR(0x12,0x22), BASE, ARG_OPR },
  908 + { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL },
  909 + { "extll", OPR(0x12,0x26), BASE, ARG_OPR },
  910 + { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL },
  911 + { "insll", OPR(0x12,0x2B), BASE, ARG_OPR },
  912 + { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL },
  913 + { "zap", OPR(0x12,0x30), BASE, ARG_OPR },
  914 + { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL },
  915 + { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR },
  916 + { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL },
  917 + { "mskql", OPR(0x12,0x32), BASE, ARG_OPR },
  918 + { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL },
  919 + { "srl", OPR(0x12,0x34), BASE, ARG_OPR },
  920 + { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL },
  921 + { "extql", OPR(0x12,0x36), BASE, ARG_OPR },
  922 + { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL },
  923 + { "sll", OPR(0x12,0x39), BASE, ARG_OPR },
  924 + { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL },
  925 + { "insql", OPR(0x12,0x3B), BASE, ARG_OPR },
  926 + { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL },
  927 + { "sra", OPR(0x12,0x3C), BASE, ARG_OPR },
  928 + { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL },
  929 + { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR },
  930 + { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL },
  931 + { "inswh", OPR(0x12,0x57), BASE, ARG_OPR },
  932 + { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL },
  933 + { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR },
  934 + { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL },
  935 + { "msklh", OPR(0x12,0x62), BASE, ARG_OPR },
  936 + { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL },
  937 + { "inslh", OPR(0x12,0x67), BASE, ARG_OPR },
  938 + { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL },
  939 + { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR },
  940 + { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL },
  941 + { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR },
  942 + { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL },
  943 + { "insqh", OPR(0x12,0x77), BASE, ARG_OPR },
  944 + { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL },
  945 + { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR },
  946 + { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL },
  947 +
  948 + { "mull", OPR(0x13,0x00), BASE, ARG_OPR },
  949 + { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL },
  950 + { "mulq", OPR(0x13,0x20), BASE, ARG_OPR },
  951 + { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL },
  952 + { "umulh", OPR(0x13,0x30), BASE, ARG_OPR },
  953 + { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL },
  954 + { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR },
  955 + { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL },
  956 + { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR },
  957 + { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL },
  958 +
  959 + { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } },
  960 + { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 },
  961 + { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 },
  962 + { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } },
  963 + { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } },
  964 + { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 },
  965 + { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 },
  966 + { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 },
  967 + { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 },
  968 + { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 },
  969 + { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 },
  970 + { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 },
  971 + { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 },
  972 + { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 },
  973 + { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 },
  974 + { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 },
  975 + { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 },
  976 + { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 },
  977 + { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 },
  978 + { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 },
  979 + { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 },
  980 + { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 },
  981 + { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 },
  982 + { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 },
  983 + { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 },
  984 + { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 },
  985 + { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 },
  986 + { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 },
  987 + { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 },
  988 + { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 },
  989 + { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 },
  990 + { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 },
  991 + { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 },
  992 + { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 },
  993 + { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 },
  994 + { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 },
  995 + { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 },
  996 + { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 },
  997 + { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 },
  998 + { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 },
  999 + { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 },
  1000 + { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 },
  1001 + { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 },
  1002 + { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 },
  1003 + { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 },
  1004 + { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 },
  1005 + { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 },
  1006 + { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 },
  1007 + { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 },
  1008 + { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 },
  1009 + { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 },
  1010 +
  1011 + { "addf/c", FP(0x15,0x000), BASE, ARG_FP },
  1012 + { "subf/c", FP(0x15,0x001), BASE, ARG_FP },
  1013 + { "mulf/c", FP(0x15,0x002), BASE, ARG_FP },
  1014 + { "divf/c", FP(0x15,0x003), BASE, ARG_FP },
  1015 + { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 },
  1016 + { "addg/c", FP(0x15,0x020), BASE, ARG_FP },
  1017 + { "subg/c", FP(0x15,0x021), BASE, ARG_FP },
  1018 + { "mulg/c", FP(0x15,0x022), BASE, ARG_FP },
  1019 + { "divg/c", FP(0x15,0x023), BASE, ARG_FP },
  1020 + { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 },
  1021 + { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 },
  1022 + { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 },
  1023 + { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 },
  1024 + { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 },
  1025 + { "addf", FP(0x15,0x080), BASE, ARG_FP },
  1026 + { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */
  1027 + { "subf", FP(0x15,0x081), BASE, ARG_FP },
  1028 + { "mulf", FP(0x15,0x082), BASE, ARG_FP },
  1029 + { "divf", FP(0x15,0x083), BASE, ARG_FP },
  1030 + { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 },
  1031 + { "addg", FP(0x15,0x0A0), BASE, ARG_FP },
  1032 + { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */
  1033 + { "subg", FP(0x15,0x0A1), BASE, ARG_FP },
  1034 + { "mulg", FP(0x15,0x0A2), BASE, ARG_FP },
  1035 + { "divg", FP(0x15,0x0A3), BASE, ARG_FP },
  1036 + { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP },
  1037 + { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP },
  1038 + { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP },
  1039 + { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 },
  1040 + { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 },
  1041 + { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 },
  1042 + { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 },
  1043 + { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 },
  1044 + { "addf/uc", FP(0x15,0x100), BASE, ARG_FP },
  1045 + { "subf/uc", FP(0x15,0x101), BASE, ARG_FP },
  1046 + { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP },
  1047 + { "divf/uc", FP(0x15,0x103), BASE, ARG_FP },
  1048 + { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 },
  1049 + { "addg/uc", FP(0x15,0x120), BASE, ARG_FP },
  1050 + { "subg/uc", FP(0x15,0x121), BASE, ARG_FP },
  1051 + { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP },
  1052 + { "divg/uc", FP(0x15,0x123), BASE, ARG_FP },
  1053 + { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 },
  1054 + { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 },
  1055 + { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 },
  1056 + { "addf/u", FP(0x15,0x180), BASE, ARG_FP },
  1057 + { "subf/u", FP(0x15,0x181), BASE, ARG_FP },
  1058 + { "mulf/u", FP(0x15,0x182), BASE, ARG_FP },
  1059 + { "divf/u", FP(0x15,0x183), BASE, ARG_FP },
  1060 + { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 },
  1061 + { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP },
  1062 + { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP },
  1063 + { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP },
  1064 + { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP },
  1065 + { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 },
  1066 + { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 },
  1067 + { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 },
  1068 + { "addf/sc", FP(0x15,0x400), BASE, ARG_FP },
  1069 + { "subf/sc", FP(0x15,0x401), BASE, ARG_FP },
  1070 + { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP },
  1071 + { "divf/sc", FP(0x15,0x403), BASE, ARG_FP },
  1072 + { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 },
  1073 + { "addg/sc", FP(0x15,0x420), BASE, ARG_FP },
  1074 + { "subg/sc", FP(0x15,0x421), BASE, ARG_FP },
  1075 + { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP },
  1076 + { "divg/sc", FP(0x15,0x423), BASE, ARG_FP },
  1077 + { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 },
  1078 + { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 },
  1079 + { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 },
  1080 + { "addf/s", FP(0x15,0x480), BASE, ARG_FP },
  1081 + { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */
  1082 + { "subf/s", FP(0x15,0x481), BASE, ARG_FP },
  1083 + { "mulf/s", FP(0x15,0x482), BASE, ARG_FP },
  1084 + { "divf/s", FP(0x15,0x483), BASE, ARG_FP },
  1085 + { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 },
  1086 + { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP },
  1087 + { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */
  1088 + { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP },
  1089 + { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP },
  1090 + { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP },
  1091 + { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP },
  1092 + { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP },
  1093 + { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP },
  1094 + { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 },
  1095 + { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 },
  1096 + { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 },
  1097 + { "addf/suc", FP(0x15,0x500), BASE, ARG_FP },
  1098 + { "subf/suc", FP(0x15,0x501), BASE, ARG_FP },
  1099 + { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP },
  1100 + { "divf/suc", FP(0x15,0x503), BASE, ARG_FP },
  1101 + { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 },
  1102 + { "addg/suc", FP(0x15,0x520), BASE, ARG_FP },
  1103 + { "subg/suc", FP(0x15,0x521), BASE, ARG_FP },
  1104 + { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP },
  1105 + { "divg/suc", FP(0x15,0x523), BASE, ARG_FP },
  1106 + { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 },
  1107 + { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 },
  1108 + { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 },
  1109 + { "addf/su", FP(0x15,0x580), BASE, ARG_FP },
  1110 + { "subf/su", FP(0x15,0x581), BASE, ARG_FP },
  1111 + { "mulf/su", FP(0x15,0x582), BASE, ARG_FP },
  1112 + { "divf/su", FP(0x15,0x583), BASE, ARG_FP },
  1113 + { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 },
  1114 + { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP },
  1115 + { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP },
  1116 + { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP },
  1117 + { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP },
  1118 + { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 },
  1119 + { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 },
  1120 + { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 },
  1121 +
  1122 + { "adds/c", FP(0x16,0x000), BASE, ARG_FP },
  1123 + { "subs/c", FP(0x16,0x001), BASE, ARG_FP },
  1124 + { "muls/c", FP(0x16,0x002), BASE, ARG_FP },
  1125 + { "divs/c", FP(0x16,0x003), BASE, ARG_FP },
  1126 + { "addt/c", FP(0x16,0x020), BASE, ARG_FP },
  1127 + { "subt/c", FP(0x16,0x021), BASE, ARG_FP },
  1128 + { "mult/c", FP(0x16,0x022), BASE, ARG_FP },
  1129 + { "divt/c", FP(0x16,0x023), BASE, ARG_FP },
  1130 + { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 },
  1131 + { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 },
  1132 + { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 },
  1133 + { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 },
  1134 + { "adds/m", FP(0x16,0x040), BASE, ARG_FP },
  1135 + { "subs/m", FP(0x16,0x041), BASE, ARG_FP },
  1136 + { "muls/m", FP(0x16,0x042), BASE, ARG_FP },
  1137 + { "divs/m", FP(0x16,0x043), BASE, ARG_FP },
  1138 + { "addt/m", FP(0x16,0x060), BASE, ARG_FP },
  1139 + { "subt/m", FP(0x16,0x061), BASE, ARG_FP },
  1140 + { "mult/m", FP(0x16,0x062), BASE, ARG_FP },
  1141 + { "divt/m", FP(0x16,0x063), BASE, ARG_FP },
  1142 + { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 },
  1143 + { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 },
  1144 + { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 },
  1145 + { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 },
  1146 + { "adds", FP(0x16,0x080), BASE, ARG_FP },
  1147 + { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */
  1148 + { "subs", FP(0x16,0x081), BASE, ARG_FP },
  1149 + { "muls", FP(0x16,0x082), BASE, ARG_FP },
  1150 + { "divs", FP(0x16,0x083), BASE, ARG_FP },
  1151 + { "addt", FP(0x16,0x0A0), BASE, ARG_FP },
  1152 + { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */
  1153 + { "subt", FP(0x16,0x0A1), BASE, ARG_FP },
  1154 + { "mult", FP(0x16,0x0A2), BASE, ARG_FP },
  1155 + { "divt", FP(0x16,0x0A3), BASE, ARG_FP },
  1156 + { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP },
  1157 + { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP },
  1158 + { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP },
  1159 + { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP },
  1160 + { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 },
  1161 + { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 },
  1162 + { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 },
  1163 + { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 },
  1164 + { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP },
  1165 + { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP },
  1166 + { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP },
  1167 + { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP },
  1168 + { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP },
  1169 + { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP },
  1170 + { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP },
  1171 + { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP },
  1172 + { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 },
  1173 + { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 },
  1174 + { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 },
  1175 + { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 },
  1176 + { "adds/uc", FP(0x16,0x100), BASE, ARG_FP },
  1177 + { "subs/uc", FP(0x16,0x101), BASE, ARG_FP },
  1178 + { "muls/uc", FP(0x16,0x102), BASE, ARG_FP },
  1179 + { "divs/uc", FP(0x16,0x103), BASE, ARG_FP },
  1180 + { "addt/uc", FP(0x16,0x120), BASE, ARG_FP },
  1181 + { "subt/uc", FP(0x16,0x121), BASE, ARG_FP },
  1182 + { "mult/uc", FP(0x16,0x122), BASE, ARG_FP },
  1183 + { "divt/uc", FP(0x16,0x123), BASE, ARG_FP },
  1184 + { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 },
  1185 + { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 },
  1186 + { "adds/um", FP(0x16,0x140), BASE, ARG_FP },
  1187 + { "subs/um", FP(0x16,0x141), BASE, ARG_FP },
  1188 + { "muls/um", FP(0x16,0x142), BASE, ARG_FP },
  1189 + { "divs/um", FP(0x16,0x143), BASE, ARG_FP },
  1190 + { "addt/um", FP(0x16,0x160), BASE, ARG_FP },
  1191 + { "subt/um", FP(0x16,0x161), BASE, ARG_FP },
  1192 + { "mult/um", FP(0x16,0x162), BASE, ARG_FP },
  1193 + { "divt/um", FP(0x16,0x163), BASE, ARG_FP },
  1194 + { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 },
  1195 + { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 },
  1196 + { "adds/u", FP(0x16,0x180), BASE, ARG_FP },
  1197 + { "subs/u", FP(0x16,0x181), BASE, ARG_FP },
  1198 + { "muls/u", FP(0x16,0x182), BASE, ARG_FP },
  1199 + { "divs/u", FP(0x16,0x183), BASE, ARG_FP },
  1200 + { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP },
  1201 + { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP },
  1202 + { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP },
  1203 + { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP },
  1204 + { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 },
  1205 + { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 },
  1206 + { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP },
  1207 + { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP },
  1208 + { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP },
  1209 + { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP },
  1210 + { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP },
  1211 + { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP },
  1212 + { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP },
  1213 + { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP },
  1214 + { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 },
  1215 + { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 },
  1216 + { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 },
  1217 + { "adds/suc", FP(0x16,0x500), BASE, ARG_FP },
  1218 + { "subs/suc", FP(0x16,0x501), BASE, ARG_FP },
  1219 + { "muls/suc", FP(0x16,0x502), BASE, ARG_FP },
  1220 + { "divs/suc", FP(0x16,0x503), BASE, ARG_FP },
  1221 + { "addt/suc", FP(0x16,0x520), BASE, ARG_FP },
  1222 + { "subt/suc", FP(0x16,0x521), BASE, ARG_FP },
  1223 + { "mult/suc", FP(0x16,0x522), BASE, ARG_FP },
  1224 + { "divt/suc", FP(0x16,0x523), BASE, ARG_FP },
  1225 + { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 },
  1226 + { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 },
  1227 + { "adds/sum", FP(0x16,0x540), BASE, ARG_FP },
  1228 + { "subs/sum", FP(0x16,0x541), BASE, ARG_FP },
  1229 + { "muls/sum", FP(0x16,0x542), BASE, ARG_FP },
  1230 + { "divs/sum", FP(0x16,0x543), BASE, ARG_FP },
  1231 + { "addt/sum", FP(0x16,0x560), BASE, ARG_FP },
  1232 + { "subt/sum", FP(0x16,0x561), BASE, ARG_FP },
  1233 + { "mult/sum", FP(0x16,0x562), BASE, ARG_FP },
  1234 + { "divt/sum", FP(0x16,0x563), BASE, ARG_FP },
  1235 + { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 },
  1236 + { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 },
  1237 + { "adds/su", FP(0x16,0x580), BASE, ARG_FP },
  1238 + { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */
  1239 + { "subs/su", FP(0x16,0x581), BASE, ARG_FP },
  1240 + { "muls/su", FP(0x16,0x582), BASE, ARG_FP },
  1241 + { "divs/su", FP(0x16,0x583), BASE, ARG_FP },
  1242 + { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP },
  1243 + { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */
  1244 + { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP },
  1245 + { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP },
  1246 + { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP },
  1247 + { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP },
  1248 + { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP },
  1249 + { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP },
  1250 + { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP },
  1251 + { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 },
  1252 + { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 },
  1253 + { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP },
  1254 + { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP },
  1255 + { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP },
  1256 + { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP },
  1257 + { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP },
  1258 + { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP },
  1259 + { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP },
  1260 + { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP },
  1261 + { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 },
  1262 + { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 },
  1263 + { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 },
  1264 + { "adds/suic", FP(0x16,0x700), BASE, ARG_FP },
  1265 + { "subs/suic", FP(0x16,0x701), BASE, ARG_FP },
  1266 + { "muls/suic", FP(0x16,0x702), BASE, ARG_FP },
  1267 + { "divs/suic", FP(0x16,0x703), BASE, ARG_FP },
  1268 + { "addt/suic", FP(0x16,0x720), BASE, ARG_FP },
  1269 + { "subt/suic", FP(0x16,0x721), BASE, ARG_FP },
  1270 + { "mult/suic", FP(0x16,0x722), BASE, ARG_FP },
  1271 + { "divt/suic", FP(0x16,0x723), BASE, ARG_FP },
  1272 + { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 },
  1273 + { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 },
  1274 + { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 },
  1275 + { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 },
  1276 + { "adds/suim", FP(0x16,0x740), BASE, ARG_FP },
  1277 + { "subs/suim", FP(0x16,0x741), BASE, ARG_FP },
  1278 + { "muls/suim", FP(0x16,0x742), BASE, ARG_FP },
  1279 + { "divs/suim", FP(0x16,0x743), BASE, ARG_FP },
  1280 + { "addt/suim", FP(0x16,0x760), BASE, ARG_FP },
  1281 + { "subt/suim", FP(0x16,0x761), BASE, ARG_FP },
  1282 + { "mult/suim", FP(0x16,0x762), BASE, ARG_FP },
  1283 + { "divt/suim", FP(0x16,0x763), BASE, ARG_FP },
  1284 + { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 },
  1285 + { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 },
  1286 + { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 },
  1287 + { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 },
  1288 + { "adds/sui", FP(0x16,0x780), BASE, ARG_FP },
  1289 + { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */
  1290 + { "subs/sui", FP(0x16,0x781), BASE, ARG_FP },
  1291 + { "muls/sui", FP(0x16,0x782), BASE, ARG_FP },
  1292 + { "divs/sui", FP(0x16,0x783), BASE, ARG_FP },
  1293 + { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP },
  1294 + { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */
  1295 + { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP },
  1296 + { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP },
  1297 + { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP },
  1298 + { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 },
  1299 + { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 },
  1300 + { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 },
  1301 + { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 },
  1302 + { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP },
  1303 + { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP },
  1304 + { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP },
  1305 + { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP },
  1306 + { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP },
  1307 + { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP },
  1308 + { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP },
  1309 + { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP },
  1310 + { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 },
  1311 + { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 },
  1312 + { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 },
  1313 + { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 },
  1314 +
  1315 + { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 },
  1316 + { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */
  1317 + { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */
  1318 + { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */
  1319 + { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */
  1320 + { "cpys", FP(0x17,0x020), BASE, ARG_FP },
  1321 + { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */
  1322 + { "cpysn", FP(0x17,0x021), BASE, ARG_FP },
  1323 + { "cpyse", FP(0x17,0x022), BASE, ARG_FP },
  1324 + { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } },
  1325 + { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } },
  1326 + { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP },
  1327 + { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP },
  1328 + { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP },
  1329 + { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP },
  1330 + { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP },
  1331 + { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP },
  1332 + { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 },
  1333 + { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 },
  1334 + { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 },
  1335 +
  1336 + { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE },
  1337 + { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */
  1338 + { "excb", MFC(0x18,0x0400), BASE, ARG_NONE },
  1339 + { "mb", MFC(0x18,0x4000), BASE, ARG_NONE },
  1340 + { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE },
  1341 + { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } },
  1342 + { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } },
  1343 + { "rpcc", MFC(0x18,0xC000), BASE, { RA } },
  1344 + { "rc", MFC(0x18,0xE000), BASE, { RA } },
  1345 + { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */
  1346 + { "rs", MFC(0x18,0xF000), BASE, { RA } },
  1347 + { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */
  1348 + { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */
  1349 +
  1350 + { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
  1351 + { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
  1352 + { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } },
  1353 + { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR },
  1354 + { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR },
  1355 + { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR },
  1356 + { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR },
  1357 + { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR },
  1358 + { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR },
  1359 + { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
  1360 + { "pal19", PCD(0x19), BASE, ARG_PCD },
  1361 +
  1362 + { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */
  1363 + BASE, { ZA, CPRB } },
  1364 + { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } },
  1365 + { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } },
  1366 + { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */
  1367 + 0xFFFFFFFF, BASE, { 0 } },
  1368 + { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } },
  1369 + { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */
  1370 + { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } },
  1371 +
  1372 + { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
  1373 + { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
  1374 + { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM },
  1375 + { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
  1376 + { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
  1377 + { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM },
  1378 + { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
  1379 + { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
  1380 + { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
  1381 + { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
  1382 + { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
  1383 + { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
  1384 + { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
  1385 + { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
  1386 + { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
  1387 + { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
  1388 + { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
  1389 + { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM },
  1390 + { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
  1391 + { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
  1392 + { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
  1393 + { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
  1394 + { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
  1395 + { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
  1396 + { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
  1397 + { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
  1398 + { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
  1399 + { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
  1400 + { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
  1401 + { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
  1402 + { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
  1403 + { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
  1404 + { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
  1405 + { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
  1406 + { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
  1407 + { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
  1408 + { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
  1409 + { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
  1410 + { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM },
  1411 + { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
  1412 + { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
  1413 + { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM },
  1414 + { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM },
  1415 + { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
  1416 + { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
  1417 + { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
  1418 + { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
  1419 + { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
  1420 + { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
  1421 + { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
  1422 + { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
  1423 + { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
  1424 + { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM },
  1425 + { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
  1426 + { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
  1427 + { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
  1428 + { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
  1429 + { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
  1430 + { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
  1431 + { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
  1432 + { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
  1433 + { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
  1434 + { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
  1435 + { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
  1436 + { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
  1437 + { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM },
  1438 + { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
  1439 + { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
  1440 + { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM },
  1441 + { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
  1442 + { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
  1443 + { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
  1444 + { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
  1445 + { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
  1446 + { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
  1447 + { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
  1448 + { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
  1449 + { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
  1450 + { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
  1451 + { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
  1452 + { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM },
  1453 + { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
  1454 + { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
  1455 + { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
  1456 + { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
  1457 + { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
  1458 + { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
  1459 + { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
  1460 + { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
  1461 + { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
  1462 + { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
  1463 + { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
  1464 + { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
  1465 + { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
  1466 + { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
  1467 + { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
  1468 + { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
  1469 + { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
  1470 + { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
  1471 + { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
  1472 + { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
  1473 + { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM },
  1474 + { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
  1475 + { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
  1476 + { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM },
  1477 + { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM },
  1478 + { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
  1479 + { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
  1480 + { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
  1481 + { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
  1482 + { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
  1483 + { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
  1484 + { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
  1485 + { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
  1486 + { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
  1487 + { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM },
  1488 + { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
  1489 + { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
  1490 + { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
  1491 + { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
  1492 + { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
  1493 + { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
  1494 + { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
  1495 + { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
  1496 + { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
  1497 + { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
  1498 + { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
  1499 + { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
  1500 + { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
  1501 + { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
  1502 + { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
  1503 + { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
  1504 + { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
  1505 + { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
  1506 + { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
  1507 + { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
  1508 + { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
  1509 + { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
  1510 + { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
  1511 + { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
  1512 + { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
  1513 + { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
  1514 + { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
  1515 + { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
  1516 + { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
  1517 + { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
  1518 + { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
  1519 + { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
  1520 + { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
  1521 + { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
  1522 + { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
  1523 + { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
  1524 + { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
  1525 + { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
  1526 + { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
  1527 + { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
  1528 + { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
  1529 + { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
  1530 + { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
  1531 + { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
  1532 + { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
  1533 + { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
  1534 + { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
  1535 + { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
  1536 + { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
  1537 + { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
  1538 + { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
  1539 + { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
  1540 + { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
  1541 + { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
  1542 + { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
  1543 + { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
  1544 + { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
  1545 + { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
  1546 + { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
  1547 + { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
  1548 + { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
  1549 + { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
  1550 + { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
  1551 + { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
  1552 + { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
  1553 + { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
  1554 + { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
  1555 + { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
  1556 + { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
  1557 + { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
  1558 + { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
  1559 + { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
  1560 + { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
  1561 + { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
  1562 + { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
  1563 + { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
  1564 + { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
  1565 + { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
  1566 + { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
  1567 + { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
  1568 + { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
  1569 + { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
  1570 + { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
  1571 + { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
  1572 + { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
  1573 + { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
  1574 + { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
  1575 + { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
  1576 + { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
  1577 + { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
  1578 + { "pal1b", PCD(0x1B), BASE, ARG_PCD },
  1579 +
  1580 + { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 },
  1581 + { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 },
  1582 + { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 },
  1583 + { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR },
  1584 + { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 },
  1585 + { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 },
  1586 + { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 },
  1587 + { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 },
  1588 + { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 },
  1589 + { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 },
  1590 + { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR },
  1591 + { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL },
  1592 + { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR },
  1593 + { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL },
  1594 + { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR },
  1595 + { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL },
  1596 + { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR },
  1597 + { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL },
  1598 + { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR },
  1599 + { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL },
  1600 + { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR },
  1601 + { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL },
  1602 + { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR },
  1603 + { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL },
  1604 + { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR },
  1605 + { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL },
  1606 + { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } },
  1607 + { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } },
  1608 +
  1609 + { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
  1610 + { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
  1611 + { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
  1612 + { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR },
  1613 + { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR },
  1614 + { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR },
  1615 + { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR },
  1616 + { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR },
  1617 + { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR },
  1618 + { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR },
  1619 + { "pal1d", PCD(0x1D), BASE, ARG_PCD },
  1620 +
  1621 + { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE },
  1622 + { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE },
  1623 + { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
  1624 + { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
  1625 + { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
  1626 + { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
  1627 + { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
  1628 + { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
  1629 + { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
  1630 + { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
  1631 + { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
  1632 + { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
  1633 + { "pal1e", PCD(0x1E), BASE, ARG_PCD },
  1634 +
  1635 + { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
  1636 + { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
  1637 + { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */
  1638 + { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
  1639 + { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
  1640 + { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM },
  1641 + { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
  1642 + { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
  1643 + { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
  1644 + { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
  1645 + { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
  1646 + { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
  1647 + { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
  1648 + { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM },
  1649 + { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
  1650 + { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
  1651 + { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
  1652 + { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
  1653 + { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
  1654 + { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
  1655 + { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
  1656 + { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
  1657 + { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
  1658 + { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
  1659 + { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
  1660 + { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
  1661 + { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
  1662 + { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
  1663 + { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
  1664 + { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
  1665 + { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM },
  1666 + { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
  1667 + { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
  1668 + { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
  1669 + { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
  1670 + { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
  1671 + { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
  1672 + { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */
  1673 + { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
  1674 + { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
  1675 + { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM },
  1676 + { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
  1677 + { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
  1678 + { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
  1679 + { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
  1680 + { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
  1681 + { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
  1682 + { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
  1683 + { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM },
  1684 + { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
  1685 + { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
  1686 + { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
  1687 + { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
  1688 + { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
  1689 + { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
  1690 + { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
  1691 + { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
  1692 + { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
  1693 + { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
  1694 + { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
  1695 + { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM },
  1696 + { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
  1697 + { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
  1698 + { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
  1699 + { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
  1700 + { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
  1701 + { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
  1702 + { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM },
  1703 + { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
  1704 + { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
  1705 + { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
  1706 + { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
  1707 + { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
  1708 + { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
  1709 + { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
  1710 + { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
  1711 + { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
  1712 + { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
  1713 + { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
  1714 + { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
  1715 + { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
  1716 + { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
  1717 + { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
  1718 + { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
  1719 + { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
  1720 + { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
  1721 + { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
  1722 + { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
  1723 + { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
  1724 + { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
  1725 + { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
  1726 + { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
  1727 + { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
  1728 + { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
  1729 + { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
  1730 + { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
  1731 + { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
  1732 + { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
  1733 + { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
  1734 + { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
  1735 + { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
  1736 + { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
  1737 + { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
  1738 + { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
  1739 + { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
  1740 + { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
  1741 + { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
  1742 + { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
  1743 + { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
  1744 + { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
  1745 + { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
  1746 + { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
  1747 + { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
  1748 + { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
  1749 + { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
  1750 + { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
  1751 + { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
  1752 + { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
  1753 + { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
  1754 + { "pal1f", PCD(0x1F), BASE, ARG_PCD },
  1755 +
  1756 + { "ldf", MEM(0x20), BASE, ARG_FMEM },
  1757 + { "ldg", MEM(0x21), BASE, ARG_FMEM },
  1758 + { "lds", MEM(0x22), BASE, ARG_FMEM },
  1759 + { "ldt", MEM(0x23), BASE, ARG_FMEM },
  1760 + { "stf", MEM(0x24), BASE, ARG_FMEM },
  1761 + { "stg", MEM(0x25), BASE, ARG_FMEM },
  1762 + { "sts", MEM(0x26), BASE, ARG_FMEM },
  1763 + { "stt", MEM(0x27), BASE, ARG_FMEM },
  1764 +
  1765 + { "ldl", MEM(0x28), BASE, ARG_MEM },
  1766 + { "ldq", MEM(0x29), BASE, ARG_MEM },
  1767 + { "ldl_l", MEM(0x2A), BASE, ARG_MEM },
  1768 + { "ldq_l", MEM(0x2B), BASE, ARG_MEM },
  1769 + { "stl", MEM(0x2C), BASE, ARG_MEM },
  1770 + { "stq", MEM(0x2D), BASE, ARG_MEM },
  1771 + { "stl_c", MEM(0x2E), BASE, ARG_MEM },
  1772 + { "stq_c", MEM(0x2F), BASE, ARG_MEM },
  1773 +
  1774 + { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */
  1775 + { "br", BRA(0x30), BASE, ARG_BRA },
  1776 + { "fbeq", BRA(0x31), BASE, ARG_FBRA },
  1777 + { "fblt", BRA(0x32), BASE, ARG_FBRA },
  1778 + { "fble", BRA(0x33), BASE, ARG_FBRA },
  1779 + { "bsr", BRA(0x34), BASE, ARG_BRA },
  1780 + { "fbne", BRA(0x35), BASE, ARG_FBRA },
  1781 + { "fbge", BRA(0x36), BASE, ARG_FBRA },
  1782 + { "fbgt", BRA(0x37), BASE, ARG_FBRA },
  1783 + { "blbc", BRA(0x38), BASE, ARG_BRA },
  1784 + { "beq", BRA(0x39), BASE, ARG_BRA },
  1785 + { "blt", BRA(0x3A), BASE, ARG_BRA },
  1786 + { "ble", BRA(0x3B), BASE, ARG_BRA },
  1787 + { "blbs", BRA(0x3C), BASE, ARG_BRA },
  1788 + { "bne", BRA(0x3D), BASE, ARG_BRA },
  1789 + { "bge", BRA(0x3E), BASE, ARG_BRA },
  1790 + { "bgt", BRA(0x3F), BASE, ARG_BRA },
  1791 +};
  1792 +
  1793 +const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes);
  1794 +
  1795 +/* OSF register names. */
  1796 +
  1797 +static const char * const osf_regnames[64] = {
  1798 + "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
  1799 + "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
  1800 + "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
  1801 + "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
  1802 + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
  1803 + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
  1804 + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
  1805 + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
  1806 +};
  1807 +
  1808 +/* VMS register names. */
  1809 +
  1810 +static const char * const vms_regnames[64] = {
  1811 + "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
  1812 + "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
  1813 + "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
  1814 + "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ",
  1815 + "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
  1816 + "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
  1817 + "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
  1818 + "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ"
  1819 +};
  1820 +
  1821 +/* Disassemble Alpha instructions. */
  1822 +
  1823 +int
  1824 +print_insn_alpha (memaddr, info)
  1825 + bfd_vma memaddr;
  1826 + struct disassemble_info *info;
  1827 +{
  1828 + static const struct alpha_opcode *opcode_index[AXP_NOPS+1];
  1829 + const char * const * regnames;
  1830 + const struct alpha_opcode *opcode, *opcode_end;
  1831 + const unsigned char *opindex;
  1832 + unsigned insn, op, isa_mask;
  1833 + int need_comma;
  1834 +
  1835 + /* Initialize the majorop table the first time through */
  1836 + if (!opcode_index[0])
  1837 + {
  1838 + opcode = alpha_opcodes;
  1839 + opcode_end = opcode + alpha_num_opcodes;
  1840 +
  1841 + for (op = 0; op < AXP_NOPS; ++op)
  1842 + {
  1843 + opcode_index[op] = opcode;
  1844 + while (opcode < opcode_end && op == AXP_OP (opcode->opcode))
  1845 + ++opcode;
  1846 + }
  1847 + opcode_index[op] = opcode;
  1848 + }
  1849 +
  1850 + if (info->flavour == bfd_target_evax_flavour)
  1851 + regnames = vms_regnames;
  1852 + else
  1853 + regnames = osf_regnames;
  1854 +
  1855 + isa_mask = AXP_OPCODE_NOPAL;
  1856 + switch (info->mach)
  1857 + {
  1858 + case bfd_mach_alpha_ev4:
  1859 + isa_mask |= AXP_OPCODE_EV4;
  1860 + break;
  1861 + case bfd_mach_alpha_ev5:
  1862 + isa_mask |= AXP_OPCODE_EV5;
  1863 + break;
  1864 + case bfd_mach_alpha_ev6:
  1865 + isa_mask |= AXP_OPCODE_EV6;
  1866 + break;
  1867 + }
  1868 +
  1869 + /* Read the insn into a host word */
  1870 + {
  1871 + bfd_byte buffer[4];
  1872 + int status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  1873 + if (status != 0)
  1874 + {
  1875 + (*info->memory_error_func) (status, memaddr, info);
  1876 + return -1;
  1877 + }
  1878 + insn = bfd_getl32 (buffer);
  1879 + }
  1880 +
  1881 + /* Get the major opcode of the instruction. */
  1882 + op = AXP_OP (insn);
  1883 +
  1884 + /* Find the first match in the opcode table. */
  1885 + opcode_end = opcode_index[op + 1];
  1886 + for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode)
  1887 + {
  1888 + if ((insn ^ opcode->opcode) & opcode->mask)
  1889 + continue;
  1890 +
  1891 + if (!(opcode->flags & isa_mask))
  1892 + continue;
  1893 +
  1894 + /* Make two passes over the operands. First see if any of them
  1895 + have extraction functions, and, if they do, make sure the
  1896 + instruction is valid. */
  1897 + {
  1898 + int invalid = 0;
  1899 + for (opindex = opcode->operands; *opindex != 0; opindex++)
  1900 + {
  1901 + const struct alpha_operand *operand = alpha_operands + *opindex;
  1902 + if (operand->extract)
  1903 + (*operand->extract) (insn, &invalid);
  1904 + }
  1905 + if (invalid)
  1906 + continue;
  1907 + }
  1908 +
  1909 + /* The instruction is valid. */
  1910 + goto found;
  1911 + }
  1912 +
  1913 + /* No instruction found */
  1914 + (*info->fprintf_func) (info->stream, ".long %#08x", insn);
  1915 +
  1916 + return 4;
  1917 +
  1918 +found:
  1919 + (*info->fprintf_func) (info->stream, "%s", opcode->name);
  1920 + if (opcode->operands[0] != 0)
  1921 + (*info->fprintf_func) (info->stream, "\t");
  1922 +
  1923 + /* Now extract and print the operands. */
  1924 + need_comma = 0;
  1925 + for (opindex = opcode->operands; *opindex != 0; opindex++)
  1926 + {
  1927 + const struct alpha_operand *operand = alpha_operands + *opindex;
  1928 + int value;
  1929 +
  1930 + /* Operands that are marked FAKE are simply ignored. We
  1931 + already made sure that the extract function considered
  1932 + the instruction to be valid. */
  1933 + if ((operand->flags & AXP_OPERAND_FAKE) != 0)
  1934 + continue;
  1935 +
  1936 + /* Extract the value from the instruction. */
  1937 + if (operand->extract)
  1938 + value = (*operand->extract) (insn, (int *) NULL);
  1939 + else
  1940 + {
  1941 + value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
  1942 + if (operand->flags & AXP_OPERAND_SIGNED)
  1943 + {
  1944 + int signbit = 1 << (operand->bits - 1);
  1945 + value = (value ^ signbit) - signbit;
  1946 + }
  1947 + }
  1948 +
  1949 + if (need_comma &&
  1950 + ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA))
  1951 + != AXP_OPERAND_PARENS))
  1952 + {
  1953 + (*info->fprintf_func) (info->stream, ",");
  1954 + }
  1955 + if (operand->flags & AXP_OPERAND_PARENS)
  1956 + (*info->fprintf_func) (info->stream, "(");
  1957 +
  1958 + /* Print the operand as directed by the flags. */
  1959 + if (operand->flags & AXP_OPERAND_IR)
  1960 + (*info->fprintf_func) (info->stream, "%s", regnames[value]);
  1961 + else if (operand->flags & AXP_OPERAND_FPR)
  1962 + (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]);
  1963 + else if (operand->flags & AXP_OPERAND_RELATIVE)
  1964 + (*info->print_address_func) (memaddr + 4 + value, info);
  1965 + else if (operand->flags & AXP_OPERAND_SIGNED)
  1966 + (*info->fprintf_func) (info->stream, "%d", value);
  1967 + else
  1968 + (*info->fprintf_func) (info->stream, "%#x", value);
  1969 +
  1970 + if (operand->flags & AXP_OPERAND_PARENS)
  1971 + (*info->fprintf_func) (info->stream, ")");
  1972 + need_comma = 1;
  1973 + }
  1974 +
  1975 + return 4;
  1976 +}
@@ -33,6 +33,8 @@ void disas(FILE *out, void *code, unsigned long size, enum disas_type type) @@ -33,6 +33,8 @@ void disas(FILE *out, void *code, unsigned long size, enum disas_type type)
33 print_insn = print_insn_i386; 33 print_insn = print_insn_i386;
34 #elif defined(__powerpc__) 34 #elif defined(__powerpc__)
35 print_insn = print_insn_ppc; 35 print_insn = print_insn_ppc;
  36 +#elif defined(__alpha__)
  37 + print_insn = print_insn_alpha;
36 #else 38 #else
37 fprintf(out, "Asm output not supported on this arch\n"); 39 fprintf(out, "Asm output not supported on this arch\n");
38 return; 40 return;