gwj / at91sam9263 · Commits

Commit a7e6f8ba22f7406aa13048979c6573d80dac5605

Authored by bellard
1 parent 326199c2

synced to Bochs BIOS - use 32 bit pushf/popf in 32 bit PCI bios - moved some use… 

…ful defines in rombios.h


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2188 c046a42c-6fe2-441c-8c8c-71466251a162
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pc-bios/bios.diff
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1   -diff -ruN --exclude Makefile bios.org/acpi-dsdt.dsl bios/acpi-dsdt.dsl
2   ---- bios.org/acpi-dsdt.dsl 1970-01-01 01:00:00.000000000 +0100
3   -+++ bios/acpi-dsdt.dsl 2006-09-24 20:27:54.000000000 +0200
4   -@@ -0,0 +1,559 @@
5   -+/*
6   -+ * QEMU ACPI DSDT ASL definition
7   -+ *
8   -+ * Copyright (c) 2006 Fabrice Bellard
9   -+ *
10   -+ * This library is free software; you can redistribute it and/or
11   -+ * modify it under the terms of the GNU Lesser General Public
12   -+ * License version 2 as published by the Free Software Foundation.
13   -+ *
14   -+ * This library is distributed in the hope that it will be useful,
15   -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
16   -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17   -+ * Lesser General Public License for more details.
18   -+ *
19   -+ * You should have received a copy of the GNU Lesser General Public
20   -+ * License along with this library; if not, write to the Free Software
21   -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22   -+ */
23   -+DefinitionBlock (
24   -+ "acpi-dsdt.aml", // Output Filename
25   -+ "DSDT", // Signature
26   -+ 0x01, // DSDT Compliance Revision
27   -+ "QEMU", // OEMID
28   -+ "QEMUDSDT", // TABLE ID
29   -+ 0x1 // OEM Revision
30   -+ )
31   -+{
32   -+ Scope (\)
33   -+ {
34   -+ /* CMOS memory access */
35   -+ OperationRegion (CMS, SystemIO, 0x70, 0x02)
36   -+ Field (CMS, ByteAcc, NoLock, Preserve)
37   -+ {
38   -+ CMSI, 8,
39   -+ CMSD, 8
40   -+ }
41   -+ Method (CMRD, 1, NotSerialized)
42   -+ {
43   -+ Store (Arg0, CMSI)
44   -+ Store (CMSD, Local0)
45   -+ Return (Local0)
46   -+ }
47   -+
48   -+ /* Debug Output */
49   -+ OperationRegion (DBG, SystemIO, 0xb044, 0x04)
50   -+ Field (DBG, DWordAcc, NoLock, Preserve)
51   -+ {
52   -+ DBGL, 32,
53   -+ }
54   -+ }
55   -+
56   -+
57   -+ /* PCI Bus definition */
58   -+ Scope(\_SB) {
59   -+ Device(PCI0) {
60   -+ Name (_HID, EisaId ("PNP0A03"))
61   -+ Name (_ADR, 0x00)
62   -+ Name (_UID, 1)
63   -+ Name(_PRT, Package() {
64   -+ /* PCI IRQ routing table, example from ACPI 2.0a specification,
65   -+ section 6.2.8.1 */
66   -+ /* Note: we provide the same info as the PCI routing
67   -+ table of the Bochs BIOS */
68   -+
69   -+ // PCI Slot 0
70   -+ Package() {0x0000ffff, 0, LNKD, 0},
71   -+ Package() {0x0000ffff, 1, LNKA, 0},
72   -+ Package() {0x0000ffff, 2, LNKB, 0},
73   -+ Package() {0x0000ffff, 3, LNKC, 0},
74   -+
75   -+ // PCI Slot 1
76   -+ Package() {0x0001ffff, 0, LNKA, 0},
77   -+ Package() {0x0001ffff, 1, LNKB, 0},
78   -+ Package() {0x0001ffff, 2, LNKC, 0},
79   -+ Package() {0x0001ffff, 3, LNKD, 0},
80   -+
81   -+ // PCI Slot 2
82   -+ Package() {0x0002ffff, 0, LNKB, 0},
83   -+ Package() {0x0002ffff, 1, LNKC, 0},
84   -+ Package() {0x0002ffff, 2, LNKD, 0},
85   -+ Package() {0x0002ffff, 3, LNKA, 0},
86   -+
87   -+ // PCI Slot 3
88   -+ Package() {0x0003ffff, 0, LNKC, 0},
89   -+ Package() {0x0003ffff, 1, LNKD, 0},
90   -+ Package() {0x0003ffff, 2, LNKA, 0},
91   -+ Package() {0x0003ffff, 3, LNKB, 0},
92   -+
93   -+ // PCI Slot 4
94   -+ Package() {0x0004ffff, 0, LNKD, 0},
95   -+ Package() {0x0004ffff, 1, LNKA, 0},
96   -+ Package() {0x0004ffff, 2, LNKB, 0},
97   -+ Package() {0x0004ffff, 3, LNKC, 0},
98   -+
99   -+ // PCI Slot 5
100   -+ Package() {0x0005ffff, 0, LNKA, 0},
101   -+ Package() {0x0005ffff, 1, LNKB, 0},
102   -+ Package() {0x0005ffff, 2, LNKC, 0},
103   -+ Package() {0x0005ffff, 3, LNKD, 0},
104   -+ })
105   -+
106   -+ Method (_CRS, 0, NotSerialized)
107   -+ {
108   -+ Name (MEMP, ResourceTemplate ()
109   -+ {
110   -+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
111   -+ 0x0000, // Address Space Granularity
112   -+ 0x0000, // Address Range Minimum
113   -+ 0x00FF, // Address Range Maximum
114   -+ 0x0000, // Address Translation Offset
115   -+ 0x0100, // Address Length
116   -+ ,, )
117   -+ IO (Decode16,
118   -+ 0x0CF8, // Address Range Minimum
119   -+ 0x0CF8, // Address Range Maximum
120   -+ 0x01, // Address Alignment
121   -+ 0x08, // Address Length
122   -+ )
123   -+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
124   -+ 0x0000, // Address Space Granularity
125   -+ 0x0000, // Address Range Minimum
126   -+ 0x0CF7, // Address Range Maximum
127   -+ 0x0000, // Address Translation Offset
128   -+ 0x0CF8, // Address Length
129   -+ ,, , TypeStatic)
130   -+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
131   -+ 0x0000, // Address Space Granularity
132   -+ 0x0D00, // Address Range Minimum
133   -+ 0xFFFF, // Address Range Maximum
134   -+ 0x0000, // Address Translation Offset
135   -+ 0xF300, // Address Length
136   -+ ,, , TypeStatic)
137   -+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
138   -+ 0x00000000, // Address Space Granularity
139   -+ 0x000A0000, // Address Range Minimum
140   -+ 0x000BFFFF, // Address Range Maximum
141   -+ 0x00000000, // Address Translation Offset
142   -+ 0x00020000, // Address Length
143   -+ ,, , AddressRangeMemory, TypeStatic)
144   -+ DWordMemory (ResourceProducer, PosDecode, MinNotFixed, MaxFixed, NonCacheable, ReadWrite,
145   -+ 0x00000000, // Address Space Granularity
146   -+ 0x00000000, // Address Range Minimum
147   -+ 0xFEBFFFFF, // Address Range Maximum
148   -+ 0x00000000, // Address Translation Offset
149   -+ 0x00000000, // Address Length
150   -+ ,, MEMF, AddressRangeMemory, TypeStatic)
151   -+ })
152   -+ CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._MIN, PMIN)
153   -+ CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._MAX, PMAX)
154   -+ CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._LEN, PLEN)
155   -+ /* compute available RAM */
156   -+ Add(CMRD(0x34), ShiftLeft(CMRD(0x35), 8), Local0)
157   -+ ShiftLeft(Local0, 16, Local0)
158   -+ Add(Local0, 0x1000000, Local0)
159   -+ /* update field of last region */
160   -+ Store(Local0, PMIN)
161   -+ Subtract (PMAX, PMIN, PLEN)
162   -+ Increment (PLEN)
163   -+ Return (MEMP)
164   -+ }
165   -+ }
166   -+ }
167   -+
168   -+ Scope(\_SB.PCI0) {
169   -+
170   -+ /* PIIX3 ISA bridge */
171   -+ Device (ISA) {
172   -+ Name (_ADR, 0x00010000)
173   -+
174   -+ /* PIIX PCI to ISA irq remapping */
175   -+ OperationRegion (P40C, PCI_Config, 0x60, 0x04)
176   -+
177   -+
178   -+ /* Keyboard seems to be important for WinXP install */
179   -+ Device (KBD)
180   -+ {
181   -+ Name (_HID, EisaId ("PNP0303"))
182   -+ Method (_STA, 0, NotSerialized)
183   -+ {
184   -+ Return (0x0f)
185   -+ }
186   -+
187   -+ Method (_CRS, 0, NotSerialized)
188   -+ {
189   -+ Name (TMP, ResourceTemplate ()
190   -+ {
191   -+ IO (Decode16,
192   -+ 0x0060, // Address Range Minimum
193   -+ 0x0060, // Address Range Maximum
194   -+ 0x01, // Address Alignment
195   -+ 0x01, // Address Length
196   -+ )
197   -+ IO (Decode16,
198   -+ 0x0064, // Address Range Minimum
199   -+ 0x0064, // Address Range Maximum
200   -+ 0x01, // Address Alignment
201   -+ 0x01, // Address Length
202   -+ )
203   -+ IRQNoFlags ()
204   -+ {1}
205   -+ })
206   -+ Return (TMP)
207   -+ }
208   -+ }
209   -+
210   -+ /* PS/2 mouse */
211   -+ Device (MOU)
212   -+ {
213   -+ Name (_HID, EisaId ("PNP0F13"))
214   -+ Method (_STA, 0, NotSerialized)
215   -+ {
216   -+ Return (0x0f)
217   -+ }
218   -+
219   -+ Method (_CRS, 0, NotSerialized)
220   -+ {
221   -+ Name (TMP, ResourceTemplate ()
222   -+ {
223   -+ IRQNoFlags () {12}
224   -+ })
225   -+ Return (TMP)
226   -+ }
227   -+ }
228   -+
229   -+ /* PS/2 floppy controller */
230   -+ Device (FDC0)
231   -+ {
232   -+ Name (_HID, EisaId ("PNP0700"))
233   -+ Method (_STA, 0, NotSerialized)
234   -+ {
235   -+ Return (0x0F)
236   -+ }
237   -+ Method (_CRS, 0, NotSerialized)
238   -+ {
239   -+ Name (BUF0, ResourceTemplate ()
240   -+ {
241   -+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
242   -+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
243   -+ IRQNoFlags () {6}
244   -+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
245   -+ })
246   -+ Return (BUF0)
247   -+ }
248   -+ }
249   -+
250   -+ /* Parallel port */
251   -+ Device (LPT)
252   -+ {
253   -+ Name (_HID, EisaId ("PNP0400"))
254   -+ Method (_STA, 0, NotSerialized)
255   -+ {
256   -+ Store (\_SB.PCI0.PX13.DRSA, Local0)
257   -+ And (Local0, 0x80000000, Local0)
258   -+ If (LEqual (Local0, 0))
259   -+ {
260   -+ Return (0x00)
261   -+ }
262   -+ Else
263   -+ {
264   -+ Return (0x0F)
265   -+ }
266   -+ }
267   -+ Method (_CRS, 0, NotSerialized)
268   -+ {
269   -+ Name (BUF0, ResourceTemplate ()
270   -+ {
271   -+ IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
272   -+ IRQNoFlags () {7}
273   -+ })
274   -+ Return (BUF0)
275   -+ }
276   -+ }
277   -+
278   -+ /* Serial Ports */
279   -+ Device (COM1)
280   -+ {
281   -+ Name (_HID, EisaId ("PNP0501"))
282   -+ Name (_UID, 0x01)
283   -+ Method (_STA, 0, NotSerialized)
284   -+ {
285   -+ Store (\_SB.PCI0.PX13.DRSC, Local0)
286   -+ And (Local0, 0x08000000, Local0)
287   -+ If (LEqual (Local0, 0))
288   -+ {
289   -+ Return (0x00)
290   -+ }
291   -+ Else
292   -+ {
293   -+ Return (0x0F)
294   -+ }
295   -+ }
296   -+ Method (_CRS, 0, NotSerialized)
297   -+ {
298   -+ Name (BUF0, ResourceTemplate ()
299   -+ {
300   -+ IO (Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
301   -+ IRQNoFlags () {4}
302   -+ })
303   -+ Return (BUF0)
304   -+ }
305   -+ }
306   -+
307   -+ Device (COM2)
308   -+ {
309   -+ Name (_HID, EisaId ("PNP0501"))
310   -+ Name (_UID, 0x02)
311   -+ Method (_STA, 0, NotSerialized)
312   -+ {
313   -+ Store (\_SB.PCI0.PX13.DRSC, Local0)
314   -+ And (Local0, 0x80000000, Local0)
315   -+ If (LEqual (Local0, 0))
316   -+ {
317   -+ Return (0x00)
318   -+ }
319   -+ Else
320   -+ {
321   -+ Return (0x0F)
322   -+ }
323   -+ }
324   -+ Method (_CRS, 0, NotSerialized)
325   -+ {
326   -+ Name (BUF0, ResourceTemplate ()
327   -+ {
328   -+ IO (Decode16, 0x02F8, 0x02F8, 0x00, 0x08)
329   -+ IRQNoFlags () {3}
330   -+ })
331   -+ Return (BUF0)
332   -+ }
333   -+ }
334   -+ }
335   -+
336   -+ /* PIIX4 PM */
337   -+ Device (PX13) {
338   -+ Name (_ADR, 0x00010003)
339   -+
340   -+ OperationRegion (P13C, PCI_Config, 0x5c, 0x24)
341   -+ Field (P13C, DWordAcc, NoLock, Preserve)
342   -+ {
343   -+ DRSA, 32,
344   -+ DRSB, 32,
345   -+ DRSC, 32,
346   -+ DRSE, 32,
347   -+ DRSF, 32,
348   -+ DRSG, 32,
349   -+ DRSH, 32,
350   -+ DRSI, 32,
351   -+ DRSJ, 32
352   -+ }
353   -+ }
354   -+ }
355   -+
356   -+ /* PCI IRQs */
357   -+ Scope(\_SB) {
358   -+ Field (\_SB.PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
359   -+ {
360   -+ PRQ0, 8,
361   -+ PRQ1, 8,
362   -+ PRQ2, 8,
363   -+ PRQ3, 8
364   -+ }
365   -+
366   -+ Device(LNKA){
367   -+ Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
368   -+ Name(_UID, 1)
369   -+ Name(_PRS, ResourceTemplate(){
370   -+ IRQ (Level, ActiveLow, Shared)
371   -+ {3,4,5,6,7,9,10,11,12}
372   -+ })
373   -+ Method (_STA, 0, NotSerialized)
374   -+ {
375   -+ Store (0x0B, Local0)
376   -+ If (And (0x80, PRQ0, Local1))
377   -+ {
378   -+ Store (0x09, Local0)
379   -+ }
380   -+ Return (Local0)
381   -+ }
382   -+ Method (_DIS, 0, NotSerialized)
383   -+ {
384   -+ Or (PRQ0, 0x80, PRQ0)
385   -+ }
386   -+ Method (_CRS, 0, NotSerialized)
387   -+ {
388   -+ Name (PRR0, ResourceTemplate ()
389   -+ {
390   -+ IRQ (Level, ActiveLow, Shared)
391   -+ {1}
392   -+ })
393   -+ CreateWordField (PRR0, 0x01, TMP)
394   -+ Store (PRQ0, Local0)
395   -+ If (LLess (Local0, 0x80))
396   -+ {
397   -+ ShiftLeft (One, Local0, TMP)
398   -+ }
399   -+ Else
400   -+ {
401   -+ Store (Zero, TMP)
402   -+ }
403   -+ Return (PRR0)
404   -+ }
405   -+ Method (_SRS, 1, NotSerialized)
406   -+ {
407   -+ CreateWordField (Arg0, 0x01, TMP)
408   -+ FindSetRightBit (TMP, Local0)
409   -+ Decrement (Local0)
410   -+ Store (Local0, PRQ0)
411   -+ }
412   -+ }
413   -+ Device(LNKB){
414   -+ Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
415   -+ Name(_UID, 2)
416   -+ Name(_PRS, ResourceTemplate(){
417   -+ IRQ (Level, ActiveLow, Shared)
418   -+ {3,4,5,6,7,9,10,11,12}
419   -+ })
420   -+ Method (_STA, 0, NotSerialized)
421   -+ {
422   -+ Store (0x0B, Local0)
423   -+ If (And (0x80, PRQ1, Local1))
424   -+ {
425   -+ Store (0x09, Local0)
426   -+ }
427   -+ Return (Local0)
428   -+ }
429   -+ Method (_DIS, 0, NotSerialized)
430   -+ {
431   -+ Or (PRQ1, 0x80, PRQ1)
432   -+ }
433   -+ Method (_CRS, 0, NotSerialized)
434   -+ {
435   -+ Name (PRR0, ResourceTemplate ()
436   -+ {
437   -+ IRQ (Level, ActiveLow, Shared)
438   -+ {1}
439   -+ })
440   -+ CreateWordField (PRR0, 0x01, TMP)
441   -+ Store (PRQ1, Local0)
442   -+ If (LLess (Local0, 0x80))
443   -+ {
444   -+ ShiftLeft (One, Local0, TMP)
445   -+ }
446   -+ Else
447   -+ {
448   -+ Store (Zero, TMP)
449   -+ }
450   -+ Return (PRR0)
451   -+ }
452   -+ Method (_SRS, 1, NotSerialized)
453   -+ {
454   -+ CreateWordField (Arg0, 0x01, TMP)
455   -+ FindSetRightBit (TMP, Local0)
456   -+ Decrement (Local0)
457   -+ Store (Local0, PRQ1)
458   -+ }
459   -+ }
460   -+ Device(LNKC){
461   -+ Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
462   -+ Name(_UID, 3)
463   -+ Name(_PRS, ResourceTemplate(){
464   -+ IRQ (Level, ActiveLow, Shared)
465   -+ {3,4,5,6,7,9,10,11,12}
466   -+ })
467   -+ Method (_STA, 0, NotSerialized)
468   -+ {
469   -+ Store (0x0B, Local0)
470   -+ If (And (0x80, PRQ2, Local1))
471   -+ {
472   -+ Store (0x09, Local0)
473   -+ }
474   -+ Return (Local0)
475   -+ }
476   -+ Method (_DIS, 0, NotSerialized)
477   -+ {
478   -+ Or (PRQ2, 0x80, PRQ2)
479   -+ }
480   -+ Method (_CRS, 0, NotSerialized)
481   -+ {
482   -+ Name (PRR0, ResourceTemplate ()
483   -+ {
484   -+ IRQ (Level, ActiveLow, Shared)
485   -+ {1}
486   -+ })
487   -+ CreateWordField (PRR0, 0x01, TMP)
488   -+ Store (PRQ2, Local0)
489   -+ If (LLess (Local0, 0x80))
490   -+ {
491   -+ ShiftLeft (One, Local0, TMP)
492   -+ }
493   -+ Else
494   -+ {
495   -+ Store (Zero, TMP)
496   -+ }
497   -+ Return (PRR0)
498   -+ }
499   -+ Method (_SRS, 1, NotSerialized)
500   -+ {
501   -+ CreateWordField (Arg0, 0x01, TMP)
502   -+ FindSetRightBit (TMP, Local0)
503   -+ Decrement (Local0)
504   -+ Store (Local0, PRQ2)
505   -+ }
506   -+ }
507   -+ Device(LNKD){
508   -+ Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
509   -+ Name(_UID, 4)
510   -+ Name(_PRS, ResourceTemplate(){
511   -+ IRQ (Level, ActiveLow, Shared)
512   -+ {3,4,5,6,7,9,10,11,12}
513   -+ })
514   -+ Method (_STA, 0, NotSerialized)
515   -+ {
516   -+ Store (0x0B, Local0)
517   -+ If (And (0x80, PRQ3, Local1))
518   -+ {
519   -+ Store (0x09, Local0)
520   -+ }
521   -+ Return (Local0)
522   -+ }
523   -+ Method (_DIS, 0, NotSerialized)
524   -+ {
525   -+ Or (PRQ3, 0x80, PRQ3)
526   -+ }
527   -+ Method (_CRS, 0, NotSerialized)
528   -+ {
529   -+ Name (PRR0, ResourceTemplate ()
530   -+ {
531   -+ IRQ (Level, ActiveLow, Shared)
532   -+ {1}
533   -+ })
534   -+ CreateWordField (PRR0, 0x01, TMP)
535   -+ Store (PRQ3, Local0)
536   -+ If (LLess (Local0, 0x80))
537   -+ {
538   -+ ShiftLeft (One, Local0, TMP)
539   -+ }
540   -+ Else
541   -+ {
542   -+ Store (Zero, TMP)
543   -+ }
544   -+ Return (PRR0)
545   -+ }
546   -+ Method (_SRS, 1, NotSerialized)
547   -+ {
548   -+ CreateWordField (Arg0, 0x01, TMP)
549   -+ FindSetRightBit (TMP, Local0)
550   -+ Decrement (Local0)
551   -+ Store (Local0, PRQ3)
552   -+ }
553   -+ }
554   -+ }
555   -+
556   -+ /* S5 = power off state */
557   -+ Name (_S5, Package (4) {
558   -+ 0x00, // PM1a_CNT.SLP_TYP
559   -+ 0x00, // PM2a_CNT.SLP_TYP
560   -+ 0x00, // reserved
561   -+ 0x00, // reserved
562   -+ })
563   -+}
564   -diff -ruN --exclude Makefile bios.org/acpi-dsdt.hex bios/acpi-dsdt.hex
565   ---- bios.org/acpi-dsdt.hex 1970-01-01 01:00:00.000000000 +0100
566   -+++ bios/acpi-dsdt.hex 2006-09-24 20:27:54.000000000 +0200
567   -@@ -0,0 +1,278 @@
568   -+/*
569   -+ *
570   -+ * Intel ACPI Component Architecture
571   -+ * ASL Optimizing Compiler version 20060421 [Apr 29 2006]
572   -+ * Copyright (C) 2000 - 2006 Intel Corporation
573   -+ * Supports ACPI Specification Revision 3.0a
574   -+ *
575   -+ * Compilation of "/usr/local/home/bellard/qemu-current/hw/acpi-dsdt.dsl" - Wed Jun 14 20:09:53 2006
576   -+ *
577   -+ * C source code output
578   -+ *
579   -+ */
580   -+unsigned char AmlCode[] =
581   -+{
582   -+ 0x44,0x53,0x44,0x54,0x32,0x08,0x00,0x00, /* 00000000 "DSDT2..." */
583   -+ 0x01,0x5B,0x51,0x45,0x4D,0x55,0x00,0x00, /* 00000008 ".[QEMU.." */
584   -+ 0x51,0x45,0x4D,0x55,0x44,0x53,0x44,0x54, /* 00000010 "QEMUDSDT" */
585   -+ 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
586   -+ 0x21,0x04,0x06,0x20,0x10,0x4F,0x04,0x5C, /* 00000020 "!.. .O.\" */
587   -+ 0x00,0x5B,0x80,0x43,0x4D,0x53,0x5F,0x01, /* 00000028 ".[.CMS_." */
588   -+ 0x0A,0x70,0x0A,0x02,0x5B,0x81,0x10,0x43, /* 00000030 ".p..[..C" */
589   -+ 0x4D,0x53,0x5F,0x01,0x43,0x4D,0x53,0x49, /* 00000038 "MS_.CMSI" */
590   -+ 0x08,0x43,0x4D,0x53,0x44,0x08,0x14,0x14, /* 00000040 ".CMSD..." */
591   -+ 0x43,0x4D,0x52,0x44,0x01,0x70,0x68,0x43, /* 00000048 "CMRD.phC" */
592   -+ 0x4D,0x53,0x49,0x70,0x43,0x4D,0x53,0x44, /* 00000050 "MSIpCMSD" */
593   -+ 0x60,0xA4,0x60,0x5B,0x80,0x44,0x42,0x47, /* 00000058 "`.`[.DBG" */
594   -+ 0x5F,0x01,0x0B,0x44,0xB0,0x0A,0x04,0x5B, /* 00000060 "_..D...[" */
595   -+ 0x81,0x0B,0x44,0x42,0x47,0x5F,0x03,0x44, /* 00000068 "..DBG_.D" */
596   -+ 0x42,0x47,0x4C,0x20,0x10,0x4E,0x25,0x5F, /* 00000070 "BGL .N%_" */
597   -+ 0x53,0x42,0x5F,0x5B,0x82,0x46,0x25,0x50, /* 00000078 "SB_[.F%P" */
598   -+ 0x43,0x49,0x30,0x08,0x5F,0x48,0x49,0x44, /* 00000080 "CI0._HID" */
599   -+ 0x0C,0x41,0xD0,0x0A,0x03,0x08,0x5F,0x41, /* 00000088 ".A...._A" */
600   -+ 0x44,0x52,0x00,0x08,0x5F,0x55,0x49,0x44, /* 00000090 "DR.._UID" */
601   -+ 0x01,0x08,0x5F,0x50,0x52,0x54,0x12,0x47, /* 00000098 ".._PRT.G" */
602   -+ 0x15,0x18,0x12,0x0B,0x04,0x0B,0xFF,0xFF, /* 000000A0 "........" */
603   -+ 0x00,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0B, /* 000000A8 ".LNKD..." */
604   -+ 0x04,0x0B,0xFF,0xFF,0x01,0x4C,0x4E,0x4B, /* 000000B0 ".....LNK" */
605   -+ 0x41,0x00,0x12,0x0C,0x04,0x0B,0xFF,0xFF, /* 000000B8 "A......." */
606   -+ 0x0A,0x02,0x4C,0x4E,0x4B,0x42,0x00,0x12, /* 000000C0 "..LNKB.." */
607   -+ 0x0C,0x04,0x0B,0xFF,0xFF,0x0A,0x03,0x4C, /* 000000C8 ".......L" */
608   -+ 0x4E,0x4B,0x43,0x00,0x12,0x0D,0x04,0x0C, /* 000000D0 "NKC....." */
609   -+ 0xFF,0xFF,0x01,0x00,0x00,0x4C,0x4E,0x4B, /* 000000D8 ".....LNK" */
610   -+ 0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 000000E0 "A......." */
611   -+ 0x01,0x00,0x01,0x4C,0x4E,0x4B,0x42,0x00, /* 000000E8 "...LNKB." */
612   -+ 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01,0x00, /* 000000F0 "........" */
613   -+ 0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00,0x12, /* 000000F8 "..LNKC.." */
614   -+ 0x0E,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A, /* 00000100 "........" */
615   -+ 0x03,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0D, /* 00000108 ".LNKD..." */
616   -+ 0x04,0x0C,0xFF,0xFF,0x02,0x00,0x00,0x4C, /* 00000110 ".......L" */
617   -+ 0x4E,0x4B,0x42,0x00,0x12,0x0D,0x04,0x0C, /* 00000118 "NKB....." */
618   -+ 0xFF,0xFF,0x02,0x00,0x01,0x4C,0x4E,0x4B, /* 00000120 ".....LNK" */
619   -+ 0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF, /* 00000128 "C......." */
620   -+ 0x02,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x44, /* 00000130 "....LNKD" */
621   -+ 0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x02, /* 00000138 "........" */
622   -+ 0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x41,0x00, /* 00000140 "...LNKA." */
623   -+ 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x03,0x00, /* 00000148 "........" */
624   -+ 0x00,0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0D, /* 00000150 ".LNKC..." */
625   -+ 0x04,0x0C,0xFF,0xFF,0x03,0x00,0x01,0x4C, /* 00000158 ".......L" */
626   -+ 0x4E,0x4B,0x44,0x00,0x12,0x0E,0x04,0x0C, /* 00000160 "NKD....." */
627   -+ 0xFF,0xFF,0x03,0x00,0x0A,0x02,0x4C,0x4E, /* 00000168 "......LN" */
628   -+ 0x4B,0x41,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000170 "KA......" */
629   -+ 0xFF,0x03,0x00,0x0A,0x03,0x4C,0x4E,0x4B, /* 00000178 ".....LNK" */
630   -+ 0x42,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000180 "B......." */
631   -+ 0x04,0x00,0x00,0x4C,0x4E,0x4B,0x44,0x00, /* 00000188 "...LNKD." */
632   -+ 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x04,0x00, /* 00000190 "........" */
633   -+ 0x01,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0E, /* 00000198 ".LNKA..." */
634   -+ 0x04,0x0C,0xFF,0xFF,0x04,0x00,0x0A,0x02, /* 000001A0 "........" */
635   -+ 0x4C,0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04, /* 000001A8 "LNKB...." */
636   -+ 0x0C,0xFF,0xFF,0x04,0x00,0x0A,0x03,0x4C, /* 000001B0 ".......L" */
637   -+ 0x4E,0x4B,0x43,0x00,0x12,0x0D,0x04,0x0C, /* 000001B8 "NKC....." */
638   -+ 0xFF,0xFF,0x05,0x00,0x00,0x4C,0x4E,0x4B, /* 000001C0 ".....LNK" */
639   -+ 0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 000001C8 "A......." */
640   -+ 0x05,0x00,0x01,0x4C,0x4E,0x4B,0x42,0x00, /* 000001D0 "...LNKB." */
641   -+ 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x05,0x00, /* 000001D8 "........" */
642   -+ 0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00,0x12, /* 000001E0 "..LNKC.." */
643   -+ 0x0E,0x04,0x0C,0xFF,0xFF,0x05,0x00,0x0A, /* 000001E8 "........" */
644   -+ 0x03,0x4C,0x4E,0x4B,0x44,0x00,0x14,0x4C, /* 000001F0 ".LNKD..L" */
645   -+ 0x0D,0x5F,0x43,0x52,0x53,0x00,0x08,0x4D, /* 000001F8 "._CRS..M" */
646   -+ 0x45,0x4D,0x50,0x11,0x42,0x07,0x0A,0x6E, /* 00000200 "EMP.B..n" */
647   -+ 0x88,0x0D,0x00,0x02,0x0C,0x00,0x00,0x00, /* 00000208 "........" */
648   -+ 0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x01, /* 00000210 "........" */
649   -+ 0x47,0x01,0xF8,0x0C,0xF8,0x0C,0x01,0x08, /* 00000218 "G......." */
650   -+ 0x88,0x0D,0x00,0x01,0x0C,0x03,0x00,0x00, /* 00000220 "........" */
651   -+ 0x00,0x00,0xF7,0x0C,0x00,0x00,0xF8,0x0C, /* 00000228 "........" */
652   -+ 0x88,0x0D,0x00,0x01,0x0C,0x03,0x00,0x00, /* 00000230 "........" */
653   -+ 0x00,0x0D,0xFF,0xFF,0x00,0x00,0x00,0xF3, /* 00000238 "........" */
654   -+ 0x87,0x17,0x00,0x00,0x0C,0x03,0x00,0x00, /* 00000240 "........" */
655   -+ 0x00,0x00,0x00,0x00,0x0A,0x00,0xFF,0xFF, /* 00000248 "........" */
656   -+ 0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000250 "........" */
657   -+ 0x02,0x00,0x87,0x17,0x00,0x00,0x08,0x01, /* 00000258 "........" */
658   -+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000260 "........" */
659   -+ 0xFF,0xFF,0xBF,0xFE,0x00,0x00,0x00,0x00, /* 00000268 "........" */
660   -+ 0x00,0x00,0x00,0x00,0x79,0x00,0x8A,0x4D, /* 00000270 "....y..M" */
661   -+ 0x45,0x4D,0x50,0x0A,0x5C,0x50,0x4D,0x49, /* 00000278 "EMP.\PMI" */
662   -+ 0x4E,0x8A,0x4D,0x45,0x4D,0x50,0x0A,0x60, /* 00000280 "N.MEMP.`" */
663   -+ 0x50,0x4D,0x41,0x58,0x8A,0x4D,0x45,0x4D, /* 00000288 "PMAX.MEM" */
664   -+ 0x50,0x0A,0x68,0x50,0x4C,0x45,0x4E,0x72, /* 00000290 "P.hPLENr" */
665   -+ 0x43,0x4D,0x52,0x44,0x0A,0x34,0x79,0x43, /* 00000298 "CMRD.4yC" */
666   -+ 0x4D,0x52,0x44,0x0A,0x35,0x0A,0x08,0x00, /* 000002A0 "MRD.5..." */
667   -+ 0x60,0x79,0x60,0x0A,0x10,0x60,0x72,0x60, /* 000002A8 "`y`..`r`" */
668   -+ 0x0C,0x00,0x00,0x00,0x01,0x60,0x70,0x60, /* 000002B0 ".....`p`" */
669   -+ 0x50,0x4D,0x49,0x4E,0x74,0x50,0x4D,0x41, /* 000002B8 "PMINtPMA" */
670   -+ 0x58,0x50,0x4D,0x49,0x4E,0x50,0x4C,0x45, /* 000002C0 "XPMINPLE" */
671   -+ 0x4E,0x75,0x50,0x4C,0x45,0x4E,0xA4,0x4D, /* 000002C8 "NuPLEN.M" */
672   -+ 0x45,0x4D,0x50,0x10,0x42,0x26,0x2E,0x5F, /* 000002D0 "EMP.B&._" */
673   -+ 0x53,0x42,0x5F,0x50,0x43,0x49,0x30,0x5B, /* 000002D8 "SB_PCI0[" */
674   -+ 0x82,0x43,0x20,0x49,0x53,0x41,0x5F,0x08, /* 000002E0 ".C ISA_." */
675   -+ 0x5F,0x41,0x44,0x52,0x0C,0x00,0x00,0x01, /* 000002E8 "_ADR...." */
676   -+ 0x00,0x5B,0x80,0x50,0x34,0x30,0x43,0x02, /* 000002F0 ".[.P40C." */
677   -+ 0x0A,0x60,0x0A,0x04,0x5B,0x82,0x44,0x04, /* 000002F8 ".`..[.D." */
678   -+ 0x4B,0x42,0x44,0x5F,0x08,0x5F,0x48,0x49, /* 00000300 "KBD_._HI" */
679   -+ 0x44,0x0C,0x41,0xD0,0x03,0x03,0x14,0x09, /* 00000308 "D.A....." */
680   -+ 0x5F,0x53,0x54,0x41,0x00,0xA4,0x0A,0x0F, /* 00000310 "_STA...." */
681   -+ 0x14,0x29,0x5F,0x43,0x52,0x53,0x00,0x08, /* 00000318 ".)_CRS.." */
682   -+ 0x54,0x4D,0x50,0x5F,0x11,0x18,0x0A,0x15, /* 00000320 "TMP_...." */
683   -+ 0x47,0x01,0x60,0x00,0x60,0x00,0x01,0x01, /* 00000328 "G.`.`..." */
684   -+ 0x47,0x01,0x64,0x00,0x64,0x00,0x01,0x01, /* 00000330 "G.d.d..." */
685   -+ 0x22,0x02,0x00,0x79,0x00,0xA4,0x54,0x4D, /* 00000338 ""..y..TM" */
686   -+ 0x50,0x5F,0x5B,0x82,0x33,0x4D,0x4F,0x55, /* 00000340 "P_[.3MOU" */
687   -+ 0x5F,0x08,0x5F,0x48,0x49,0x44,0x0C,0x41, /* 00000348 "_._HID.A" */
688   -+ 0xD0,0x0F,0x13,0x14,0x09,0x5F,0x53,0x54, /* 00000350 "....._ST" */
689   -+ 0x41,0x00,0xA4,0x0A,0x0F,0x14,0x19,0x5F, /* 00000358 "A......_" */
690   -+ 0x43,0x52,0x53,0x00,0x08,0x54,0x4D,0x50, /* 00000360 "CRS..TMP" */
691   -+ 0x5F,0x11,0x08,0x0A,0x05,0x22,0x00,0x10, /* 00000368 "_....".." */
692   -+ 0x79,0x00,0xA4,0x54,0x4D,0x50,0x5F,0x5B, /* 00000370 "y..TMP_[" */
693   -+ 0x82,0x47,0x04,0x46,0x44,0x43,0x30,0x08, /* 00000378 ".G.FDC0." */
694   -+ 0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,0x07, /* 00000380 "_HID.A.." */
695   -+ 0x00,0x14,0x09,0x5F,0x53,0x54,0x41,0x00, /* 00000388 "..._STA." */
696   -+ 0xA4,0x0A,0x0F,0x14,0x2C,0x5F,0x43,0x52, /* 00000390 "....,_CR" */
697   -+ 0x53,0x00,0x08,0x42,0x55,0x46,0x30,0x11, /* 00000398 "S..BUF0." */
698   -+ 0x1B,0x0A,0x18,0x47,0x01,0xF2,0x03,0xF2, /* 000003A0 "...G...." */
699   -+ 0x03,0x00,0x04,0x47,0x01,0xF7,0x03,0xF7, /* 000003A8 "...G...." */
700   -+ 0x03,0x00,0x01,0x22,0x40,0x00,0x2A,0x04, /* 000003B0 "..."@.*." */
701   -+ 0x00,0x79,0x00,0xA4,0x42,0x55,0x46,0x30, /* 000003B8 ".y..BUF0" */
702   -+ 0x5B,0x82,0x4B,0x05,0x4C,0x50,0x54,0x5F, /* 000003C0 "[.K.LPT_" */
703   -+ 0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0, /* 000003C8 "._HID.A." */
704   -+ 0x04,0x00,0x14,0x28,0x5F,0x53,0x54,0x41, /* 000003D0 "...(_STA" */
705   -+ 0x00,0x70,0x5E,0x5E,0x5E,0x2E,0x50,0x58, /* 000003D8 ".p^^^.PX" */
706   -+ 0x31,0x33,0x44,0x52,0x53,0x41,0x60,0x7B, /* 000003E0 "13DRSA`{" */
707   -+ 0x60,0x0C,0x00,0x00,0x00,0x80,0x60,0xA0, /* 000003E8 "`.....`." */
708   -+ 0x06,0x93,0x60,0x00,0xA4,0x00,0xA1,0x04, /* 000003F0 "..`....." */
709   -+ 0xA4,0x0A,0x0F,0x14,0x21,0x5F,0x43,0x52, /* 000003F8 "....!_CR" */
710   -+ 0x53,0x00,0x08,0x42,0x55,0x46,0x30,0x11, /* 00000400 "S..BUF0." */
711   -+ 0x10,0x0A,0x0D,0x47,0x01,0x78,0x03,0x78, /* 00000408 "...G.x.x" */
712   -+ 0x03,0x08,0x08,0x22,0x80,0x00,0x79,0x00, /* 00000410 "..."..y." */
713   -+ 0xA4,0x42,0x55,0x46,0x30,0x5B,0x82,0x41, /* 00000418 ".BUF0[.A" */
714   -+ 0x06,0x43,0x4F,0x4D,0x31,0x08,0x5F,0x48, /* 00000420 ".COM1._H" */
715   -+ 0x49,0x44,0x0C,0x41,0xD0,0x05,0x01,0x08, /* 00000428 "ID.A...." */
716   -+ 0x5F,0x55,0x49,0x44,0x01,0x14,0x28,0x5F, /* 00000430 "_UID..(_" */
717   -+ 0x53,0x54,0x41,0x00,0x70,0x5E,0x5E,0x5E, /* 00000438 "STA.p^^^" */
718   -+ 0x2E,0x50,0x58,0x31,0x33,0x44,0x52,0x53, /* 00000440 ".PX13DRS" */
719   -+ 0x43,0x60,0x7B,0x60,0x0C,0x00,0x00,0x00, /* 00000448 "C`{`...." */
720   -+ 0x08,0x60,0xA0,0x06,0x93,0x60,0x00,0xA4, /* 00000450 ".`...`.." */
721   -+ 0x00,0xA1,0x04,0xA4,0x0A,0x0F,0x14,0x21, /* 00000458 ".......!" */
722   -+ 0x5F,0x43,0x52,0x53,0x00,0x08,0x42,0x55, /* 00000460 "_CRS..BU" */
723   -+ 0x46,0x30,0x11,0x10,0x0A,0x0D,0x47,0x01, /* 00000468 "F0....G." */
724   -+ 0xF8,0x03,0xF8,0x03,0x00,0x08,0x22,0x10, /* 00000470 "......"." */
725   -+ 0x00,0x79,0x00,0xA4,0x42,0x55,0x46,0x30, /* 00000478 ".y..BUF0" */
726   -+ 0x5B,0x82,0x42,0x06,0x43,0x4F,0x4D,0x32, /* 00000480 "[.B.COM2" */
727   -+ 0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0, /* 00000488 "._HID.A." */
728   -+ 0x05,0x01,0x08,0x5F,0x55,0x49,0x44,0x0A, /* 00000490 "..._UID." */
729   -+ 0x02,0x14,0x28,0x5F,0x53,0x54,0x41,0x00, /* 00000498 "..(_STA." */
730   -+ 0x70,0x5E,0x5E,0x5E,0x2E,0x50,0x58,0x31, /* 000004A0 "p^^^.PX1" */
731   -+ 0x33,0x44,0x52,0x53,0x43,0x60,0x7B,0x60, /* 000004A8 "3DRSC`{`" */
732   -+ 0x0C,0x00,0x00,0x00,0x80,0x60,0xA0,0x06, /* 000004B0 ".....`.." */
733   -+ 0x93,0x60,0x00,0xA4,0x00,0xA1,0x04,0xA4, /* 000004B8 ".`......" */
734   -+ 0x0A,0x0F,0x14,0x21,0x5F,0x43,0x52,0x53, /* 000004C0 "...!_CRS" */
735   -+ 0x00,0x08,0x42,0x55,0x46,0x30,0x11,0x10, /* 000004C8 "..BUF0.." */
736   -+ 0x0A,0x0D,0x47,0x01,0xF8,0x02,0xF8,0x02, /* 000004D0 "..G....." */
737   -+ 0x00,0x08,0x22,0x08,0x00,0x79,0x00,0xA4, /* 000004D8 ".."..y.." */
738   -+ 0x42,0x55,0x46,0x30,0x5B,0x82,0x40,0x05, /* 000004E0 "BUF0[.@." */
739   -+ 0x50,0x58,0x31,0x33,0x08,0x5F,0x41,0x44, /* 000004E8 "PX13._AD" */
740   -+ 0x52,0x0C,0x03,0x00,0x01,0x00,0x5B,0x80, /* 000004F0 "R.....[." */
741   -+ 0x50,0x31,0x33,0x43,0x02,0x0A,0x5C,0x0A, /* 000004F8 "P13C..\." */
742   -+ 0x24,0x5B,0x81,0x33,0x50,0x31,0x33,0x43, /* 00000500 "$[.3P13C" */
743   -+ 0x03,0x44,0x52,0x53,0x41,0x20,0x44,0x52, /* 00000508 ".DRSA DR" */
744   -+ 0x53,0x42,0x20,0x44,0x52,0x53,0x43,0x20, /* 00000510 "SB DRSC " */
745   -+ 0x44,0x52,0x53,0x45,0x20,0x44,0x52,0x53, /* 00000518 "DRSE DRS" */
746   -+ 0x46,0x20,0x44,0x52,0x53,0x47,0x20,0x44, /* 00000520 "F DRSG D" */
747   -+ 0x52,0x53,0x48,0x20,0x44,0x52,0x53,0x49, /* 00000528 "RSH DRSI" */
748   -+ 0x20,0x44,0x52,0x53,0x4A,0x20,0x10,0x4F, /* 00000530 " DRSJ .O" */
749   -+ 0x2E,0x5F,0x53,0x42,0x5F,0x5B,0x81,0x24, /* 00000538 "._SB_[.$" */
750   -+ 0x2F,0x03,0x50,0x43,0x49,0x30,0x49,0x53, /* 00000540 "/.PCI0IS" */
751   -+ 0x41,0x5F,0x50,0x34,0x30,0x43,0x01,0x50, /* 00000548 "A_P40C.P" */
752   -+ 0x52,0x51,0x30,0x08,0x50,0x52,0x51,0x31, /* 00000550 "RQ0.PRQ1" */
753   -+ 0x08,0x50,0x52,0x51,0x32,0x08,0x50,0x52, /* 00000558 ".PRQ2.PR" */
754   -+ 0x51,0x33,0x08,0x5B,0x82,0x4E,0x0A,0x4C, /* 00000560 "Q3.[.N.L" */
755   -+ 0x4E,0x4B,0x41,0x08,0x5F,0x48,0x49,0x44, /* 00000568 "NKA._HID" */
756   -+ 0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F,0x55, /* 00000570 ".A...._U" */
757   -+ 0x49,0x44,0x01,0x08,0x5F,0x50,0x52,0x53, /* 00000578 "ID.._PRS" */
758   -+ 0x11,0x09,0x0A,0x06,0x23,0xF8,0x1E,0x18, /* 00000580 "....#..." */
759   -+ 0x79,0x00,0x14,0x1A,0x5F,0x53,0x54,0x41, /* 00000588 "y..._STA" */
760   -+ 0x00,0x70,0x0A,0x0B,0x60,0xA0,0x0D,0x7B, /* 00000590 ".p..`..{" */
761   -+ 0x0A,0x80,0x50,0x52,0x51,0x30,0x61,0x70, /* 00000598 "..PRQ0ap" */
762   -+ 0x0A,0x09,0x60,0xA4,0x60,0x14,0x11,0x5F, /* 000005A0 "..`.`.._" */
763   -+ 0x44,0x49,0x53,0x00,0x7D,0x50,0x52,0x51, /* 000005A8 "DIS.}PRQ" */
764   -+ 0x30,0x0A,0x80,0x50,0x52,0x51,0x30,0x14, /* 000005B0 "0..PRQ0." */
765   -+ 0x3F,0x5F,0x43,0x52,0x53,0x00,0x08,0x50, /* 000005B8 "?_CRS..P" */
766   -+ 0x52,0x52,0x30,0x11,0x09,0x0A,0x06,0x23, /* 000005C0 "RR0....#" */
767   -+ 0x02,0x00,0x18,0x79,0x00,0x8B,0x50,0x52, /* 000005C8 "...y..PR" */
768   -+ 0x52,0x30,0x01,0x54,0x4D,0x50,0x5F,0x70, /* 000005D0 "R0.TMP_p" */
769   -+ 0x50,0x52,0x51,0x30,0x60,0xA0,0x0C,0x95, /* 000005D8 "PRQ0`..." */
770   -+ 0x60,0x0A,0x80,0x79,0x01,0x60,0x54,0x4D, /* 000005E0 "`..y.`TM" */
771   -+ 0x50,0x5F,0xA1,0x07,0x70,0x00,0x54,0x4D, /* 000005E8 "P_..p.TM" */
772   -+ 0x50,0x5F,0xA4,0x50,0x52,0x52,0x30,0x14, /* 000005F0 "P_.PRR0." */
773   -+ 0x1B,0x5F,0x53,0x52,0x53,0x01,0x8B,0x68, /* 000005F8 "._SRS..h" */
774   -+ 0x01,0x54,0x4D,0x50,0x5F,0x82,0x54,0x4D, /* 00000600 ".TMP_.TM" */
775   -+ 0x50,0x5F,0x60,0x76,0x60,0x70,0x60,0x50, /* 00000608 "P_`v`p`P" */
776   -+ 0x52,0x51,0x30,0x5B,0x82,0x4F,0x0A,0x4C, /* 00000610 "RQ0[.O.L" */
777   -+ 0x4E,0x4B,0x42,0x08,0x5F,0x48,0x49,0x44, /* 00000618 "NKB._HID" */
778   -+ 0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F,0x55, /* 00000620 ".A...._U" */
779   -+ 0x49,0x44,0x0A,0x02,0x08,0x5F,0x50,0x52, /* 00000628 "ID..._PR" */
780   -+ 0x53,0x11,0x09,0x0A,0x06,0x23,0xF8,0x1E, /* 00000630 "S....#.." */
781   -+ 0x18,0x79,0x00,0x14,0x1A,0x5F,0x53,0x54, /* 00000638 ".y..._ST" */
782   -+ 0x41,0x00,0x70,0x0A,0x0B,0x60,0xA0,0x0D, /* 00000640 "A.p..`.." */
783   -+ 0x7B,0x0A,0x80,0x50,0x52,0x51,0x31,0x61, /* 00000648 "{..PRQ1a" */
784   -+ 0x70,0x0A,0x09,0x60,0xA4,0x60,0x14,0x11, /* 00000650 "p..`.`.." */
785   -+ 0x5F,0x44,0x49,0x53,0x00,0x7D,0x50,0x52, /* 00000658 "_DIS.}PR" */
786   -+ 0x51,0x31,0x0A,0x80,0x50,0x52,0x51,0x31, /* 00000660 "Q1..PRQ1" */
787   -+ 0x14,0x3F,0x5F,0x43,0x52,0x53,0x00,0x08, /* 00000668 ".?_CRS.." */
788   -+ 0x50,0x52,0x52,0x30,0x11,0x09,0x0A,0x06, /* 00000670 "PRR0...." */
789   -+ 0x23,0x02,0x00,0x18,0x79,0x00,0x8B,0x50, /* 00000678 "#...y..P" */
790   -+ 0x52,0x52,0x30,0x01,0x54,0x4D,0x50,0x5F, /* 00000680 "RR0.TMP_" */
791   -+ 0x70,0x50,0x52,0x51,0x31,0x60,0xA0,0x0C, /* 00000688 "pPRQ1`.." */
792   -+ 0x95,0x60,0x0A,0x80,0x79,0x01,0x60,0x54, /* 00000690 ".`..y.`T" */
793   -+ 0x4D,0x50,0x5F,0xA1,0x07,0x70,0x00,0x54, /* 00000698 "MP_..p.T" */
794   -+ 0x4D,0x50,0x5F,0xA4,0x50,0x52,0x52,0x30, /* 000006A0 "MP_.PRR0" */
795   -+ 0x14,0x1B,0x5F,0x53,0x52,0x53,0x01,0x8B, /* 000006A8 ".._SRS.." */
796   -+ 0x68,0x01,0x54,0x4D,0x50,0x5F,0x82,0x54, /* 000006B0 "h.TMP_.T" */
797   -+ 0x4D,0x50,0x5F,0x60,0x76,0x60,0x70,0x60, /* 000006B8 "MP_`v`p`" */
798   -+ 0x50,0x52,0x51,0x31,0x5B,0x82,0x4F,0x0A, /* 000006C0 "PRQ1[.O." */
799   -+ 0x4C,0x4E,0x4B,0x43,0x08,0x5F,0x48,0x49, /* 000006C8 "LNKC._HI" */
800   -+ 0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F, /* 000006D0 "D.A...._" */
801   -+ 0x55,0x49,0x44,0x0A,0x03,0x08,0x5F,0x50, /* 000006D8 "UID..._P" */
802   -+ 0x52,0x53,0x11,0x09,0x0A,0x06,0x23,0xF8, /* 000006E0 "RS....#." */
803   -+ 0x1E,0x18,0x79,0x00,0x14,0x1A,0x5F,0x53, /* 000006E8 "..y..._S" */
804   -+ 0x54,0x41,0x00,0x70,0x0A,0x0B,0x60,0xA0, /* 000006F0 "TA.p..`." */
805   -+ 0x0D,0x7B,0x0A,0x80,0x50,0x52,0x51,0x32, /* 000006F8 ".{..PRQ2" */
806   -+ 0x61,0x70,0x0A,0x09,0x60,0xA4,0x60,0x14, /* 00000700 "ap..`.`." */
807   -+ 0x11,0x5F,0x44,0x49,0x53,0x00,0x7D,0x50, /* 00000708 "._DIS.}P" */
808   -+ 0x52,0x51,0x32,0x0A,0x80,0x50,0x52,0x51, /* 00000710 "RQ2..PRQ" */
809   -+ 0x32,0x14,0x3F,0x5F,0x43,0x52,0x53,0x00, /* 00000718 "2.?_CRS." */
810   -+ 0x08,0x50,0x52,0x52,0x30,0x11,0x09,0x0A, /* 00000720 ".PRR0..." */
811   -+ 0x06,0x23,0x02,0x00,0x18,0x79,0x00,0x8B, /* 00000728 ".#...y.." */
812   -+ 0x50,0x52,0x52,0x30,0x01,0x54,0x4D,0x50, /* 00000730 "PRR0.TMP" */
813   -+ 0x5F,0x70,0x50,0x52,0x51,0x32,0x60,0xA0, /* 00000738 "_pPRQ2`." */
814   -+ 0x0C,0x95,0x60,0x0A,0x80,0x79,0x01,0x60, /* 00000740 "..`..y.`" */
815   -+ 0x54,0x4D,0x50,0x5F,0xA1,0x07,0x70,0x00, /* 00000748 "TMP_..p." */
816   -+ 0x54,0x4D,0x50,0x5F,0xA4,0x50,0x52,0x52, /* 00000750 "TMP_.PRR" */
817   -+ 0x30,0x14,0x1B,0x5F,0x53,0x52,0x53,0x01, /* 00000758 "0.._SRS." */
818   -+ 0x8B,0x68,0x01,0x54,0x4D,0x50,0x5F,0x82, /* 00000760 ".h.TMP_." */
819   -+ 0x54,0x4D,0x50,0x5F,0x60,0x76,0x60,0x70, /* 00000768 "TMP_`v`p" */
820   -+ 0x60,0x50,0x52,0x51,0x32,0x5B,0x82,0x4F, /* 00000770 "`PRQ2[.O" */
821   -+ 0x0A,0x4C,0x4E,0x4B,0x44,0x08,0x5F,0x48, /* 00000778 ".LNKD._H" */
822   -+ 0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08, /* 00000780 "ID.A...." */
823   -+ 0x5F,0x55,0x49,0x44,0x0A,0x04,0x08,0x5F, /* 00000788 "_UID..._" */
824   -+ 0x50,0x52,0x53,0x11,0x09,0x0A,0x06,0x23, /* 00000790 "PRS....#" */
825   -+ 0xF8,0x1E,0x18,0x79,0x00,0x14,0x1A,0x5F, /* 00000798 "...y..._" */
826   -+ 0x53,0x54,0x41,0x00,0x70,0x0A,0x0B,0x60, /* 000007A0 "STA.p..`" */
827   -+ 0xA0,0x0D,0x7B,0x0A,0x80,0x50,0x52,0x51, /* 000007A8 "..{..PRQ" */
828   -+ 0x33,0x61,0x70,0x0A,0x09,0x60,0xA4,0x60, /* 000007B0 "3ap..`.`" */
829   -+ 0x14,0x11,0x5F,0x44,0x49,0x53,0x00,0x7D, /* 000007B8 ".._DIS.}" */
830   -+ 0x50,0x52,0x51,0x33,0x0A,0x80,0x50,0x52, /* 000007C0 "PRQ3..PR" */
831   -+ 0x51,0x33,0x14,0x3F,0x5F,0x43,0x52,0x53, /* 000007C8 "Q3.?_CRS" */
832   -+ 0x00,0x08,0x50,0x52,0x52,0x30,0x11,0x09, /* 000007D0 "..PRR0.." */
833   -+ 0x0A,0x06,0x23,0x02,0x00,0x18,0x79,0x00, /* 000007D8 "..#...y." */
834   -+ 0x8B,0x50,0x52,0x52,0x30,0x01,0x54,0x4D, /* 000007E0 ".PRR0.TM" */
835   -+ 0x50,0x5F,0x70,0x50,0x52,0x51,0x33,0x60, /* 000007E8 "P_pPRQ3`" */
836   -+ 0xA0,0x0C,0x95,0x60,0x0A,0x80,0x79,0x01, /* 000007F0 "...`..y." */
837   -+ 0x60,0x54,0x4D,0x50,0x5F,0xA1,0x07,0x70, /* 000007F8 "`TMP_..p" */
838   -+ 0x00,0x54,0x4D,0x50,0x5F,0xA4,0x50,0x52, /* 00000800 ".TMP_.PR" */
839   -+ 0x52,0x30,0x14,0x1B,0x5F,0x53,0x52,0x53, /* 00000808 "R0.._SRS" */
840   -+ 0x01,0x8B,0x68,0x01,0x54,0x4D,0x50,0x5F, /* 00000810 "..h.TMP_" */
841   -+ 0x82,0x54,0x4D,0x50,0x5F,0x60,0x76,0x60, /* 00000818 ".TMP_`v`" */
842   -+ 0x70,0x60,0x50,0x52,0x51,0x33,0x08,0x5F, /* 00000820 "p`PRQ3._" */
843   -+ 0x53,0x35,0x5F,0x12,0x06,0x04,0x00,0x00, /* 00000828 "S5_....." */
844   -+ 0x00,0x00,
845   -+};
846   -Binary files bios.org/BIOS-bochs-latest and bios/BIOS-bochs-latest differ
847   -diff -ruN --exclude Makefile bios.org/Makefile.in bios/Makefile.in
848   ---- bios.org/Makefile.in 2006-01-13 18:36:27.000000000 +0100
849   -+++ bios/Makefile.in 2006-09-24 21:37:05.000000000 +0200
850   -@@ -61,7 +61,8 @@
  1 +Index: BIOS-bochs-latest
  2 +===================================================================
  3 +RCS file: /cvsroot/bochs/bochs/bios/BIOS-bochs-latest,v
  4 +retrieving revision 1.133
  5 +diff -u -w -r1.133 BIOS-bochs-latest
  6 +Binary files /tmp/cvsrjjP5I and BIOS-bochs-latest differ
  7 +Index: rombios.c
  8 +===================================================================
  9 +RCS file: /cvsroot/bochs/bochs/bios/rombios.c,v
  10 +retrieving revision 1.170
  11 +diff -u -w -r1.170 rombios.c
  12 +--- rombios.c 30 Sep 2006 11:22:53 -0000 1.170
  13 ++++ rombios.c 1 Oct 2006 16:03:53 -0000
  14 +@@ -4115,7 +4115,7 @@
  15 + case 3:
  16 + set_e820_range(ES, regs.u.r16.di,
  17 + 0x00100000L,
  18 +- extended_memory_size - 0x10000L, 1);
  19 ++ extended_memory_size - ACPI_DATA_SIZE, 1);
  20 + regs.u.r32.ebx = 4;
  21 + regs.u.r32.eax = 0x534D4150;
  22 + regs.u.r32.ecx = 0x14;
  23 +@@ -4124,7 +4124,7 @@
  24 + break;
  25 + case 4:
  26 + set_e820_range(ES, regs.u.r16.di,
  27 +- extended_memory_size - 0x10000L,
  28 ++ extended_memory_size - ACPI_DATA_SIZE,
  29 + extended_memory_size, 3); // ACPI RAM
  30 + regs.u.r32.ebx = 5;
  31 + regs.u.r32.eax = 0x534D4150;
  32 +@@ -8723,7 +8723,7 @@
  33 +
  34 + .align 16
  35 + bios32_entry_point:
  36 +- pushf
  37 ++ pushfd
  38 + cmp eax, #0x49435024 ;; "$PCI"
  39 + jne unknown_service
  40 + mov eax, #0x80000000
  41 +@@ -8750,12 +8750,12 @@
  42 + #ifdef BX_QEMU
  43 + and dword ptr[esp+8],0xfffffffc ;; reset CS.RPL for kqemu
  44 + #endif
  45 +- popf
  46 ++ popfd
  47 + retf
851 48  
852   - clean:
853   - @RMCOMMAND@ *.o *.a *.s _rombios*_.c rombios*.txt rombios*.sym
854   -- @RMCOMMAND@ usage biossums
855   -+ @RMCOMMAND@ usage biossums rombios16.bin
856   -+ @RMCOMMAND@ rombios32.bin rombios32.out pad tmp32.bin
  49 + .align 16
  50 + pcibios_protected:
  51 +- pushf
  52 ++ pushfd
  53 + cli
  54 + push esi
  55 + push edi
  56 +@@ -8864,7 +8864,7 @@
  57 + #ifdef BX_QEMU
  58 + and dword ptr[esp+8],0xfffffffc ;; reset CS.RPL for kqemu
  59 + #endif
  60 +- popf
  61 ++ popfd
  62 + stc
  63 + retf
  64 + pci_pro_ok:
  65 +@@ -8874,7 +8874,7 @@
  66 + #ifdef BX_QEMU
  67 + and dword ptr[esp+8],0xfffffffc ;; reset CS.RPL for kqemu
  68 + #endif
  69 +- popf
  70 ++ popfd
  71 + clc
  72 + retf
857 73  
858   - dist-clean: clean
859   - @RMCOMMAND@ Makefile
860   -@@ -69,15 +70,40 @@
861   - bios-clean:
862   - @RMCOMMAND@ BIOS-bochs-*
  74 +Index: rombios.h
  75 +===================================================================
  76 +RCS file: /cvsroot/bochs/bochs/bios/rombios.h,v
  77 +retrieving revision 1.1
  78 +diff -u -w -r1.1 rombios.h
  79 +--- rombios.h 30 Sep 2006 11:22:53 -0000 1.1
  80 ++++ rombios.h 1 Oct 2006 16:03:54 -0000
  81 +@@ -19,7 +19,7 @@
  82 + // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
863 83  
864   --BIOS-bochs-latest: rombios.c apmbios.S biossums
865   -+rombios16.bin: rombios.c apmbios.S biossums
866   - $(GCC) $(BIOS_BUILD_DATE) -E -P $< > _rombios_.c
867   - $(BCC) -o rombios.s -C-c -D__i86__ -0 -S _rombios_.c
868   - sed -e 's/^\.text//' -e 's/^\.data//' rombios.s > _rombios_.s
869   - $(AS86) _rombios_.s -b tmp.bin -u- -w- -g -0 -j -O -l rombios.txt
870   - -perl ${srcdir}/makesym.perl < rombios.txt > rombios.sym
871   -- mv tmp.bin BIOS-bochs-latest
872   -- ./biossums BIOS-bochs-latest
873   -+ mv tmp.bin rombios16.bin
874   -+ ./biossums rombios16.bin
875   - rm -f _rombios_.s
  84 + /* define it to include QEMU specific code */
  85 +-//#define BX_QEMU
  86 ++#define BX_QEMU
876 87  
  88 + #define BX_ROMBIOS32 1
  89 + #define DEBUG_ROMBIOS 0
  90 +@@ -48,3 +48,7 @@
  91 + #endif
  92 + #define BX_INFO(format, p...) bios_printf(BIOS_PRINTF_INFO, format, ##p)
  93 + #define BX_PANIC(format, p...) bios_printf(BIOS_PRINTF_DEBHALT, format, ##p)
877 94 +
878   -+rombios32.bin: rombios32.out pad
879   -+ objcopy -O binary $< tmp32.bin
880   -+ ./pad < tmp32.bin > $@ 65536 0xff
881   -+
882   -+rombios32.out: rombios32start.o rombios32.o rombios32.ld
883   -+ ld -o $@ -T rombios32.ld rombios32start.o rombios32.o
884   -+
885   -+rombios32.o: rombios32.c acpi-dsdt.hex
886   -+ $(GCC) -O2 -Wall -c -o $@ $<
887   -+
888   -+ifeq ("1", "0")
889   -+acpi-dsdt.hex: acpi-dsdt.dsl
890   -+ iasl -tc -p $@ $<
891   -+endif
892   -+
893   -+rombios32start.o: rombios32start.S
894   -+ $(GCC) -c -o $@ $<
895   -+
896   -+BIOS-bochs-latest: rombios16.bin rombios32.bin
897   -+ cat rombios32.bin rombios16.bin > $@
898   -+
899   -+pad: pad.c
900   -+ $(GCC) -o $@ $<
901   -+
902   - biossums: biossums.c
903   - $(GCC) -o biossums biossums.c
904   -diff -ruN --exclude Makefile bios.org/pad.c bios/pad.c
905   ---- bios.org/pad.c 1970-01-01 01:00:00.000000000 +0100
906   -+++ bios/pad.c 2006-09-24 20:22:58.000000000 +0200
907   -@@ -0,0 +1,20 @@
908   -+#include <stdlib.h>
909   -+#include <stdio.h>
910   -+
911   -+int main(int argc, char **argv)
912   -+{
913   -+ int len, val, i, c;
914   -+
915   -+ len = strtol(argv[1], NULL, 0);
916   -+ val = strtol(argv[2], NULL, 0);
917   -+ for(i = 0 ; i < len; i++) {
918   -+ c = getchar();
919   -+ if (c == EOF)
920   -+ break;
921   -+ putchar(c);
922   -+ }
923   -+ for( ; i < len; i++) {
924   -+ putchar(val);
925   -+ }
926   -+ return 0;
927   -+}
928   -diff -ruN --exclude Makefile bios.org/rombios32.c bios/rombios32.c
929   ---- bios.org/rombios32.c 1970-01-01 01:00:00.000000000 +0100
930   -+++ bios/rombios32.c 2006-09-24 21:29:27.000000000 +0200
931   -@@ -0,0 +1,1324 @@
  95 ++#define ACPI_DATA_SIZE 0x00010000L
  96 ++#define PM_IO_BASE 0xb000
  97 ++#define CPU_COUNT_ADDR 0xf000
  98 +Index: rombios32.c
  99 +===================================================================
  100 +RCS file: /cvsroot/bochs/bochs/bios/rombios32.c,v
  101 +retrieving revision 1.4
  102 +diff -u -w -r1.4 rombios32.c
  103 +--- rombios32.c 30 Sep 2006 11:22:53 -0000 1.4
  104 ++++ rombios32.c 1 Oct 2006 16:03:54 -0000
  105 +@@ -55,13 +55,10 @@
  106 +
  107 + #define APIC_ENABLED 0x0100
  108 +
  109 +-#define CPU_COUNT_ADDR 0xf000
  110 + #define AP_BOOT_ADDR 0x10000
  111 +
  112 + #define MPTABLE_MAX_SIZE 0x00002000
  113 +-#define ACPI_DATA_SIZE 0x00010000
  114 + #define SMI_CMD_IO_ADDR 0xb2
  115 +-#define PM_IO_BASE 0xb000
  116 +
  117 + #define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
  118 +
  119 +@@ -354,12 +351,14 @@
  120 +
  121 + void delay_ms(int n)
  122 + {
  123 +- int i, j, r1, r2;
  124 ++ int i, j;
  125 + for(i = 0; i < n; i++) {
  126 +-#if BX_QEMU
  127 ++#ifdef BX_QEMU
  128 + /* approximative ! */
  129 + for(j = 0; j < 1000000; j++);
  130 + #else
  131 ++ {
  132 ++ int r1, r2;
  133 + j = 66;
  134 + r1 = inb(0x61) & 0x10;
  135 + do {
  136 +@@ -369,6 +368,7 @@
  137 + r1 = r2;
  138 + }
  139 + } while (j > 0);
  140 ++ }
  141 + #endif
  142 + }
  143 + }
  144 +Index: rombios32start.S
  145 +===================================================================
  146 +RCS file: /cvsroot/bochs/bochs/bios/rombios32start.S,v
  147 +retrieving revision 1.1
  148 +diff -u -w -r1.1 rombios32start.S
  149 +--- rombios32start.S 28 Sep 2006 18:56:20 -0000 1.1
  150 ++++ rombios32start.S 1 Oct 2006 16:03:54 -0000
  151 +@@ -1,3 +1,25 @@
  152 ++/////////////////////////////////////////////////////////////////////////
  153 ++// $Id: bios.diff,v 1.15 2006-10-01 16:08:15 bellard Exp $
  154 ++/////////////////////////////////////////////////////////////////////////
  155 ++//
932 156 +// 32 bit Bochs BIOS init code
933 157 +// Copyright (C) 2006 Fabrice Bellard
934 158 +//
... ... @@ -945,1933 +169,50 @@ diff -ruN --exclude Makefile bios.org/rombios32.c bios/rombios32.c
945 169 +// You should have received a copy of the GNU Lesser General Public
946 170 +// License along with this library; if not, write to the Free Software
947 171 +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
948   -+#include <stdarg.h>
949   -+#include <stddef.h>
950   -+
951   -+typedef signed char int8_t;
952   -+typedef short int16_t;
953   -+typedef int int32_t;
954   -+typedef long long int64_t;
955   -+typedef unsigned char uint8_t;
956   -+typedef unsigned short uint16_t;
957   -+typedef unsigned int uint32_t;
958   -+typedef unsigned long long uint64_t;
959   -+
960   -+/* if true, put the MP float table and ACPI RSDT in EBDA and the MP
961   -+ table in RAM. Unfortunately, Linux has bugs with that, so we prefer
962   -+ to modify the BIOS in shadow RAM */
963   -+//#define BX_USE_EBDA_TABLES
964   -+
965   -+/* define it if the (emulated) hardware supports SMM mode */
966   -+#define BX_USE_SMM
967   -+
968   -+#define BX_INFO(fmt, args...) bios_printf(0, fmt, ## args);
969   -+
970   -+#define INFO_PORT 0x402
971   -+
972   -+#define cpuid(index, eax, ebx, ecx, edx) \
973   -+ asm volatile ("cpuid" \
974   -+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
975   -+ : "0" (index))
976   -+
977   -+#define CPUID_APIC (1 << 9)
978   -+
979   -+#define APIC_BASE ((uint8_t *)0xfee00000)
980   -+#define APIC_ICR_LOW 0x300
981   -+#define APIC_SVR 0x0F0
982   -+#define APIC_ID 0x020
983   -+#define APIC_LVT3 0x370
984   -+
985   -+#define APIC_ENABLED 0x0100
986   -+
987   -+#define CPU_COUNT_ADDR 0xf000
988   -+#define AP_BOOT_ADDR 0x10000
989   -+
990   -+#define MPTABLE_MAX_SIZE 0x00002000
991   -+#define ACPI_DATA_SIZE 0x00010000
992   -+#define SMI_CMD_IO_ADDR 0xb2
993   -+#define PM_IO_BASE 0xb000
994   -+
995   -+#define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
996   -+
997   -+static inline void outl(int addr, int val)
998   -+{
999   -+ asm volatile ("outl %1, %w0" : : "d" (addr), "a" (val));
1000   -+}
1001   -+
1002   -+static inline void outw(int addr, int val)
1003   -+{
1004   -+ asm volatile ("outw %w1, %w0" : : "d" (addr), "a" (val));
1005   -+}
1006   -+
1007   -+static inline void outb(int addr, int val)
1008   -+{
1009   -+ asm volatile ("outb %b1, %w0" : : "d" (addr), "a" (val));
1010   -+}
1011   -+
1012   -+static inline uint32_t inl(int addr)
1013   -+{
1014   -+ uint32_t val;
1015   -+ asm volatile ("inl %w1, %0" : "=a" (val) : "d" (addr));
1016   -+ return val;
1017   -+}
1018   -+
1019   -+static inline uint16_t inw(int addr)
1020   -+{
1021   -+ uint16_t val;
1022   -+ asm volatile ("inw %w1, %w0" : "=a" (val) : "d" (addr));
1023   -+ return val;
1024   -+}
1025   -+
1026   -+static inline uint8_t inb(int addr)
1027   -+{
1028   -+ uint8_t val;
1029   -+ asm volatile ("inb %w1, %b0" : "=a" (val) : "d" (addr));
1030   -+ return val;
1031   -+}
1032   -+
1033   -+static inline void writel(void *addr, uint32_t val)
1034   -+{
1035   -+ *(volatile uint32_t *)addr = val;
1036   -+}
1037   -+
1038   -+static inline void writew(void *addr, uint16_t val)
1039   -+{
1040   -+ *(volatile uint16_t *)addr = val;
1041   -+}
1042   -+
1043   -+static inline void writeb(void *addr, uint8_t val)
1044   -+{
1045   -+ *(volatile uint8_t *)addr = val;
1046   -+}
1047   -+
1048   -+static inline uint32_t readl(const void *addr)
1049   -+{
1050   -+ return *(volatile const uint32_t *)addr;
1051   -+}
1052   -+
1053   -+static inline uint16_t readw(const void *addr)
1054   -+{
1055   -+ return *(volatile const uint16_t *)addr;
1056   -+}
1057   -+
1058   -+static inline uint8_t readb(const void *addr)
1059   -+{
1060   -+ return *(volatile const uint8_t *)addr;
1061   -+}
1062   -+
1063   -+static inline void putc(int c)
1064   -+{
1065   -+ outb(INFO_PORT, c);
1066   -+}
1067   -+
1068   -+static inline int isdigit(int c)
1069   -+{
1070   -+ return c >= '0' && c <= '9';
1071   -+}
1072   -+
1073   -+void *memset(void *d1, int val, size_t len)
1074   -+{
1075   -+ uint8_t *d = d1;
1076   -+
1077   -+ while (len--) {
1078   -+ *d++ = val;
1079   -+ }
1080   -+ return d1;
1081   -+}
1082   -+
1083   -+void *memcpy(void *d1, const void *s1, size_t len)
1084   -+{
1085   -+ uint8_t *d = d1;
1086   -+ const uint8_t *s = s1;
1087   -+
1088   -+ while (len--) {
1089   -+ *d++ = *s++;
1090   -+ }
1091   -+ return d1;
1092   -+}
1093   -+
1094   -+void *memmove(void *d1, const void *s1, size_t len)
1095   -+{
1096   -+ uint8_t *d = d1;
1097   -+ const uint8_t *s = s1;
1098   -+
1099   -+ if (d <= s) {
1100   -+ while (len--) {
1101   -+ *d++ = *s++;
1102   -+ }
1103   -+ } else {
1104   -+ d += len;
1105   -+ s += len;
1106   -+ while (len--) {
1107   -+ *--d = *--s;
1108   -+ }
1109   -+ }
1110   -+ return d1;
1111   -+}
1112   -+
1113   -+size_t strlen(const char *s)
1114   -+{
1115   -+ const char *s1;
1116   -+ for(s1 = s; *s1 != '\0'; s1++);
1117   -+ return s1 - s;
1118   -+}
1119   -+
1120   -+/* from BSD ppp sources */
1121   -+int vsnprintf(char *buf, int buflen, const char *fmt, va_list args)
1122   -+{
1123   -+ int c, i, n;
1124   -+ int width, prec, fillch;
1125   -+ int base, len, neg;
1126   -+ unsigned long val = 0;
1127   -+ const char *f;
1128   -+ char *str, *buf0;
1129   -+ char num[32];
1130   -+ static const char hexchars[] = "0123456789abcdef";
1131   -+
1132   -+ buf0 = buf;
1133   -+ --buflen;
1134   -+ while (buflen > 0) {
1135   -+ for (f = fmt; *f != '%' && *f != 0; ++f)
1136   -+ ;
1137   -+ if (f > fmt) {
1138   -+ len = f - fmt;
1139   -+ if (len > buflen)
1140   -+ len = buflen;
1141   -+ memcpy(buf, fmt, len);
1142   -+ buf += len;
1143   -+ buflen -= len;
1144   -+ fmt = f;
1145   -+ }
1146   -+ if (*fmt == 0)
1147   -+ break;
1148   -+ c = *++fmt;
1149   -+ width = prec = 0;
1150   -+ fillch = ' ';
1151   -+ if (c == '0') {
1152   -+ fillch = '0';
1153   -+ c = *++fmt;
1154   -+ }
1155   -+ if (c == '*') {
1156   -+ width = va_arg(args, int);
1157   -+ c = *++fmt;
1158   -+ } else {
1159   -+ while (isdigit(c)) {
1160   -+ width = width * 10 + c - '0';
1161   -+ c = *++fmt;
1162   -+ }
1163   -+ }
1164   -+ if (c == '.') {
1165   -+ c = *++fmt;
1166   -+ if (c == '*') {
1167   -+ prec = va_arg(args, int);
1168   -+ c = *++fmt;
1169   -+ } else {
1170   -+ while (isdigit(c)) {
1171   -+ prec = prec * 10 + c - '0';
1172   -+ c = *++fmt;
1173   -+ }
1174   -+ }
1175   -+ }
1176   -+ /* modifiers */
1177   -+ switch(c) {
1178   -+ case 'l':
1179   -+ c = *++fmt;
1180   -+ break;
1181   -+ default:
1182   -+ break;
1183   -+ }
1184   -+ str = 0;
1185   -+ base = 0;
1186   -+ neg = 0;
1187   -+ ++fmt;
1188   -+ switch (c) {
1189   -+ case 'd':
1190   -+ i = va_arg(args, int);
1191   -+ if (i < 0) {
1192   -+ neg = 1;
1193   -+ val = -i;
1194   -+ } else
1195   -+ val = i;
1196   -+ base = 10;
1197   -+ break;
1198   -+ case 'o':
1199   -+ val = va_arg(args, unsigned int);
1200   -+ base = 8;
1201   -+ break;
1202   -+ case 'x':
1203   -+ case 'X':
1204   -+ val = va_arg(args, unsigned int);
1205   -+ base = 16;
1206   -+ break;
1207   -+ case 'p':
1208   -+ val = (unsigned long) va_arg(args, void *);
1209   -+ base = 16;
1210   -+ neg = 2;
1211   -+ break;
1212   -+ case 's':
1213   -+ str = va_arg(args, char *);
1214   -+ break;
1215   -+ case 'c':
1216   -+ num[0] = va_arg(args, int);
1217   -+ num[1] = 0;
1218   -+ str = num;
1219   -+ break;
1220   -+ default:
1221   -+ *buf++ = '%';
1222   -+ if (c != '%')
1223   -+ --fmt; /* so %z outputs %z etc. */
1224   -+ --buflen;
1225   -+ continue;
1226   -+ }
1227   -+ if (base != 0) {
1228   -+ str = num + sizeof(num);
1229   -+ *--str = 0;
1230   -+ while (str > num + neg) {
1231   -+ *--str = hexchars[val % base];
1232   -+ val = val / base;
1233   -+ if (--prec <= 0 && val == 0)
1234   -+ break;
1235   -+ }
1236   -+ switch (neg) {
1237   -+ case 1:
1238   -+ *--str = '-';
1239   -+ break;
1240   -+ case 2:
1241   -+ *--str = 'x';
1242   -+ *--str = '0';
1243   -+ break;
1244   -+ }
1245   -+ len = num + sizeof(num) - 1 - str;
1246   -+ } else {
1247   -+ len = strlen(str);
1248   -+ if (prec > 0 && len > prec)
1249   -+ len = prec;
1250   -+ }
1251   -+ if (width > 0) {
1252   -+ if (width > buflen)
1253   -+ width = buflen;
1254   -+ if ((n = width - len) > 0) {
1255   -+ buflen -= n;
1256   -+ for (; n > 0; --n)
1257   -+ *buf++ = fillch;
1258   -+ }
1259   -+ }
1260   -+ if (len > buflen)
1261   -+ len = buflen;
1262   -+ memcpy(buf, str, len);
1263   -+ buf += len;
1264   -+ buflen -= len;
1265   -+ }
1266   -+ *buf = 0;
1267   -+ return buf - buf0;
1268   -+}
1269   -+
1270   -+void bios_printf(int flags, const char *fmt, ...)
1271   -+{
1272   -+ va_list ap;
1273   -+ char buf[1024];
1274   -+ const char *s;
1275   -+
1276   -+ va_start(ap, fmt);
1277   -+ vsnprintf(buf, sizeof(buf), fmt, ap);
1278   -+ s = buf;
1279   -+ while (*s)
1280   -+ putc(*s++);
1281   -+ va_end(ap);
1282   -+}
1283   -+
1284   -+/* approximative ! */
1285   -+void delay_ms(int n)
1286   -+{
1287   -+ int i, j;
1288   -+ for(i = 0; i < n; i++) {
1289   -+ for(j = 0; j < 1000000; j++);
1290   -+ }
1291   -+}
1292   -+
1293   -+int smp_cpus;
1294   -+uint32_t cpuid_features;
1295   -+uint32_t cpuid_ext_features;
1296   -+unsigned long ram_size;
1297   -+#ifdef BX_USE_EBDA_TABLES
1298   -+unsigned long ebda_cur_addr;
1299   -+#endif
1300   -+int acpi_enabled;
1301   -+uint32_t pm_io_base;
1302   -+int pm_sci_int;
1303   -+unsigned long bios_table_cur_addr;
1304   -+unsigned long bios_table_end_addr;
1305   -+
1306   -+void cpu_probe(void)
1307   -+{
1308   -+ uint32_t eax, ebx, ecx, edx;
1309   -+ cpuid(1, eax, ebx, ecx, edx);
1310   -+ cpuid_features = edx;
1311   -+ cpuid_ext_features = ecx;
1312   -+}
1313   -+
1314   -+static int cmos_readb(int addr)
1315   -+{
1316   -+ outb(0x70, addr);
1317   -+ return inb(0x71);
1318   -+}
1319   -+
1320   -+void ram_probe(void)
1321   -+{
1322   -+ ram_size = (cmos_readb(0x34) | (cmos_readb(0x35) << 8)) * 65536 +
1323   -+ 16 * 1024 * 1024;
1324   -+#ifdef BX_USE_EBDA_TABLES
1325   -+ ebda_cur_addr = ((*(uint16_t *)(0x40e)) << 4) + 0x380;
1326   -+#endif
1327   -+ BX_INFO("ram_size=0x%08lx\n");
1328   -+}
1329   -+
1330   -+/****************************************************/
1331   -+/* SMP probe */
1332   -+
1333   -+extern uint8_t smp_ap_boot_code_start;
1334   -+extern uint8_t smp_ap_boot_code_end;
1335   -+
1336   -+/* find the number of CPUs by launching a SIPI to them */
1337   -+void smp_probe(void)
1338   -+{
1339   -+ uint32_t val, sipi_vector;
1340   -+
1341   -+ smp_cpus = 1;
1342   -+ if (cpuid_features & CPUID_APIC) {
1343   -+
1344   -+ /* enable local APIC */
1345   -+ val = readl(APIC_BASE + APIC_SVR);
1346   -+ val |= APIC_ENABLED;
1347   -+ writel(APIC_BASE + APIC_SVR, val);
1348   -+
1349   -+ writew((void *)CPU_COUNT_ADDR, 1);
1350   -+ /* copy AP boot code */
1351   -+ memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
1352   -+ &smp_ap_boot_code_end - &smp_ap_boot_code_start);
1353   -+
1354   -+ /* broadcast SIPI */
1355   -+ writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
1356   -+ sipi_vector = AP_BOOT_ADDR >> 12;
1357   -+ writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
1358   -+
1359   -+ delay_ms(10);
1360   -+
1361   -+ smp_cpus = readw((void *)CPU_COUNT_ADDR);
1362   -+ }
1363   -+ BX_INFO("Found %d cpus\n", smp_cpus);
1364   -+}
1365   -+
1366   -+/****************************************************/
1367   -+/* PCI init */
1368   -+
1369   -+#define PCI_ADDRESS_SPACE_MEM 0x00
1370   -+#define PCI_ADDRESS_SPACE_IO 0x01
1371   -+#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
1372   -+
1373   -+#define PCI_ROM_SLOT 6
1374   -+#define PCI_NUM_REGIONS 7
1375   -+
1376   -+#define PCI_DEVICES_MAX 64
1377   -+
1378   -+#define PCI_VENDOR_ID 0x00 /* 16 bits */
1379   -+#define PCI_DEVICE_ID 0x02 /* 16 bits */
1380   -+#define PCI_COMMAND 0x04 /* 16 bits */
1381   -+#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
1382   -+#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
1383   -+#define PCI_CLASS_DEVICE 0x0a /* Device class */
1384   -+#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
1385   -+#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
1386   -+#define PCI_MIN_GNT 0x3e /* 8 bits */
1387   -+#define PCI_MAX_LAT 0x3f /* 8 bits */
1388   -+
1389   -+typedef struct PCIDevice {
1390   -+ int bus;
1391   -+ int devfn;
1392   -+} PCIDevice;
1393   -+
1394   -+static uint32_t pci_bios_io_addr;
1395   -+static uint32_t pci_bios_mem_addr;
1396   -+/* host irqs corresponding to PCI irqs A-D */
1397   -+static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
1398   -+static PCIDevice i440_pcidev;
1399   -+
1400   -+static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
1401   -+{
1402   -+ outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
1403   -+ outl(0xcfc, val);
1404   -+}
1405   -+
1406   -+static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
1407   -+{
1408   -+ outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
1409   -+ outw(0xcfc + (addr & 2), val);
1410   -+}
1411   -+
1412   -+static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
1413   -+{
1414   -+ outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
1415   -+ outb(0xcfc + (addr & 3), val);
1416   -+}
1417   -+
1418   -+static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
1419   -+{
1420   -+ outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
1421   -+ return inl(0xcfc);
1422   -+}
1423   -+
1424   -+static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
1425   -+{
1426   -+ outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
1427   -+ return inw(0xcfc + (addr & 2));
1428   -+}
1429   -+
1430   -+static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
1431   -+{
1432   -+ outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
1433   -+ return inb(0xcfc + (addr & 3));
1434   -+}
1435   -+
1436   -+static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
1437   -+{
1438   -+ uint16_t cmd;
1439   -+ uint32_t ofs, old_addr;
1440   -+
1441   -+ if ( region_num == PCI_ROM_SLOT ) {
1442   -+ ofs = 0x30;
1443   -+ }else{
1444   -+ ofs = 0x10 + region_num * 4;
1445   -+ }
1446   -+
1447   -+ old_addr = pci_config_readl(d, ofs);
1448   -+
1449   -+ pci_config_writel(d, ofs, addr);
1450   -+ BX_INFO("region %d: 0x%08x\n", region_num, addr);
1451   -+
1452   -+ /* enable memory mappings */
1453   -+ cmd = pci_config_readw(d, PCI_COMMAND);
1454   -+ if ( region_num == PCI_ROM_SLOT )
1455   -+ cmd |= 2;
1456   -+ else if (old_addr & PCI_ADDRESS_SPACE_IO)
1457   -+ cmd |= 1;
1458   -+ else
1459   -+ cmd |= 2;
1460   -+ pci_config_writew(d, PCI_COMMAND, cmd);
1461   -+}
1462   -+
1463   -+/* return the global irq number corresponding to a given device irq
1464   -+ pin. We could also use the bus number to have a more precise
1465   -+ mapping. */
1466   -+static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
1467   -+{
1468   -+ int slot_addend;
1469   -+ slot_addend = (pci_dev->devfn >> 3) - 1;
1470   -+ return (irq_num + slot_addend) & 3;
1471   -+}
1472   -+
1473   -+static int find_bios_table_area(void)
1474   -+{
1475   -+ unsigned long addr;
1476   -+ for(addr = 0xf0000; addr < 0x100000; addr += 16) {
1477   -+ if (*(uint32_t *)addr == 0xaafb4442) {
1478   -+ bios_table_cur_addr = addr + 8;
1479   -+ bios_table_end_addr = bios_table_cur_addr + *(uint32_t *)(addr + 4);
1480   -+ BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
1481   -+ bios_table_cur_addr, bios_table_end_addr);
1482   -+ return 0;
1483   -+ }
1484   -+ }
1485   -+ return -1;
1486   -+}
1487   -+
1488   -+static void bios_shadow_init(PCIDevice *d)
1489   -+{
1490   -+ int v;
1491   -+
1492   -+ if (find_bios_table_area() < 0)
1493   -+ return;
1494   -+
1495   -+ /* remap the BIOS to shadow RAM an keep it read/write while we
1496   -+ are writing tables */
1497   -+ memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
1498   -+ v = pci_config_readb(d, 0x59);
1499   -+ v = (v & 0x0f) | (0x30);
1500   -+ pci_config_writeb(d, 0x59, v);
1501   -+ memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
1502   -+
1503   -+ i440_pcidev = *d;
1504   -+}
1505   -+
1506   -+static void bios_lock_shadow_ram(void)
1507   -+{
1508   -+ PCIDevice *d = &i440_pcidev;
1509   -+ int v;
1510   -+
1511   -+ v = pci_config_readb(d, 0x59);
1512   -+ v = (v & 0x0f) | (0x10);
1513   -+ pci_config_writeb(d, 0x59, v);
1514   -+}
  172 ++#include "rombios.h"
1515 173 +
1516   -+static void pci_bios_init_bridges(PCIDevice *d)
1517   -+{
1518   -+ uint16_t vendor_id, device_id;
1519   -+
1520   -+ vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1521   -+ device_id = pci_config_readw(d, PCI_DEVICE_ID);
1522   -+
1523   -+ if (vendor_id == 0x8086 && device_id == 0x7000) {
1524   -+ int i, irq;
1525   -+ uint8_t elcr[2];
1526   -+
1527   -+ /* PIIX3 bridge */
1528   -+
1529   -+ elcr[0] = 0x00;
1530   -+ elcr[1] = 0x00;
1531   -+ for(i = 0; i < 4; i++) {
1532   -+ irq = pci_irqs[i];
1533   -+ /* set to trigger level */
1534   -+ elcr[irq >> 3] |= (1 << (irq & 7));
1535   -+ /* activate irq remapping in PIIX */
1536   -+ pci_config_writeb(d, 0x60 + i, irq);
1537   -+ }
1538   -+ outb(0x4d0, elcr[0]);
1539   -+ outb(0x4d1, elcr[1]);
1540   -+ BX_INFO("PIIX3 init: elcr=%02x %02x\n",
1541   -+ elcr[0], elcr[1]);
1542   -+ } else if (vendor_id == 0x8086 && device_id == 0x1237) {
1543   -+ /* i440 PCI bridge */
1544   -+ bios_shadow_init(d);
1545   -+ }
1546   -+}
1547   -+
1548   -+extern uint8_t smm_relocation_start, smm_relocation_end;
1549   -+extern uint8_t smm_code_start, smm_code_end;
1550   -+
1551   -+#ifdef BX_USE_SMM
1552   -+static void smm_init(void)
1553   -+{
1554   -+ /* copy the SMM relocation code */
1555   -+ memcpy((void *)0x38000, &smm_relocation_start,
1556   -+ &smm_relocation_end - &smm_relocation_start);
1557   -+ /* raise an SMI interrupt */
1558   -+ outb(0xb2, 00);
1559   -+
1560   -+ /* enable the SMM memory window */
1561   -+ pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x40);
1562   -+
1563   -+ /* copy the SMM code */
1564   -+ memcpy((void *)0xa8000, &smm_code_start,
1565   -+ &smm_code_end - &smm_code_start);
1566   -+
1567   -+ /* close the SMM memory window and enable normal SMM */
1568   -+ pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
1569   -+}
1570   -+#endif
1571   -+
1572   -+static void pci_bios_init_device(PCIDevice *d)
1573   -+{
1574   -+ int class;
1575   -+ uint32_t *paddr;
1576   -+ int i, pin, pic_irq, vendor_id, device_id;
1577   -+
1578   -+ class = pci_config_readw(d, PCI_CLASS_DEVICE);
1579   -+ vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1580   -+ device_id = pci_config_readw(d, PCI_DEVICE_ID);
1581   -+ BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
1582   -+ d->bus, d->devfn, vendor_id, device_id);
1583   -+ switch(class) {
1584   -+ case 0x0101:
1585   -+ if (vendor_id == 0x8086 && device_id == 0x7010) {
1586   -+ /* PIIX3 IDE */
1587   -+ pci_config_writew(d, 0x40, 0x8000); // enable IDE0
1588   -+ pci_config_writew(d, 0x42, 0x8000); // enable IDE1
1589   -+ goto default_map;
1590   -+ } else {
1591   -+ /* IDE: we map it as in ISA mode */
1592   -+ pci_set_io_region_addr(d, 0, 0x1f0);
1593   -+ pci_set_io_region_addr(d, 1, 0x3f4);
1594   -+ pci_set_io_region_addr(d, 2, 0x170);
1595   -+ pci_set_io_region_addr(d, 3, 0x374);
1596   -+ }
1597   -+ break;
1598   -+ case 0x0300:
1599   -+ if (vendor_id != 0x1234)
1600   -+ goto default_map;
1601   -+ /* VGA: map frame buffer to default Bochs VBE address */
1602   -+ pci_set_io_region_addr(d, 0, 0xE0000000);
1603   -+ break;
1604   -+ case 0x0800:
1605   -+ /* PIC */
1606   -+ if (vendor_id == 0x1014) {
1607   -+ /* IBM */
1608   -+ if (device_id == 0x0046 || device_id == 0xFFFF) {
1609   -+ /* MPIC & MPIC2 */
1610   -+ pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
1611   -+ }
1612   -+ }
1613   -+ break;
1614   -+ case 0xff00:
1615   -+ if (vendor_id == 0x0106b &&
1616   -+ (device_id == 0x0017 || device_id == 0x0022)) {
1617   -+ /* macio bridge */
1618   -+ pci_set_io_region_addr(d, 0, 0x80800000);
1619   -+ }
1620   -+ break;
1621   -+ default:
1622   -+ default_map:
1623   -+ /* default memory mappings */
1624   -+ for(i = 0; i < PCI_NUM_REGIONS; i++) {
1625   -+ int ofs;
1626   -+ uint32_t val, size ;
1627   -+
1628   -+ if (i == PCI_ROM_SLOT)
1629   -+ ofs = 0x30;
1630   -+ else
1631   -+ ofs = 0x10 + i * 4;
1632   -+ pci_config_writel(d, ofs, 0xffffffff);
1633   -+ val = pci_config_readl(d, ofs);
1634   -+ if (val != 0) {
1635   -+ size = (~(val & ~0xf)) + 1;
1636   -+ if (val & PCI_ADDRESS_SPACE_IO)
1637   -+ paddr = &pci_bios_io_addr;
1638   -+ else
1639   -+ paddr = &pci_bios_mem_addr;
1640   -+ *paddr = (*paddr + size - 1) & ~(size - 1);
1641   -+ pci_set_io_region_addr(d, i, *paddr);
1642   -+ *paddr += size;
1643   -+ }
1644   -+ }
1645   -+ break;
1646   -+ }
1647   -+
1648   -+ /* map the interrupt */
1649   -+ pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
1650   -+ if (pin != 0) {
1651   -+ pin = pci_slot_get_pirq(d, pin - 1);
1652   -+ pic_irq = pci_irqs[pin];
1653   -+ pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
1654   -+ }
1655   -+
1656   -+ if (vendor_id == 0x8086 && device_id == 0x7113) {
1657   -+ /* PIIX4 Power Management device (for ACPI) */
1658   -+ pm_io_base = PM_IO_BASE;
1659   -+ pci_config_writel(d, 0x40, pm_io_base | 1);
1660   -+ pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
1661   -+ pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
1662   -+#ifdef BX_USE_SMM
1663   -+ smm_init();
1664   -+#endif
1665   -+ acpi_enabled = 1;
1666   -+ }
1667   -+}
1668   -+
1669   -+void pci_for_each_device(void (*init_func)(PCIDevice *d))
1670   -+{
1671   -+ PCIDevice d1, *d = &d1;
1672   -+ int bus, devfn;
1673   -+ uint16_t vendor_id, device_id;
1674   -+
1675   -+ for(bus = 0; bus < 1; bus++) {
1676   -+ for(devfn = 0; devfn < 256; devfn++) {
1677   -+ d->bus = bus;
1678   -+ d->devfn = devfn;
1679   -+ vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1680   -+ device_id = pci_config_readw(d, PCI_DEVICE_ID);
1681   -+ if (vendor_id != 0xffff || device_id != 0xffff) {
1682   -+ init_func(d);
1683   -+ }
1684   -+ }
1685   -+ }
1686   -+}
1687   -+
1688   -+void pci_bios_init(void)
1689   -+{
1690   -+ pci_bios_io_addr = 0xc000;
1691   -+ pci_bios_mem_addr = 0xf0000000;
1692   -+
1693   -+ pci_for_each_device(pci_bios_init_bridges);
1694   -+
1695   -+ pci_for_each_device(pci_bios_init_device);
1696   -+}
1697   -+
1698   -+/****************************************************/
1699   -+/* Multi Processor table init */
1700   -+
1701   -+static void putb(uint8_t **pp, int val)
1702   -+{
1703   -+ uint8_t *q;
1704   -+ q = *pp;
1705   -+ *q++ = val;
1706   -+ *pp = q;
1707   -+}
1708   -+
1709   -+static void putstr(uint8_t **pp, const char *str)
1710   -+{
1711   -+ uint8_t *q;
1712   -+ q = *pp;
1713   -+ while (*str)
1714   -+ *q++ = *str++;
1715   -+ *pp = q;
1716   -+}
1717   -+
1718   -+static void putle16(uint8_t **pp, int val)
1719   -+{
1720   -+ uint8_t *q;
1721   -+ q = *pp;
1722   -+ *q++ = val;
1723   -+ *q++ = val >> 8;
1724   -+ *pp = q;
1725   -+}
1726   -+
1727   -+static void putle32(uint8_t **pp, int val)
1728   -+{
1729   -+ uint8_t *q;
1730   -+ q = *pp;
1731   -+ *q++ = val;
1732   -+ *q++ = val >> 8;
1733   -+ *q++ = val >> 16;
1734   -+ *q++ = val >> 24;
1735   -+ *pp = q;
1736   -+}
1737   -+
1738   -+static int mpf_checksum(const uint8_t *data, int len)
1739   -+{
1740   -+ int sum, i;
1741   -+ sum = 0;
1742   -+ for(i = 0; i < len; i++)
1743   -+ sum += data[i];
1744   -+ return sum & 0xff;
1745   -+}
1746   -+
1747   -+static unsigned long align(unsigned long addr, unsigned long v)
1748   -+{
1749   -+ return (addr + v - 1) & ~(v - 1);
1750   -+}
1751   -+
1752   -+static void mptable_init(void)
1753   -+{
1754   -+ uint8_t *mp_config_table, *q, *float_pointer_struct;
1755   -+ int ioapic_id, i, len;
1756   -+ int mp_config_table_size;
1757   -+
1758   -+ if (smp_cpus <= 1)
1759   -+ return;
1760   -+
1761   -+#ifdef BX_USE_EBDA_TABLES
1762   -+ mp_config_table = (uint8_t *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
1763   -+#else
1764   -+ bios_table_cur_addr = align(bios_table_cur_addr, 16);
1765   -+ mp_config_table = (uint8_t *)bios_table_cur_addr;
1766   -+#endif
1767   -+ q = mp_config_table;
1768   -+ putstr(&q, "PCMP"); /* "PCMP signature */
1769   -+ putle16(&q, 0); /* table length (patched later) */
1770   -+ putb(&q, 4); /* spec rev */
1771   -+ putb(&q, 0); /* checksum (patched later) */
1772   -+ putstr(&q, "QEMUCPU "); /* OEM id */
1773   -+ putstr(&q, "0.1 "); /* vendor id */
1774   -+ putle32(&q, 0); /* OEM table ptr */
1775   -+ putle16(&q, 0); /* OEM table size */
1776   -+ putle16(&q, 20); /* entry count */
1777   -+ putle32(&q, 0xfee00000); /* local APIC addr */
1778   -+ putle16(&q, 0); /* ext table length */
1779   -+ putb(&q, 0); /* ext table checksum */
1780   -+ putb(&q, 0); /* reserved */
1781   -+
1782   -+ for(i = 0; i < smp_cpus; i++) {
1783   -+ putb(&q, 0); /* entry type = processor */
1784   -+ putb(&q, i); /* APIC id */
1785   -+ putb(&q, 0x11); /* local APIC version number */
1786   -+ if (i == 0)
1787   -+ putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
1788   -+ else
1789   -+ putb(&q, 1); /* cpu flags: enabled */
1790   -+ putb(&q, 0); /* cpu signature */
1791   -+ putb(&q, 6);
1792   -+ putb(&q, 0);
1793   -+ putb(&q, 0);
1794   -+ putle16(&q, 0x201); /* feature flags */
1795   -+ putle16(&q, 0);
1796   -+
1797   -+ putle16(&q, 0); /* reserved */
1798   -+ putle16(&q, 0);
1799   -+ putle16(&q, 0);
1800   -+ putle16(&q, 0);
1801   -+ }
1802   -+
1803   -+ /* isa bus */
1804   -+ putb(&q, 1); /* entry type = bus */
1805   -+ putb(&q, 0); /* bus ID */
1806   -+ putstr(&q, "ISA ");
1807   -+
1808   -+ /* ioapic */
1809   -+ ioapic_id = smp_cpus;
1810   -+ putb(&q, 2); /* entry type = I/O APIC */
1811   -+ putb(&q, ioapic_id); /* apic ID */
1812   -+ putb(&q, 0x11); /* I/O APIC version number */
1813   -+ putb(&q, 1); /* enable */
1814   -+ putle32(&q, 0xfec00000); /* I/O APIC addr */
1815   -+
1816   -+ /* irqs */
1817   -+ for(i = 0; i < 16; i++) {
1818   -+ putb(&q, 3); /* entry type = I/O interrupt */
1819   -+ putb(&q, 0); /* interrupt type = vectored interrupt */
1820   -+ putb(&q, 0); /* flags: po=0, el=0 */
1821   -+ putb(&q, 0);
1822   -+ putb(&q, 0); /* source bus ID = ISA */
1823   -+ putb(&q, i); /* source bus IRQ */
1824   -+ putb(&q, ioapic_id); /* dest I/O APIC ID */
1825   -+ putb(&q, i); /* dest I/O APIC interrupt in */
1826   -+ }
1827   -+ /* patch length */
1828   -+ len = q - mp_config_table;
1829   -+ mp_config_table[4] = len;
1830   -+ mp_config_table[5] = len >> 8;
1831   -+
1832   -+ mp_config_table[7] = -mpf_checksum(mp_config_table, q - mp_config_table);
1833   -+
1834   -+ mp_config_table_size = q - mp_config_table;
1835   -+
1836   -+#ifndef BX_USE_EBDA_TABLES
1837   -+ bios_table_cur_addr += mp_config_table_size;
1838   -+#endif
1839   -+
1840   -+ /* floating pointer structure */
1841   -+#ifdef BX_USE_EBDA_TABLES
1842   -+ ebda_cur_addr = align(ebda_cur_addr, 16);
1843   -+ float_pointer_struct = (uint8_t *)ebda_cur_addr;
1844   -+#else
1845   -+ bios_table_cur_addr = align(bios_table_cur_addr, 16);
1846   -+ float_pointer_struct = (uint8_t *)bios_table_cur_addr;
1847   -+#endif
1848   -+ q = float_pointer_struct;
1849   -+ putstr(&q, "_MP_");
1850   -+ /* pointer to MP config table */
1851   -+ putle32(&q, (unsigned long)mp_config_table);
1852   -+
1853   -+ putb(&q, 1); /* length in 16 byte units */
1854   -+ putb(&q, 4); /* MP spec revision */
1855   -+ putb(&q, 0); /* checksum (patched later) */
1856   -+ putb(&q, 0); /* MP feature byte 1 */
1857   -+
1858   -+ putb(&q, 0);
1859   -+ putb(&q, 0);
1860   -+ putb(&q, 0);
1861   -+ putb(&q, 0);
1862   -+ float_pointer_struct[10] =
1863   -+ -mpf_checksum(float_pointer_struct, q - float_pointer_struct);
1864   -+#ifdef BX_USE_EBDA_TABLES
1865   -+ ebda_cur_addr += (q - float_pointer_struct);
1866   -+#else
1867   -+ bios_table_cur_addr += (q - float_pointer_struct);
1868   -+#endif
1869   -+ BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
1870   -+ (unsigned long)float_pointer_struct,
1871   -+ (unsigned long)mp_config_table,
1872   -+ mp_config_table_size);
1873   -+}
1874   -+
1875   -+/****************************************************/
1876   -+/* ACPI tables init */
1877   -+
1878   -+/* Table structure from Linux kernel (the ACPI tables are under the
1879   -+ BSD license) */
1880   -+
1881   -+#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
1882   -+ uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
1883   -+ uint32_t length; /* Length of table, in bytes, including header */\
1884   -+ uint8_t revision; /* ACPI Specification minor version # */\
1885   -+ uint8_t checksum; /* To make sum of entire table == 0 */\
1886   -+ uint8_t oem_id [6]; /* OEM identification */\
1887   -+ uint8_t oem_table_id [8]; /* OEM table identification */\
1888   -+ uint32_t oem_revision; /* OEM revision number */\
1889   -+ uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
1890   -+ uint32_t asl_compiler_revision; /* ASL compiler revision number */
1891   -+
1892   -+
1893   -+struct acpi_table_header /* ACPI common table header */
1894   -+{
1895   -+ ACPI_TABLE_HEADER_DEF
1896   -+};
1897   -+
1898   -+struct rsdp_descriptor /* Root System Descriptor Pointer */
1899   -+{
1900   -+ uint8_t signature [8]; /* ACPI signature, contains "RSD PTR " */
1901   -+ uint8_t checksum; /* To make sum of struct == 0 */
1902   -+ uint8_t oem_id [6]; /* OEM identification */
1903   -+ uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
1904   -+ uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
1905   -+ uint32_t length; /* XSDT Length in bytes including hdr */
1906   -+ uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
1907   -+ uint8_t extended_checksum; /* Checksum of entire table */
1908   -+ uint8_t reserved [3]; /* Reserved field must be 0 */
1909   -+};
1910   -+
1911   -+/*
1912   -+ * ACPI 1.0 Root System Description Table (RSDT)
1913   -+ */
1914   -+struct rsdt_descriptor_rev1
1915   -+{
1916   -+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1917   -+ uint32_t table_offset_entry [2]; /* Array of pointers to other */
1918   -+ /* ACPI tables */
1919   -+};
1920   -+
1921   -+/*
1922   -+ * ACPI 1.0 Firmware ACPI Control Structure (FACS)
1923   -+ */
1924   -+struct facs_descriptor_rev1
1925   -+{
1926   -+ uint8_t signature[4]; /* ACPI Signature */
1927   -+ uint32_t length; /* Length of structure, in bytes */
1928   -+ uint32_t hardware_signature; /* Hardware configuration signature */
1929   -+ uint32_t firmware_waking_vector; /* ACPI OS waking vector */
1930   -+ uint32_t global_lock; /* Global Lock */
1931   -+ uint32_t S4bios_f : 1; /* Indicates if S4BIOS support is present */
1932   -+ uint32_t reserved1 : 31; /* Must be 0 */
1933   -+ uint8_t resverved3 [40]; /* Reserved - must be zero */
1934   -+};
1935   -+
1936   -+
1937   -+/*
1938   -+ * ACPI 1.0 Fixed ACPI Description Table (FADT)
1939   -+ */
1940   -+struct fadt_descriptor_rev1
1941   -+{
1942   -+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1943   -+ uint32_t firmware_ctrl; /* Physical address of FACS */
1944   -+ uint32_t dsdt; /* Physical address of DSDT */
1945   -+ uint8_t model; /* System Interrupt Model */
1946   -+ uint8_t reserved1; /* Reserved */
1947   -+ uint16_t sci_int; /* System vector of SCI interrupt */
1948   -+ uint32_t smi_cmd; /* Port address of SMI command port */
1949   -+ uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
1950   -+ uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
1951   -+ uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
1952   -+ uint8_t reserved2; /* Reserved - must be zero */
1953   -+ uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
1954   -+ uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
1955   -+ uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
1956   -+ uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
1957   -+ uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
1958   -+ uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
1959   -+ uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
1960   -+ uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
1961   -+ uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
1962   -+ uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
1963   -+ uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
1964   -+ uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
1965   -+ uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
1966   -+ uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
1967   -+ uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
1968   -+ uint8_t reserved3; /* Reserved */
1969   -+ uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
1970   -+ uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
1971   -+ uint16_t flush_size; /* Size of area read to flush caches */
1972   -+ uint16_t flush_stride; /* Stride used in flushing caches */
1973   -+ uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
1974   -+ uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
1975   -+ uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
1976   -+ uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
1977   -+ uint8_t century; /* Index to century in RTC CMOS RAM */
1978   -+ uint8_t reserved4; /* Reserved */
1979   -+ uint8_t reserved4a; /* Reserved */
1980   -+ uint8_t reserved4b; /* Reserved */
1981   -+#if 0
1982   -+ uint32_t wb_invd : 1; /* The wbinvd instruction works properly */
1983   -+ uint32_t wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
1984   -+ uint32_t proc_c1 : 1; /* All processors support C1 state */
1985   -+ uint32_t plvl2_up : 1; /* C2 state works on MP system */
1986   -+ uint32_t pwr_button : 1; /* Power button is handled as a generic feature */
1987   -+ uint32_t sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
1988   -+ uint32_t fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
1989   -+ uint32_t rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
1990   -+ uint32_t tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
1991   -+ uint32_t reserved5 : 23; /* Reserved - must be zero */
1992   -+#else
1993   -+ uint32_t flags;
1994   -+#endif
1995   -+};
1996   -+
1997   -+/*
1998   -+ * MADT values and structures
1999   -+ */
2000   -+
2001   -+/* Values for MADT PCATCompat */
2002   -+
2003   -+#define DUAL_PIC 0
2004   -+#define MULTIPLE_APIC 1
2005   -+
2006   -+
2007   -+/* Master MADT */
2008   -+
2009   -+struct multiple_apic_table
2010   -+{
2011   -+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
2012   -+ uint32_t local_apic_address; /* Physical address of local APIC */
2013   -+#if 0
2014   -+ uint32_t PCATcompat : 1; /* A one indicates system also has dual 8259s */
2015   -+ uint32_t reserved1 : 31;
2016   -+#else
2017   -+ uint32_t flags;
2018   -+#endif
2019   -+};
2020   -+
2021   -+
2022   -+/* Values for Type in APIC_HEADER_DEF */
2023   -+
2024   -+#define APIC_PROCESSOR 0
2025   -+#define APIC_IO 1
2026   -+#define APIC_XRUPT_OVERRIDE 2
2027   -+#define APIC_NMI 3
2028   -+#define APIC_LOCAL_NMI 4
2029   -+#define APIC_ADDRESS_OVERRIDE 5
2030   -+#define APIC_IO_SAPIC 6
2031   -+#define APIC_LOCAL_SAPIC 7
2032   -+#define APIC_XRUPT_SOURCE 8
2033   -+#define APIC_RESERVED 9 /* 9 and greater are reserved */
2034   -+
2035   -+/*
2036   -+ * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
2037   -+ */
2038   -+#define APIC_HEADER_DEF /* Common APIC sub-structure header */\
2039   -+ uint8_t type; \
2040   -+ uint8_t length;
2041   -+
2042   -+/* Sub-structures for MADT */
2043   -+
2044   -+struct madt_processor_apic
2045   -+{
2046   -+ APIC_HEADER_DEF
2047   -+ uint8_t processor_id; /* ACPI processor id */
2048   -+ uint8_t local_apic_id; /* Processor's local APIC id */
2049   -+#if 0
2050   -+ uint32_t processor_enabled: 1; /* Processor is usable if set */
2051   -+ uint32_t reserved2 : 31; /* Reserved, must be zero */
2052   -+#else
2053   -+ uint32_t flags;
2054   -+#endif
2055   -+};
2056   -+
2057   -+struct madt_io_apic
2058   -+{
2059   -+ APIC_HEADER_DEF
2060   -+ uint8_t io_apic_id; /* I/O APIC ID */
2061   -+ uint8_t reserved; /* Reserved - must be zero */
2062   -+ uint32_t address; /* APIC physical address */
2063   -+ uint32_t interrupt; /* Global system interrupt where INTI
2064   -+ * lines start */
2065   -+};
2066   -+
2067   -+#include "acpi-dsdt.hex"
2068   -+
2069   -+static inline uint16_t cpu_to_le16(uint16_t x)
2070   -+{
2071   -+ return x;
2072   -+}
2073   -+
2074   -+static inline uint32_t cpu_to_le32(uint32_t x)
2075   -+{
2076   -+ return x;
2077   -+}
2078   -+
2079   -+static int acpi_checksum(const uint8_t *data, int len)
2080   -+{
2081   -+ int sum, i;
2082   -+ sum = 0;
2083   -+ for(i = 0; i < len; i++)
2084   -+ sum += data[i];
2085   -+ return (-sum) & 0xff;
2086   -+}
2087   -+
2088   -+static void acpi_build_table_header(struct acpi_table_header *h,
2089   -+ char *sig, int len)
2090   -+{
2091   -+ memcpy(h->signature, sig, 4);
2092   -+ h->length = cpu_to_le32(len);
2093   -+ h->revision = 0;
2094   -+ memcpy(h->oem_id, "QEMU ", 6);
2095   -+ memcpy(h->oem_table_id, "QEMU", 4);
2096   -+ memcpy(h->oem_table_id + 4, sig, 4);
2097   -+ h->oem_revision = cpu_to_le32(1);
2098   -+ memcpy(h->asl_compiler_id, "QEMU", 4);
2099   -+ h->asl_compiler_revision = cpu_to_le32(1);
2100   -+ h->checksum = acpi_checksum((void *)h, len);
2101   -+}
2102   -+
2103   -+/* base_addr must be a multiple of 4KB */
2104   -+void acpi_bios_init(void)
2105   -+{
2106   -+ struct rsdp_descriptor *rsdp;
2107   -+ struct rsdt_descriptor_rev1 *rsdt;
2108   -+ struct fadt_descriptor_rev1 *fadt;
2109   -+ struct facs_descriptor_rev1 *facs;
2110   -+ struct multiple_apic_table *madt;
2111   -+ uint8_t *dsdt;
2112   -+ uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr;
2113   -+ uint32_t acpi_tables_size, madt_addr, madt_size;
2114   -+ int i;
2115   -+
2116   -+ /* reserve memory space for tables */
2117   -+#ifdef BX_USE_EBDA_TABLES
2118   -+ ebda_cur_addr = align(ebda_cur_addr, 16);
2119   -+ rsdp = (void *)(ebda_cur_addr);
2120   -+ ebda_cur_addr += sizeof(*rsdp);
2121   -+#else
2122   -+ bios_table_cur_addr = align(bios_table_cur_addr, 16);
2123   -+ rsdp = (void *)(bios_table_cur_addr);
2124   -+ bios_table_cur_addr += sizeof(*rsdp);
2125   -+#endif
2126   -+
2127   -+ addr = base_addr = ram_size - ACPI_DATA_SIZE;
2128   -+ rsdt_addr = addr;
2129   -+ rsdt = (void *)(addr);
2130   -+ addr += sizeof(*rsdt);
2131   -+
2132   -+ fadt_addr = addr;
2133   -+ fadt = (void *)(addr);
2134   -+ addr += sizeof(*fadt);
2135   -+
2136   -+ /* XXX: FACS should be in RAM */
2137   -+ addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
2138   -+ facs_addr = addr;
2139   -+ facs = (void *)(addr);
2140   -+ addr += sizeof(*facs);
2141   -+
2142   -+ dsdt_addr = addr;
2143   -+ dsdt = (void *)(addr);
2144   -+ addr += sizeof(AmlCode);
2145   -+
2146   -+ addr = (addr + 7) & ~7;
2147   -+ madt_addr = addr;
2148   -+ madt_size = sizeof(*madt) +
2149   -+ sizeof(struct madt_processor_apic) * smp_cpus +
2150   -+ sizeof(struct madt_io_apic);
2151   -+ madt = (void *)(addr);
2152   -+ addr += madt_size;
2153   -+
2154   -+ acpi_tables_size = addr - base_addr;
2155   -+
2156   -+ BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
2157   -+ (unsigned long)rsdp,
2158   -+ (unsigned long)rsdt, acpi_tables_size);
2159   -+
2160   -+ /* RSDP */
2161   -+ memset(rsdp, 0, sizeof(*rsdp));
2162   -+ memcpy(rsdp->signature, "RSD PTR ", 8);
2163   -+ memcpy(rsdp->oem_id, "QEMU ", 6);
2164   -+ rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
2165   -+ rsdp->checksum = acpi_checksum((void *)rsdp, 20);
2166   -+
2167   -+ /* RSDT */
2168   -+ rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
2169   -+ rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
2170   -+ acpi_build_table_header((struct acpi_table_header *)rsdt,
2171   -+ "RSDT", sizeof(*rsdt));
2172   -+
2173   -+ /* FADT */
2174   -+ memset(fadt, 0, sizeof(*fadt));
2175   -+ fadt->firmware_ctrl = cpu_to_le32(facs_addr);
2176   -+ fadt->dsdt = cpu_to_le32(dsdt_addr);
2177   -+ fadt->model = 1;
2178   -+ fadt->reserved1 = 0;
2179   -+ fadt->sci_int = cpu_to_le16(pm_sci_int);
2180   -+ fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
2181   -+ fadt->acpi_enable = 0xf1;
2182   -+ fadt->acpi_disable = 0xf0;
2183   -+ fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
2184   -+ fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
2185   -+ fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
2186   -+ fadt->pm1_evt_len = 4;
2187   -+ fadt->pm1_cnt_len = 2;
2188   -+ fadt->pm_tmr_len = 4;
2189   -+ fadt->plvl2_lat = cpu_to_le16(50);
2190   -+ fadt->plvl3_lat = cpu_to_le16(50);
2191   -+ fadt->plvl3_lat = cpu_to_le16(50);
2192   -+ /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
2193   -+ fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
2194   -+ acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
2195   -+ sizeof(*fadt));
2196   -+
2197   -+ /* FACS */
2198   -+ memset(facs, 0, sizeof(*facs));
2199   -+ memcpy(facs->signature, "FACS", 4);
2200   -+ facs->length = cpu_to_le32(sizeof(*facs));
2201   -+
2202   -+ /* DSDT */
2203   -+ memcpy(dsdt, AmlCode, sizeof(AmlCode));
2204   -+
2205   -+ /* MADT */
2206   -+ {
2207   -+ struct madt_processor_apic *apic;
2208   -+ struct madt_io_apic *io_apic;
2209   -+
2210   -+ memset(madt, 0, madt_size);
2211   -+ madt->local_apic_address = cpu_to_le32(0xfee00000);
2212   -+ madt->flags = cpu_to_le32(1);
2213   -+ apic = (void *)(madt + 1);
2214   -+ for(i=0;i<smp_cpus;i++) {
2215   -+ apic->type = APIC_PROCESSOR;
2216   -+ apic->length = sizeof(*apic);
2217   -+ apic->processor_id = i;
2218   -+ apic->local_apic_id = i;
2219   -+ apic->flags = cpu_to_le32(1);
2220   -+ apic++;
2221   -+ }
2222   -+ io_apic = (void *)apic;
2223   -+ io_apic->type = APIC_IO;
2224   -+ io_apic->length = sizeof(*io_apic);
2225   -+ io_apic->io_apic_id = smp_cpus;
2226   -+ io_apic->address = cpu_to_le32(0xfec00000);
2227   -+ io_apic->interrupt = cpu_to_le32(0);
2228   -+
2229   -+ acpi_build_table_header((struct acpi_table_header *)madt,
2230   -+ "APIC", madt_size);
2231   -+ }
2232   -+}
2233   -+
2234   -+void rombios32_init(void)
2235   -+{
2236   -+ BX_INFO("Starting rombios32\n");
2237   -+
2238   -+ ram_probe();
2239   -+
2240   -+ cpu_probe();
2241   -+
2242   -+ smp_probe();
2243   -+
2244   -+ pci_bios_init();
2245   -+
2246   -+ if (bios_table_cur_addr != 0) {
2247   -+
2248   -+ mptable_init();
2249   -+
2250   -+ if (acpi_enabled)
2251   -+ acpi_bios_init();
2252   -+
2253   -+ bios_lock_shadow_ram();
2254   -+ }
2255   -+}
2256   -diff -ruN --exclude Makefile bios.org/rombios32.ld bios/rombios32.ld
2257   ---- bios.org/rombios32.ld 1970-01-01 01:00:00.000000000 +0100
2258   -+++ bios/rombios32.ld 2006-09-24 20:28:05.000000000 +0200
2259   -@@ -0,0 +1,19 @@
2260   -+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
2261   -+OUTPUT_ARCH(i386)
2262   -+ENTRY(_start);
2263   -+SECTIONS
2264   -+{
2265   -+ . = 0x00040000;
2266   -+ .text : { *(.text) }
2267   -+ .rodata : { *(.rodata) }
2268   -+ . = ALIGN(4096);
2269   -+ .data : { *(.data) }
2270   -+ __bss_start = . ;
2271   -+ .bss : { *(.bss) *(COMMON) }
2272   -+ _end = . ;
2273   -+ /DISCARD/ : { *(.stab)
2274   -+ *(.stabstr)
2275   -+ *(.comment)
2276   -+ *(.note)
2277   -+ }
2278   -+}
2279   -diff -ruN --exclude Makefile bios.org/rombios32start.S bios/rombios32start.S
2280   ---- bios.org/rombios32start.S 1970-01-01 01:00:00.000000000 +0100
2281   -+++ bios/rombios32start.S 2006-09-24 20:22:58.000000000 +0200
2282   -@@ -0,0 +1,76 @@
2283   -+.globl _start
2284   -+.globl smp_ap_boot_code_start
2285   -+.globl smp_ap_boot_code_end
2286   -+.global smm_relocation_start
2287   -+.global smm_relocation_end
2288   -+.global smm_code_start
2289   -+.global smm_code_end
2290   -+
2291   -+#define PM_IO_BASE 0xb000
2292   -+
2293   -+_start:
2294   -+ /* clear bss section */
2295   -+ xor %eax, %eax
2296   -+ mov $__bss_start, %edi
2297   -+ mov $_end, %ecx
2298   -+ sub %edi, %ecx
2299   -+ rep stosb
2300   -+
2301   -+ jmp rombios32_init
2302   -+
2303   -+#define CPU_COUNT 0xf000
2304   -+
2305   -+ .code16
2306   -+smp_ap_boot_code_start:
2307   -+ xor %ax, %ax
2308   -+ mov %ax, %ds
2309   -+ incw CPU_COUNT
2310   -+1:
2311   -+ hlt
2312   -+ jmp 1b
2313   -+smp_ap_boot_code_end:
2314   -+
2315   -+/* code to relocate SMBASE to 0xa0000 */
2316   -+smm_relocation_start:
2317   -+ mov $0x38000 + 0x7efc, %ebx
2318   -+ mov (%ebx), %al /* revision ID to see if x86_64 or x86 */
2319   -+ cmp $0x64, %al
2320   -+ je 1f
2321   -+ mov $0x38000 + 0x7ef8, %ebx
2322   -+ jmp 2f
2323   -+1:
2324   -+ mov $0x38000 + 0x7f00, %ebx
2325   -+2:
2326   -+ movl $0xa0000, %eax
2327   -+ movl %eax, (%ebx)
2328   -+ rsm
2329   -+smm_relocation_end:
2330   -+
2331   -+/* minimal SMM code to enable or disable ACPI */
2332   -+smm_code_start:
2333   -+ movw $0xb2, %dx
2334   -+ inb %dx, %al
2335   -+ cmp $0xf0, %al
2336   -+ jne 1f
2337   -+
2338   -+ /* ACPI disable */
2339   -+ mov $PM_IO_BASE + 0x04, %dx /* PMCNTRL */
2340   -+ inw %dx, %ax
2341   -+ andw $~1, %ax
2342   -+ outw %ax, %dx
2343   -+
2344   -+ jmp 2f
2345   -+
2346   -+1:
2347   -+ cmp $0xf1, %al
2348   -+ jne 2f
2349   -+
2350   -+ /* ACPI enable */
2351   -+ mov $PM_IO_BASE + 0x04, %dx /* PMCNTRL */
2352   -+ inw %dx, %ax
2353   -+ orw $1, %ax
2354   -+ outw %ax, %dx
2355   -+
2356   -+2:
2357   -+ rsm
2358   -+smm_code_end:
2359   -diff -ruN --exclude Makefile bios.org/rombios.c bios/rombios.c
2360   ---- bios.org/rombios.c 2006-08-11 19:34:12.000000000 +0200
2361   -+++ bios/rombios.c 2006-09-24 20:35:47.000000000 +0200
2362   -@@ -24,7 +24,7 @@
2363   - // License along with this library; if not, write to the Free Software
2364   - // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
2365   -
2366   --// ROM BIOS for use with Bochs/Plex x86 emulation environment
2367   -+// ROM BIOS for use with Bochs/Plex x86/QEMU emulation environment
2368   -
2369   -
2370   - // ROM BIOS compatability entry points:
2371   -@@ -143,6 +143,7 @@
2372   - #define BX_FLOPPY_ON_CNT 37 /* 2 seconds */
2373   - #define BX_PCIBIOS 1
2374   - #define BX_APM 1
2375   -+#define BX_ROMBIOS32 1
2376   -
2377   - #define BX_USE_ATADRV 1
2378   - #define BX_ELTORITO_BOOT 1
2379   -@@ -159,6 +160,9 @@
2380   - #define BIOS_REVISION 1
2381   - #define BIOS_CONFIG_TABLE 0xe6f5
2382   -
2383   -+/* define it to include QEMU specific code */
2384   -+#define BX_QEMU
2385   -+
2386   - #ifndef BIOS_BUILD_DATE
2387   - # define BIOS_BUILD_DATE "06/23/99"
2388   - #endif
2389   -@@ -170,7 +174,9 @@
2390   - #define BASE_MEM_IN_K (640 - EBDA_SIZE)
2391   -
2392   - // Define the application NAME
2393   --#ifdef PLEX86
2394   -+#if defined(BX_QEMU)
2395   -+# define BX_APPNAME "QEMU"
2396   -+#elif defined(PLEX86)
2397   - # define BX_APPNAME "Plex86"
2398   - #else
2399   - # define BX_APPNAME "Bochs"
2400   -@@ -1826,6 +1832,9 @@
2401   - #ifdef BX_ELTORITO_BOOT
2402   - "eltorito "
2403   - #endif
2404   -+#ifdef BX_ROMBIOS32
2405   -+ "rombios32 "
2406   -+#endif
2407   - "\n\n");
2408   - }
  174 + .globl _start
  175 + .globl smp_ap_boot_code_start
  176 + .globl smp_ap_boot_code_end
  177 +@@ -6,8 +28,6 @@
  178 + .global smm_code_start
  179 + .global smm_code_end
2409 180  
2410   -@@ -4085,6 +4094,24 @@
2411   - case 0x20: // coded by osmaker aka K.J.
2412   - if(regs.u.r32.edx == 0x534D4150)
2413   - {
2414   -+ extended_memory_size = inb_cmos(0x35);
2415   -+ extended_memory_size <<= 8;
2416   -+ extended_memory_size |= inb_cmos(0x34);
2417   -+ extended_memory_size *= 64;
2418   -+ // greater than EFF00000???
2419   -+ if(extended_memory_size > 0x3bc000) {
2420   -+ extended_memory_size = 0x3bc000; // everything after this is reserved memory until we get to 0x100000000
2421   -+ }
2422   -+ extended_memory_size *= 1024;
2423   -+ extended_memory_size += (16L * 1024 * 1024);
2424   -+
2425   -+ if(extended_memory_size <= (16L * 1024 * 1024)) {
2426   -+ extended_memory_size = inb_cmos(0x31);
2427   -+ extended_memory_size <<= 8;
2428   -+ extended_memory_size |= inb_cmos(0x30);
2429   -+ extended_memory_size *= 1024;
2430   -+ }
2431   -+
2432   - switch(regs.u.r16.bx)
2433   - {
2434   - case 0:
2435   -@@ -4115,27 +4142,9 @@
2436   - return;
2437   - break;
2438   - case 3:
2439   -- extended_memory_size = inb_cmos(0x35);
2440   -- extended_memory_size <<= 8;
2441   -- extended_memory_size |= inb_cmos(0x34);
2442   -- extended_memory_size *= 64;
2443   -- if(extended_memory_size > 0x3bc000) // greater than EFF00000???
2444   -- {
2445   -- extended_memory_size = 0x3bc000; // everything after this is reserved memory until we get to 0x100000000
2446   -- }
2447   -- extended_memory_size *= 1024;
2448   -- extended_memory_size += (16L * 1024 * 1024);
  181 +-#define PM_IO_BASE 0xb000
2449 182 -
2450   -- if(extended_memory_size <= (16L * 1024 * 1024))
2451   -- {
2452   -- extended_memory_size = inb_cmos(0x31);
2453   -- extended_memory_size <<= 8;
2454   -- extended_memory_size |= inb_cmos(0x30);
2455   -- extended_memory_size *= 1024;
2456   -- }
2457   --
2458   - set_e820_range(ES, regs.u.r16.di,
2459   -- 0x00100000L, extended_memory_size, 1);
2460   -+ 0x00100000L,
2461   -+ extended_memory_size - 0x10000L, 1);
2462   - regs.u.r32.ebx = 4;
2463   - regs.u.r32.eax = 0x534D4150;
2464   - regs.u.r32.ecx = 0x14;
2465   -@@ -4143,6 +4152,16 @@
2466   - return;
2467   - break;
2468   - case 4:
2469   -+ set_e820_range(ES, regs.u.r16.di,
2470   -+ extended_memory_size - 0x10000L,
2471   -+ extended_memory_size, 3); // ACPI RAM
2472   -+ regs.u.r32.ebx = 5;
2473   -+ regs.u.r32.eax = 0x534D4150;
2474   -+ regs.u.r32.ecx = 0x14;
2475   -+ CLEAR_CF();
2476   -+ return;
2477   -+ break;
2478   -+ case 5:
2479   - /* 256KB BIOS area at the end of 4 GB */
2480   - set_e820_range(ES, regs.u.r16.di,
2481   - 0xfffc0000L, 0x00000000L, 2);
2482   -@@ -8757,6 +8776,9 @@
2483   - unknown_service:
2484   - mov al, #0x80
2485   - bios32_end:
2486   -+#ifdef BX_QEMU
2487   -+ and dword ptr[esp+8],0xfffffffc ;; reset CS.RPL for kqemu
2488   -+#endif
2489   - popf
2490   - retf
2491   -
2492   -@@ -8868,6 +8890,9 @@
2493   - pci_pro_fail:
2494   - pop edi
2495   - pop esi
2496   -+#ifdef BX_QEMU
2497   -+ and dword ptr[esp+8],0xfffffffc ;; reset CS.RPL for kqemu
2498   -+#endif
2499   - popf
2500   - stc
2501   - retf
2502   -@@ -8875,6 +8900,9 @@
2503   - xor ah, ah
2504   - pop edi
2505   - pop esi
2506   -+#ifdef BX_QEMU
2507   -+ and dword ptr[esp+8],0xfffffffc ;; reset CS.RPL for kqemu
2508   -+#endif
2509   - popf
2510   - clc
2511   - retf
2512   -@@ -9183,227 +9211,118 @@
2513   - db 0 ;; reserved
2514   - pci_routing_table_structure_end:
  183 + _start:
  184 + /* clear bss section */
  185 + xor %eax, %eax
  186 +@@ -18,13 +38,11 @@
2515 187  
2516   --pci_irq_list:
2517   -- db 11, 10, 9, 5;
2518   -+#endif // BX_PCIBIOS
  188 + jmp rombios32_init
2519 189  
2520   --pcibios_init_sel_reg:
2521   -- push eax
2522   -- mov eax, #0x800000
2523   -- mov ax, bx
2524   -- shl eax, #8
2525   -- and dl, #0xfc
2526   -- or al, dl
2527   -- mov dx, #0x0cf8
2528   -- out dx, eax
2529   -- pop eax
2530   -- ret
2531   --
2532   --pcibios_init_iomem_bases:
2533   -- push bp
2534   -- mov bp, sp
2535   -- mov eax, #0xe0000000 ;; base for memory init
2536   -- push eax
2537   -- mov ax, #0xc000 ;; base for i/o init
2538   -- push ax
2539   -- mov ax, #0x0010 ;; start at base address #0
2540   -+#if BX_ROMBIOS32
2541   -+rombios32_init:
2542   -+ ;; save a20 and enable it
2543   -+ in al, 0x92
2544   - push ax
2545   -- mov bx, #0x0008
2546   --pci_init_io_loop1:
2547   -- mov dl, #0x00
2548   -- call pcibios_init_sel_reg
2549   -- mov dx, #0x0cfc
2550   -- in ax, dx
2551   -- cmp ax, #0xffff
2552   -- jz next_pci_dev
2553   -- mov dl, #0x04 ;; disable i/o and memory space access
2554   -- call pcibios_init_sel_reg
2555   -- mov dx, #0x0cfc
2556   -- in al, dx
2557   -- and al, #0xfc
2558   -- out dx, al
2559   --pci_init_io_loop2:
2560   -- mov dl, [bp-8]
2561   -- call pcibios_init_sel_reg
2562   -- mov dx, #0x0cfc
2563   -- in eax, dx
2564   -- test al, #0x01
2565   -- jnz init_io_base
2566   -- mov ecx, eax
2567   -- mov eax, #0xffffffff
2568   -- out dx, eax
2569   -- in eax, dx
2570   -- cmp eax, ecx
2571   -- je next_pci_base
2572   -- xor eax, #0xffffffff
2573   -- mov ecx, eax
2574   -- mov eax, [bp-4]
2575   -- out dx, eax
2576   -- add eax, ecx ;; calculate next free mem base
2577   -- add eax, #0x01000000
2578   -- and eax, #0xff000000
2579   -- mov [bp-4], eax
2580   -- jmp next_pci_base
2581   --init_io_base:
2582   -- mov cx, ax
2583   -- mov ax, #0xffff
2584   -- out dx, ax
2585   -- in ax, dx
2586   -- cmp ax, cx
2587   -- je next_pci_base
2588   -- xor ax, #0xfffe
2589   -- mov cx, ax
2590   -- mov ax, [bp-6]
2591   -- out dx, ax
2592   -- add ax, cx ;; calculate next free i/o base
2593   -- add ax, #0x0100
2594   -- and ax, #0xff00
2595   -- mov [bp-6], ax
2596   --next_pci_base:
2597   -- mov al, [bp-8]
2598   -- add al, #0x04
2599   -- cmp al, #0x28
2600   -- je enable_iomem_space
2601   -- mov byte ptr[bp-8], al
2602   -- jmp pci_init_io_loop2
2603   --enable_iomem_space:
2604   -- mov dl, #0x04 ;; enable i/o and memory space access if available
2605   -- call pcibios_init_sel_reg
2606   -- mov dx, #0x0cfc
2607   -- in al, dx
2608   -- or al, #0x07
2609   -- out dx, al
2610   --next_pci_dev:
2611   -- mov byte ptr[bp-8], #0x10
2612   -- inc bx
2613   -- cmp bx, #0x0100
2614   -- jne pci_init_io_loop1
2615   -- mov sp, bp
2616   -- pop bp
2617   -- ret
2618   -+ or al, #0x02
2619   -+ out 0x92, al
2620   -
2621   --pcibios_init_set_elcr:
2622   -- push ax
2623   -- push cx
2624   -- mov dx, #0x04d0
2625   -- test al, #0x08
2626   -- jz is_master_pic
2627   -- inc dx
2628   -- and al, #0x07
2629   --is_master_pic:
2630   -- mov cl, al
2631   -- mov bl, #0x01
2632   -- shl bl, cl
2633   -- in al, dx
2634   -- or al, bl
2635   -- out dx, al
2636   -- pop cx
2637   -- pop ax
2638   -- ret
2639   -+ ;; save SS:SP to the BDA
2640   -+ xor ax, ax
2641   -+ mov ds, ax
2642   -+ mov 0x0469, ss
2643   -+ mov 0x0467, sp
2644   -
2645   --pcibios_init_irqs:
2646   -- push ds
2647   -- push bp
2648   -- mov ax, #0xf000
2649   -- mov ds, ax
2650   -- mov dx, #0x04d0 ;; reset ELCR1 + ELCR2
2651   -- mov al, #0x00
2652   -- out dx, al
2653   -- inc dx
2654   -- out dx, al
2655   -- mov si, #pci_routing_table_structure
2656   -- mov bh, [si+8]
2657   -- mov bl, [si+9]
2658   -- mov dl, #0x00
2659   -- call pcibios_init_sel_reg
2660   -- mov dx, #0x0cfc
2661   -- in eax, dx
2662   -- cmp eax, [si+12] ;; check irq router
2663   -- jne pci_init_end
2664   -- mov dl, [si+34]
2665   -- call pcibios_init_sel_reg
2666   -- push bx ;; save irq router bus + devfunc
2667   -- mov dx, #0x0cfc
2668   -- mov ax, #0x8080
2669   -- out dx, ax ;; reset PIRQ route control
2670   -- inc dx
2671   -- inc dx
2672   -- out dx, ax
2673   -- mov ax, [si+6]
2674   -- sub ax, #0x20
2675   -- shr ax, #4
2676   -- mov cx, ax
2677   -- add si, #0x20 ;; set pointer to 1st entry
2678   -- mov bp, sp
2679   -- mov ax, #pci_irq_list
2680   -- push ax
2681   -- xor ax, ax
2682   -- push ax
2683   --pci_init_irq_loop1:
2684   -- mov bh, [si]
2685   -- mov bl, [si+1]
2686   --pci_init_irq_loop2:
2687   -- mov dl, #0x00
2688   -- call pcibios_init_sel_reg
2689   -- mov dx, #0x0cfc
2690   -- in ax, dx
2691   -- cmp ax, #0xffff
2692   -- jnz pci_test_int_pin
2693   -- test bl, #0x07
2694   -- jz next_pir_entry
2695   -- jmp next_pci_func
2696   --pci_test_int_pin:
2697   -- mov dl, #0x3c
2698   -- call pcibios_init_sel_reg
2699   -- mov dx, #0x0cfd
2700   -- in al, dx
2701   -- and al, #0x07
2702   -- jz next_pci_func
2703   -- dec al ;; determine pirq reg
2704   -- mov dl, #0x03
2705   -- mul al, dl
2706   -- add al, #0x02
2707   -- xor ah, ah
2708   -- mov bx, ax
2709   -- mov al, [si+bx]
2710   -- mov dl, al
2711   -- mov bx, [bp]
2712   -- call pcibios_init_sel_reg
2713   -- mov dx, #0x0cfc
2714   -- and al, #0x03
2715   -- add dl, al
2716   -- in al, dx
2717   -- cmp al, #0x80
2718   -- jb pirq_found
2719   -- mov bx, [bp-2] ;; pci irq list pointer
2720   -- mov al, [bx]
2721   -- out dx, al
2722   -- inc bx
2723   -- mov [bp-2], bx
2724   -- call pcibios_init_set_elcr
2725   --pirq_found:
2726   -- mov bh, [si]
2727   -- mov bl, [si+1]
2728   -- add bl, [bp-3] ;; pci function number
2729   -- mov dl, #0x3c
2730   -- call pcibios_init_sel_reg
2731   -- mov dx, #0x0cfc
2732   -- out dx, al
2733   --next_pci_func:
2734   -- inc byte ptr[bp-3]
2735   -- inc bl
2736   -- test bl, #0x07
2737   -- jnz pci_init_irq_loop2
2738   --next_pir_entry:
2739   -- add si, #0x10
2740   -- mov byte ptr[bp-3], #0x00
2741   -- loop pci_init_irq_loop1
2742   -- mov sp, bp
2743   -- pop bx
2744   --pci_init_end:
2745   -- pop bp
2746   -- pop ds
2747   -+ SEG CS
2748   -+ lidt [pmode_IDT_info]
2749   -+ SEG CS
2750   -+ lgdt [rombios32_gdt_48]
2751   -+ ;; set PE bit in CR0
2752   -+ mov eax, cr0
2753   -+ or al, #0x01
2754   -+ mov cr0, eax
2755   -+ ;; start protected mode code: ljmpl 0x10:rombios32_init1
2756   -+ db 0x66, 0xea
2757   -+ dw rombios32_05
2758   -+ dw 0x000f ;; high 16 bit address
2759   -+ dw 0x0010
2760   -+
2761   -+use32 386
2762   -+rombios32_05:
2763   -+ ;; init data segments
2764   -+ mov eax, #0x18
2765   -+ mov ds, ax
2766   -+ mov es, ax
2767   -+ mov ss, ax
2768   -+ xor eax, eax
2769   -+ mov fs, ax
2770   -+ mov gs, ax
2771   -+ cld
2772   -+
2773   -+ ;; copy rombios32 code to ram (ram offset = 1MB)
2774   -+ mov esi, #0xfffe0000
2775   -+ mov edi, #0x00040000
2776   -+ mov ecx, #0x10000 / 4
2777   -+ rep
2778   -+ movsd
2779   -+
2780   -+ ;; init the stack pointer
2781   -+ mov esp, #0x00080000
2782   -+
2783   -+ ;; call rombios32 code
2784   -+ mov eax, #0x00040000
2785   -+ call eax
2786   -+
2787   -+ ;; return to 16 bit protected mode first
2788   -+ db 0xea
2789   -+ dd rombios32_10
2790   -+ dw 0x20
2791   -+
2792   -+use16 386
2793   -+rombios32_10:
2794   -+ ;; restore data segment limits to 0xffff
2795   -+ mov ax, #0x28
2796   -+ mov ds, ax
2797   -+ mov es, ax
2798   -+ mov ss, ax
2799   -+ mov fs, ax
2800   -+ mov gs, ax
2801   -+
2802   -+ ;; reset PE bit in CR0
2803   -+ mov eax, cr0
2804   -+ and al, #0xFE
2805   -+ mov cr0, eax
2806   -+
2807   -+ ;; far jump to flush CPU queue after transition to real mode
2808   -+ JMP_AP(0xf000, rombios32_real_mode)
2809   -+
2810   -+rombios32_real_mode:
2811   -+ ;; restore IDT to normal real-mode defaults
2812   -+ SEG CS
2813   -+ lidt [rmode_IDT_info]
2814   -+
2815   -+ xor ax, ax
2816   -+ mov ds, ax
2817   -+ mov es, ax
2818   -+ mov fs, ax
2819   -+ mov gs, ax
2820   -+
2821   -+ ;; restore SS:SP from the BDA
2822   -+ mov ss, 0x0469
2823   -+ mov sp, 0x0467
2824   -+ ;; restore a20
2825   -+ pop ax
2826   -+ out 0x92, al
2827   - ret
2828   --#endif // BX_PCIBIOS
2829   -+
2830   -+rombios32_gdt_48:
2831   -+ dw 0x30
2832   -+ dw rombios32_gdt
2833   -+ dw 0x000f
2834   -+
2835   -+rombios32_gdt:
2836   -+ dw 0, 0, 0, 0
2837   -+ dw 0, 0, 0, 0
2838   -+ dw 0xffff, 0, 0x9b00, 0x00cf ; 32 bit flat code segment (0x10)
2839   -+ dw 0xffff, 0, 0x9300, 0x00cf ; 32 bit flat data segment (0x18)
2840   -+ dw 0xffff, 0, 0x9b0f, 0x0000 ; 16 bit code segment base=0xf0000 limit=0xffff
2841   -+ dw 0xffff, 0, 0x9300, 0x0000 ; 16 bit data segment base=0x0 limit=0xffff
2842   -+#endif
2843   -+
2844   -
2845   - ; parallel port detection: base address in DX, index in BX, timeout in CL
2846   - detect_parport:
2847   -@@ -9535,10 +9454,17 @@
2848   - ;; DATA_SEG_DEFS_HERE
2849   -
2850   -
2851   -+;; the following area can be used to write dynamically generated tables
2852   -+ .align 16
2853   -+bios_table_area_start:
2854   -+ dd 0xaafb4442
2855   -+ dd bios_table_area_end - bios_table_area_start - 8;
2856   -+
2857   - ;--------
2858   - ;- POST -
2859   - ;--------
2860   - .org 0xe05b ; POST Entry Point
2861   -+bios_table_area_end:
2862   - post:
2863   -
2864   - xor ax, ax
2865   -@@ -9802,9 +9728,9 @@
2866   - #endif
2867   - out 0xa1, AL ;slave pic: unmask IRQ 12, 13, 14
2868   -
2869   -- call pcibios_init_iomem_bases
2870   -- call pcibios_init_irqs
  190 +-#define CPU_COUNT 0xf000
2871 191 -
2872   -+#if BX_ROMBIOS32
2873   -+ call rombios32_init
2874   -+#endif
2875   - call rom_scan
2876   -
2877   - call _print_bios_banner
  192 + .code16
  193 + smp_ap_boot_code_start:
  194 + xor %ax, %ax
  195 + mov %ax, %ds
  196 +- incw CPU_COUNT
  197 ++ incw CPU_COUNT_ADDR
  198 + 1:
  199 + hlt
  200 + jmp 1b
  201 +@@ -33,7 +51,7 @@
  202 + /* code to relocate SMBASE to 0xa0000 */
  203 + smm_relocation_start:
  204 + mov $0x38000 + 0x7efc, %ebx
  205 +- mov (%ebx), %al /* revision ID to see if x86_64 or x86 */
  206 ++ addr32 mov (%ebx), %al /* revision ID to see if x86_64 or x86 */
  207 + cmp $0x64, %al
  208 + je 1f
  209 + mov $0x38000 + 0x7ef8, %ebx
  210 +@@ -42,7 +60,7 @@
  211 + mov $0x38000 + 0x7f00, %ebx
  212 + 2:
  213 + movl $0xa0000, %eax
  214 +- movl %eax, (%ebx)
  215 ++ addr32 movl %eax, (%ebx)
  216 + rsm
  217 + smm_relocation_end:
  218 +
... ...