gwj / at91sam9263 · Commits

Commit a7859e892bed8b6cbc3c4b6908af6e8884f1f7bc

Authored by aurel32
1 parent 0c8aacd4

target-ppc: fix access_type usage 

Write env->access_type before a load/store operation instead of relying
on the name of the dyngen operation.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5785 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 38 additions and 36 deletions
target-ppc/translate.c
  View file @a7859e8
... ... @@ -67,6 +67,7 @@ static TCGv cpu_ctr;
67 67 static TCGv cpu_lr;
68 68 static TCGv cpu_xer;
69 69 static TCGv_i32 cpu_fpscr;
  70 +static TCGv_i32 cpu_access_type;
70 71  
71 72 /* dyngen register indexes */
72 73 static TCGv cpu_T[3];
... ... @@ -186,6 +187,9 @@ void ppc_translate_init(void)
186 187 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
187 188 offsetof(CPUState, fpscr), "fpscr");
188 189  
  190 + cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
  191 + offsetof(CPUState, access_type), "access_type");
  192 +
189 193 /* register helpers */
190 194 #define GEN_HELPER 2
191 195 #include "helper.h"
... ... @@ -281,6 +285,11 @@ static always_inline void gen_optimize_fprf (void)
281 285 #endif
282 286 }
283 287  
  288 +static always_inline void gen_set_access_type(int access_type)
  289 +{
  290 + tcg_gen_movi_i32(cpu_access_type, access_type);
  291 +}
  292 +
284 293 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
285 294 {
286 295 #if defined(TARGET_PPC64)
... ... @@ -2780,6 +2789,7 @@ static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2780 2789 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2781 2790 { \
2782 2791 TCGv EA = tcg_temp_new(); \
  2792 + gen_set_access_type(ACCESS_INT); \
2783 2793 gen_addr_imm_index(EA, ctx, 0); \
2784 2794 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2785 2795 tcg_temp_free(EA); \
... ... @@ -2795,6 +2805,7 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2795 2805 return; \
2796 2806 } \
2797 2807 EA = tcg_temp_new(); \
  2808 + gen_set_access_type(ACCESS_INT); \
2798 2809 if (type == PPC_64B) \
2799 2810 gen_addr_imm_index(EA, ctx, 0x03); \
2800 2811 else \
... ... @@ -2814,6 +2825,7 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2814 2825 return; \
2815 2826 } \
2816 2827 EA = tcg_temp_new(); \
  2828 + gen_set_access_type(ACCESS_INT); \
2817 2829 gen_addr_reg_index(EA, ctx); \
2818 2830 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2819 2831 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
... ... @@ -2824,6 +2836,7 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2824 2836 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2825 2837 { \
2826 2838 TCGv EA = tcg_temp_new(); \
  2839 + gen_set_access_type(ACCESS_INT); \
2827 2840 gen_addr_reg_index(EA, ctx); \
2828 2841 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2829 2842 tcg_temp_free(EA); \
... ... @@ -2863,6 +2876,7 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2863 2876 }
2864 2877 }
2865 2878 EA = tcg_temp_new();
  2879 + gen_set_access_type(ACCESS_INT);
2866 2880 gen_addr_imm_index(EA, ctx, 0x03);
2867 2881 if (ctx->opcode & 0x02) {
2868 2882 /* lwa (lwau is undefined) */
... ... @@ -2901,6 +2915,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2901 2915 return;
2902 2916 }
2903 2917 EA = tcg_temp_new();
  2918 + gen_set_access_type(ACCESS_INT);
2904 2919 gen_addr_imm_index(EA, ctx, 0x0F);
2905 2920 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2906 2921 tcg_gen_addi_tl(EA, EA, 8);
... ... @@ -2915,6 +2930,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2915 2930 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2916 2931 { \
2917 2932 TCGv EA = tcg_temp_new(); \
  2933 + gen_set_access_type(ACCESS_INT); \
2918 2934 gen_addr_imm_index(EA, ctx, 0); \
2919 2935 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2920 2936 tcg_temp_free(EA); \
... ... @@ -2929,6 +2945,7 @@ GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2929 2945 return; \
2930 2946 } \
2931 2947 EA = tcg_temp_new(); \
  2948 + gen_set_access_type(ACCESS_INT); \
2932 2949 if (type == PPC_64B) \
2933 2950 gen_addr_imm_index(EA, ctx, 0x03); \
2934 2951 else \
... ... @@ -2947,6 +2964,7 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2947 2964 return; \
2948 2965 } \
2949 2966 EA = tcg_temp_new(); \
  2967 + gen_set_access_type(ACCESS_INT); \
2950 2968 gen_addr_reg_index(EA, ctx); \
2951 2969 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2952 2970 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
... ... @@ -2957,6 +2975,7 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2957 2975 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2958 2976 { \
2959 2977 TCGv EA = tcg_temp_new(); \
  2978 + gen_set_access_type(ACCESS_INT); \
2960 2979 gen_addr_reg_index(EA, ctx); \
2961 2980 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2962 2981 tcg_temp_free(EA); \
... ... @@ -3002,6 +3021,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
3002 3021 return;
3003 3022 }
3004 3023 EA = tcg_temp_new();
  3024 + gen_set_access_type(ACCESS_INT);
3005 3025 gen_addr_imm_index(EA, ctx, 0x03);
3006 3026 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3007 3027 tcg_gen_addi_tl(EA, EA, 8);
... ... @@ -3017,6 +3037,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
3017 3037 }
3018 3038 }
3019 3039 EA = tcg_temp_new();
  3040 + gen_set_access_type(ACCESS_INT);
3020 3041 gen_addr_imm_index(EA, ctx, 0x03);
3021 3042 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3022 3043 if (Rc(ctx->opcode))
... ... @@ -3240,6 +3261,7 @@ GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3240 3261 {
3241 3262 /* NIP cannot be restored if the memory exception comes from an helper */
3242 3263 gen_update_nip(ctx, ctx->nip - 4);
  3264 + gen_set_access_type(ACCESS_RES);
3243 3265 gen_addr_reg_index(cpu_T[0], ctx);
3244 3266 op_lwarx();
3245 3267 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
... ... @@ -3250,6 +3272,7 @@ GEN_HANDLER2(stwcx_, &quot;stwcx.&quot;, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3250 3272 {
3251 3273 /* NIP cannot be restored if the memory exception comes from an helper */
3252 3274 gen_update_nip(ctx, ctx->nip - 4);
  3275 + gen_set_access_type(ACCESS_RES);
3253 3276 gen_addr_reg_index(cpu_T[0], ctx);
3254 3277 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
3255 3278 op_stwcx();
... ... @@ -3270,6 +3293,7 @@ GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3270 3293 {
3271 3294 /* NIP cannot be restored if the memory exception comes from an helper */
3272 3295 gen_update_nip(ctx, ctx->nip - 4);
  3296 + gen_set_access_type(ACCESS_RES);
3273 3297 gen_addr_reg_index(cpu_T[0], ctx);
3274 3298 op_ldarx();
3275 3299 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
... ... @@ -3280,6 +3304,7 @@ GEN_HANDLER2(stdcx_, &quot;stdcx.&quot;, 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3280 3304 {
3281 3305 /* NIP cannot be restored if the memory exception comes from an helper */
3282 3306 gen_update_nip(ctx, ctx->nip - 4);
  3307 + gen_set_access_type(ACCESS_RES);
3283 3308 gen_addr_reg_index(cpu_T[0], ctx);
3284 3309 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
3285 3310 op_stdcx();
... ... @@ -3307,6 +3332,7 @@ GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
3307 3332 GEN_EXCP_NO_FP(ctx); \
3308 3333 return; \
3309 3334 } \
  3335 + gen_set_access_type(ACCESS_FLOAT); \
3310 3336 gen_addr_imm_index(cpu_T[0], ctx, 0); \
3311 3337 op_ldst(l##width); \
3312 3338 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
... ... @@ -3323,6 +3349,7 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3323 3349 GEN_EXCP_INVAL(ctx); \
3324 3350 return; \
3325 3351 } \
  3352 + gen_set_access_type(ACCESS_FLOAT); \
3326 3353 gen_addr_imm_index(cpu_T[0], ctx, 0); \
3327 3354 op_ldst(l##width); \
3328 3355 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
... ... @@ -3340,6 +3367,7 @@ GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3340 3367 GEN_EXCP_INVAL(ctx); \
3341 3368 return; \
3342 3369 } \
  3370 + gen_set_access_type(ACCESS_FLOAT); \
3343 3371 gen_addr_reg_index(cpu_T[0], ctx); \
3344 3372 op_ldst(l##width); \
3345 3373 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
... ... @@ -3353,6 +3381,7 @@ GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
3353 3381 GEN_EXCP_NO_FP(ctx); \
3354 3382 return; \
3355 3383 } \
  3384 + gen_set_access_type(ACCESS_FLOAT); \
3356 3385 gen_addr_reg_index(cpu_T[0], ctx); \
3357 3386 op_ldst(l##width); \
3358 3387 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
... ... @@ -3378,6 +3407,7 @@ GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
3378 3407 GEN_EXCP_NO_FP(ctx); \
3379 3408 return; \
3380 3409 } \
  3410 + gen_set_access_type(ACCESS_FLOAT); \
3381 3411 gen_addr_imm_index(cpu_T[0], ctx, 0); \
3382 3412 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
3383 3413 op_ldst(st##width); \
... ... @@ -3394,6 +3424,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3394 3424 GEN_EXCP_INVAL(ctx); \
3395 3425 return; \
3396 3426 } \
  3427 + gen_set_access_type(ACCESS_FLOAT); \
3397 3428 gen_addr_imm_index(cpu_T[0], ctx, 0); \
3398 3429 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
3399 3430 op_ldst(st##width); \
... ... @@ -3411,6 +3442,7 @@ GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3411 3442 GEN_EXCP_INVAL(ctx); \
3412 3443 return; \
3413 3444 } \
  3445 + gen_set_access_type(ACCESS_FLOAT); \
3414 3446 gen_addr_reg_index(cpu_T[0], ctx); \
3415 3447 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
3416 3448 op_ldst(st##width); \
... ... @@ -3424,6 +3456,7 @@ GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
3424 3456 GEN_EXCP_NO_FP(ctx); \
3425 3457 return; \
3426 3458 } \
  3459 + gen_set_access_type(ACCESS_FLOAT); \
3427 3460 gen_addr_reg_index(cpu_T[0], ctx); \
3428 3461 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
3429 3462 op_ldst(st##width); \
... ... @@ -4011,6 +4044,7 @@ GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4011 4044 {
4012 4045 /* XXX: specification says this is treated as a load by the MMU */
4013 4046 TCGv t0 = tcg_temp_new();
  4047 + gen_set_access_type(ACCESS_CACHE);
4014 4048 gen_addr_reg_index(t0, ctx);
4015 4049 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4016 4050 tcg_temp_free(t0);
... ... @@ -4028,6 +4062,7 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4028 4062 return;
4029 4063 }
4030 4064 EA = tcg_temp_new();
  4065 + gen_set_access_type(ACCESS_CACHE);
4031 4066 gen_addr_reg_index(EA, ctx);
4032 4067 val = tcg_temp_new();
4033 4068 /* XXX: specification says this should be treated as a store by the MMU */
... ... @@ -4043,6 +4078,7 @@ GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4043 4078 {
4044 4079 /* XXX: specification say this is treated as a load by the MMU */
4045 4080 TCGv t0 = tcg_temp_new();
  4081 + gen_set_access_type(ACCESS_CACHE);
4046 4082 gen_addr_reg_index(t0, ctx);
4047 4083 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4048 4084 tcg_temp_free(t0);
... ... @@ -4428,6 +4464,7 @@ static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4428 4464 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4429 4465 {
4430 4466 /* Should check EAR[E] & alignment ! */
  4467 + gen_set_access_type(ACCESS_RES);
4431 4468 gen_addr_reg_index(cpu_T[0], ctx);
4432 4469 op_eciwx();
4433 4470 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
... ... @@ -5512,6 +5549,7 @@ GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5512 5549 return;
5513 5550 }
5514 5551 EA = tcg_temp_new();
  5552 + gen_set_access_type(ACCESS_CACHE);
5515 5553 gen_addr_reg_index(EA, ctx);
5516 5554 val = tcg_temp_new();
5517 5555 gen_qemu_ld32u(val, EA, ctx->mem_idx);
... ... @@ -7630,41 +7668,5 @@ void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
7630 7668 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7631 7669 unsigned long searched_pc, int pc_pos, void *puc)
7632 7670 {
7633   - int type, c;
7634   - /* for PPC, we need to look at the micro operation to get the
7635   - * access type */
7636 7671 env->nip = gen_opc_pc[pc_pos];
7637   - c = gen_opc_buf[pc_pos];
7638   - switch(c) {
7639   -#if defined(CONFIG_USER_ONLY)
7640   -#define CASE3(op)\
7641   - case INDEX_op_ ## op ## _raw
7642   -#else
7643   -#define CASE3(op)\
7644   - case INDEX_op_ ## op ## _user:\
7645   - case INDEX_op_ ## op ## _kernel:\
7646   - case INDEX_op_ ## op ## _hypv
7647   -#endif
7648   -
7649   - CASE3(stfd):
7650   - CASE3(stfs):
7651   - CASE3(lfd):
7652   - CASE3(lfs):
7653   - type = ACCESS_FLOAT;
7654   - break;
7655   - CASE3(lwarx):
7656   - type = ACCESS_RES;
7657   - break;
7658   - CASE3(stwcx):
7659   - type = ACCESS_RES;
7660   - break;
7661   - CASE3(eciwx):
7662   - CASE3(ecowx):
7663   - type = ACCESS_EXT;
7664   - break;
7665   - default:
7666   - type = ACCESS_INT;
7667   - break;
7668   - }
7669   - env->access_type = type;
7670 7672 }
... ...