Commit a7812ae412311d7d47f8aa85656faadac9d64b56
1 parent
30913bae
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
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cpu-exec.c
... | ... | @@ -345,7 +345,7 @@ int cpu_exec(CPUState *env1) |
345 | 345 | #ifdef USE_KQEMU |
346 | 346 | if (kqemu_is_ok(env) && env->interrupt_request == 0) { |
347 | 347 | int ret; |
348 | - env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
348 | + env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); | |
349 | 349 | ret = kqemu_cpu_exec(env); |
350 | 350 | /* put eflags in CPU temporary format */ |
351 | 351 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
... | ... | @@ -571,7 +571,7 @@ int cpu_exec(CPUState *env1) |
571 | 571 | /* restore flags in standard format */ |
572 | 572 | regs_to_env(); |
573 | 573 | #if defined(TARGET_I386) |
574 | - env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
574 | + env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); | |
575 | 575 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
576 | 576 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
577 | 577 | #elif defined(TARGET_ARM) |
... | ... | @@ -695,7 +695,7 @@ int cpu_exec(CPUState *env1) |
695 | 695 | |
696 | 696 | #if defined(TARGET_I386) |
697 | 697 | /* restore flags in standard format */ |
698 | - env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
698 | + env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); | |
699 | 699 | #elif defined(TARGET_ARM) |
700 | 700 | /* XXX: Save/restore host fpu exception state?. */ |
701 | 701 | #elif defined(TARGET_SPARC) | ... | ... |
def-helper.h
0 → 100644
1 | +/* Helper file for declaring TCG helper functions. | |
2 | + Should be included at the start and end of target-foo/helper.h. | |
3 | + | |
4 | + Targets should use DEF_HELPER_N and DEF_HELPER_FLAGS_N to declare helper | |
5 | + functions. Names should be specified without the helper_ prefix, and | |
6 | + the return and argument types specified. 3 basic types are understood | |
7 | + (i32, i64 and ptr). Additional aliases are provided for convenience and | |
8 | + to match the types used by the C helper implementation. | |
9 | + | |
10 | + The target helper.h should be included in all files that use/define | |
11 | + helper functions. THis will ensure that function prototypes are | |
12 | + consistent. In addition it should be included an extra two times for | |
13 | + helper.c, defining: | |
14 | + GEN_HELPER 1 to produce op generation functions (gen_helper_*) | |
15 | + GEN_HELPER 2 to do runtime registration helper functions. | |
16 | + */ | |
17 | + | |
18 | +#ifndef DEF_HELPER_H | |
19 | +#define DEF_HELPER_H 1 | |
20 | + | |
21 | +#define HELPER(name) glue(helper_, name) | |
22 | + | |
23 | +#define GET_TCGV_i32 GET_TCGV_I32 | |
24 | +#define GET_TCGV_i64 GET_TCGV_I64 | |
25 | +#define GET_TCGV_ptr GET_TCGV_PTR | |
26 | + | |
27 | +/* Some types that make sense in C, but not for TCG. */ | |
28 | +#define dh_alias_i32 i32 | |
29 | +#define dh_alias_s32 i32 | |
30 | +#define dh_alias_int i32 | |
31 | +#define dh_alias_i64 i64 | |
32 | +#define dh_alias_s64 i64 | |
33 | +#define dh_alias_f32 i32 | |
34 | +#define dh_alias_f64 i64 | |
35 | +#if TARGET_LONG_BITS == 32 | |
36 | +#define dh_alias_tl i32 | |
37 | +#else | |
38 | +#define dh_alias_tl i64 | |
39 | +#endif | |
40 | +#define dh_alias_ptr ptr | |
41 | +#define dh_alias_void void | |
42 | +#define dh_alias_env ptr | |
43 | +#define dh_alias(t) glue(dh_alias_, t) | |
44 | + | |
45 | +#define dh_ctype_i32 uint32_t | |
46 | +#define dh_ctype_s32 int32_t | |
47 | +#define dh_ctype_int int | |
48 | +#define dh_ctype_i64 uint64_t | |
49 | +#define dh_ctype_s64 int64_t | |
50 | +#define dh_ctype_f32 float32 | |
51 | +#define dh_ctype_f64 float64 | |
52 | +#define dh_ctype_tl target_ulong | |
53 | +#define dh_ctype_ptr void * | |
54 | +#define dh_ctype_void void | |
55 | +#define dh_ctype_env CPUState * | |
56 | +#define dh_ctype(t) dh_ctype_##t | |
57 | + | |
58 | +/* We can't use glue() here because it falls foul of C preprocessor | |
59 | + recursive expansion rules. */ | |
60 | +#define dh_retvar_decl0_void void | |
61 | +#define dh_retvar_decl0_i32 TCGv_i32 retval | |
62 | +#define dh_retvar_decl0_i64 TCGv_i64 retval | |
63 | +#define dh_retvar_decl0_ptr TCGv_iptr retval | |
64 | +#define dh_retvar_decl0(t) glue(dh_retvar_decl0_, dh_alias(t)) | |
65 | + | |
66 | +#define dh_retvar_decl_void | |
67 | +#define dh_retvar_decl_i32 TCGv_i32 retval, | |
68 | +#define dh_retvar_decl_i64 TCGv_i64 retval, | |
69 | +#define dh_retvar_decl_ptr TCGv_iptr retval, | |
70 | +#define dh_retvar_decl(t) glue(dh_retvar_decl_, dh_alias(t)) | |
71 | + | |
72 | +#define dh_retvar_void TCG_CALL_DUMMY_ARG | |
73 | +#define dh_retvar_i32 GET_TCGV_i32(retval) | |
74 | +#define dh_retvar_i64 GET_TCGV_i64(retval) | |
75 | +#define dh_retvar_ptr GET_TCGV_ptr(retval) | |
76 | +#define dh_retvar(t) glue(dh_retvar_, dh_alias(t)) | |
77 | + | |
78 | +#define dh_is_64bit_void 0 | |
79 | +#define dh_is_64bit_i32 0 | |
80 | +#define dh_is_64bit_i64 1 | |
81 | +#define dh_is_64bit_ptr (TCG_TARGET_REG_BITS == 64) | |
82 | +#define dh_is_64bit(t) glue(dh_is_64bit_, dh_alias(t)) | |
83 | + | |
84 | +#define dh_arg(t, n) \ | |
85 | + args[n - 1] = glue(GET_TCGV_, dh_alias(t))(glue(arg, n)); \ | |
86 | + sizemask |= dh_is_64bit(t) << n | |
87 | + | |
88 | +#define dh_arg_decl(t, n) glue(TCGv_, dh_alias(t)) glue(arg, n) | |
89 | + | |
90 | + | |
91 | +#define DEF_HELPER_0(name, ret) \ | |
92 | + DEF_HELPER_FLAGS_0(name, 0, ret) | |
93 | +#define DEF_HELPER_1(name, ret, t1) \ | |
94 | + DEF_HELPER_FLAGS_1(name, 0, ret, t1) | |
95 | +#define DEF_HELPER_2(name, ret, t1, t2) \ | |
96 | + DEF_HELPER_FLAGS_2(name, 0, ret, t1, t2) | |
97 | +#define DEF_HELPER_3(name, ret, t1, t2, t3) \ | |
98 | + DEF_HELPER_FLAGS_3(name, 0, ret, t1, t2, t3) | |
99 | +#define DEF_HELPER_4(name, ret, t1, t2, t3, t4) \ | |
100 | + DEF_HELPER_FLAGS_4(name, 0, ret, t1, t2, t3, t4) | |
101 | + | |
102 | +#endif /* DEF_HELPER_H */ | |
103 | + | |
104 | +#ifndef GEN_HELPER | |
105 | +/* Function prototypes. */ | |
106 | + | |
107 | +#define DEF_HELPER_FLAGS_0(name, flags, ret) \ | |
108 | +dh_ctype(ret) HELPER(name) (void); | |
109 | + | |
110 | +#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ | |
111 | +dh_ctype(ret) HELPER(name) (dh_ctype(t1)); | |
112 | + | |
113 | +#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ | |
114 | +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2)); | |
115 | + | |
116 | +#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ | |
117 | +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3)); | |
118 | + | |
119 | +#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ | |
120 | +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ | |
121 | + dh_ctype(t4)); | |
122 | + | |
123 | +#undef GEN_HELPER | |
124 | +#define GEN_HELPER -1 | |
125 | + | |
126 | +#elif GEN_HELPER == 1 | |
127 | +/* Gen functions. */ | |
128 | + | |
129 | +#define DEF_HELPER_FLAGS_0(name, flags, ret) \ | |
130 | +static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ | |
131 | +{ \ | |
132 | + int sizemask; \ | |
133 | + sizemask = dh_is_64bit(ret); \ | |
134 | + tcg_gen_helperN(HELPER(name), flags, sizemask, dh_retvar(ret), 0, NULL); \ | |
135 | +} | |
136 | + | |
137 | +#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ | |
138 | +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) dh_arg_decl(t1, 1)) \ | |
139 | +{ \ | |
140 | + TCGArg args[1]; \ | |
141 | + int sizemask; \ | |
142 | + sizemask = dh_is_64bit(ret); \ | |
143 | + dh_arg(t1, 1); \ | |
144 | + tcg_gen_helperN(HELPER(name), flags, sizemask, dh_retvar(ret), 1, args); \ | |
145 | +} | |
146 | + | |
147 | +#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ | |
148 | +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) dh_arg_decl(t1, 1), \ | |
149 | + dh_arg_decl(t2, 2)) \ | |
150 | +{ \ | |
151 | + TCGArg args[2]; \ | |
152 | + int sizemask; \ | |
153 | + sizemask = dh_is_64bit(ret); \ | |
154 | + dh_arg(t1, 1); \ | |
155 | + dh_arg(t2, 2); \ | |
156 | + tcg_gen_helperN(HELPER(name), flags, sizemask, dh_retvar(ret), 2, args); \ | |
157 | +} | |
158 | + | |
159 | +#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ | |
160 | +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) dh_arg_decl(t1, 1), \ | |
161 | + dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ | |
162 | +{ \ | |
163 | + TCGArg args[3]; \ | |
164 | + int sizemask; \ | |
165 | + sizemask = dh_is_64bit(ret); \ | |
166 | + dh_arg(t1, 1); \ | |
167 | + dh_arg(t2, 2); \ | |
168 | + dh_arg(t3, 3); \ | |
169 | + tcg_gen_helperN(HELPER(name), flags, sizemask, dh_retvar(ret), 3, args); \ | |
170 | +} | |
171 | + | |
172 | +#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ | |
173 | +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) dh_arg_decl(t1, 1), \ | |
174 | + dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \ | |
175 | +{ \ | |
176 | + TCGArg args[4]; \ | |
177 | + int sizemask; \ | |
178 | + sizemask = dh_is_64bit(ret); \ | |
179 | + dh_arg(t1, 1); \ | |
180 | + dh_arg(t2, 2); \ | |
181 | + dh_arg(t3, 3); \ | |
182 | + dh_arg(t4, 4); \ | |
183 | + tcg_gen_helperN(HELPER(name), flags, sizemask, dh_retvar(ret), 4, args); \ | |
184 | +} | |
185 | + | |
186 | +#undef GEN_HELPER | |
187 | +#define GEN_HELPER -1 | |
188 | + | |
189 | +#elif GEN_HELPER == 2 | |
190 | +/* Register helpers. */ | |
191 | + | |
192 | +#define DEF_HELPER_FLAGS_0(name, flags, ret) \ | |
193 | +tcg_register_helper(HELPER(name), #name); | |
194 | + | |
195 | +#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ | |
196 | +DEF_HELPER_FLAGS_0(name, flags, ret) | |
197 | + | |
198 | +#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ | |
199 | +DEF_HELPER_FLAGS_0(name, flags, ret) | |
200 | + | |
201 | +#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ | |
202 | +DEF_HELPER_FLAGS_0(name, flags, ret) | |
203 | + | |
204 | +#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ | |
205 | +DEF_HELPER_FLAGS_0(name, flags, ret) | |
206 | + | |
207 | +#undef GEN_HELPER | |
208 | +#define GEN_HELPER -1 | |
209 | + | |
210 | +#elif GEN_HELPER == -1 | |
211 | +/* Undefine macros. */ | |
212 | + | |
213 | +#undef DEF_HELPER_FLAGS_0 | |
214 | +#undef DEF_HELPER_FLAGS_1 | |
215 | +#undef DEF_HELPER_FLAGS_2 | |
216 | +#undef DEF_HELPER_FLAGS_3 | |
217 | +#undef DEF_HELPER_FLAGS_4 | |
218 | +#undef GEN_HELPER | |
219 | + | |
220 | +#endif | |
221 | + | ... | ... |
gen-icount.h
... | ... | @@ -5,7 +5,7 @@ static int icount_label; |
5 | 5 | |
6 | 6 | static inline void gen_icount_start(void) |
7 | 7 | { |
8 | - TCGv count; | |
8 | + TCGv_i32 count; | |
9 | 9 | |
10 | 10 | if (!use_icount) |
11 | 11 | return; |
... | ... | @@ -15,7 +15,7 @@ static inline void gen_icount_start(void) |
15 | 15 | count needs to live over the conditional branch. To workaround this |
16 | 16 | we allow the target to supply a convenient register temporary. */ |
17 | 17 | #ifndef ICOUNT_TEMP |
18 | - count = tcg_temp_local_new(TCG_TYPE_I32); | |
18 | + count = tcg_temp_local_new_i32(); | |
19 | 19 | #else |
20 | 20 | count = ICOUNT_TEMP; |
21 | 21 | #endif |
... | ... | @@ -27,7 +27,7 @@ static inline void gen_icount_start(void) |
27 | 27 | tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, icount_label); |
28 | 28 | tcg_gen_st16_i32(count, cpu_env, offsetof(CPUState, icount_decr.u16.low)); |
29 | 29 | #ifndef ICOUNT_TEMP |
30 | - tcg_temp_free(count); | |
30 | + tcg_temp_free_i32(count); | |
31 | 31 | #endif |
32 | 32 | } |
33 | 33 | |
... | ... | @@ -42,15 +42,15 @@ static void gen_icount_end(TranslationBlock *tb, int num_insns) |
42 | 42 | |
43 | 43 | static void inline gen_io_start(void) |
44 | 44 | { |
45 | - TCGv tmp = tcg_const_i32(1); | |
45 | + TCGv_i32 tmp = tcg_const_i32(1); | |
46 | 46 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io)); |
47 | - tcg_temp_free(tmp); | |
47 | + tcg_temp_free_i32(tmp); | |
48 | 48 | } |
49 | 49 | |
50 | 50 | static inline void gen_io_end(void) |
51 | 51 | { |
52 | - TCGv tmp = tcg_const_i32(0); | |
52 | + TCGv_i32 tmp = tcg_const_i32(0); | |
53 | 53 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io)); |
54 | - tcg_temp_free(tmp); | |
54 | + tcg_temp_free_i32(tmp); | |
55 | 55 | } |
56 | 56 | ... | ... |
target-alpha/helper.h
1 | -#ifndef DEF_HELPER | |
2 | -#define DEF_HELPER(ret, name, params) ret name params; | |
3 | -#endif | |
4 | - | |
5 | -DEF_HELPER(void, helper_tb_flush, (void)) | |
6 | - | |
7 | -DEF_HELPER(void, helper_excp, (int, int)) | |
8 | -DEF_HELPER(uint64_t, helper_amask, (uint64_t)) | |
9 | -DEF_HELPER(uint64_t, helper_load_pcc, (void)) | |
10 | -DEF_HELPER(uint64_t, helper_load_implver, (void)) | |
11 | -DEF_HELPER(uint64_t, helper_rc, (void)) | |
12 | -DEF_HELPER(uint64_t, helper_rs, (void)) | |
13 | - | |
14 | -DEF_HELPER(uint64_t, helper_addqv, (uint64_t, uint64_t)) | |
15 | -DEF_HELPER(uint64_t, helper_addlv, (uint64_t, uint64_t)) | |
16 | -DEF_HELPER(uint64_t, helper_subqv, (uint64_t, uint64_t)) | |
17 | -DEF_HELPER(uint64_t, helper_sublv, (uint64_t, uint64_t)) | |
18 | -DEF_HELPER(uint64_t, helper_mullv, (uint64_t, uint64_t)) | |
19 | -DEF_HELPER(uint64_t, helper_mulqv, (uint64_t, uint64_t)) | |
20 | -DEF_HELPER(uint64_t, helper_umulh, (uint64_t, uint64_t)) | |
21 | - | |
22 | -DEF_HELPER(uint64_t, helper_ctpop, (uint64_t)) | |
23 | -DEF_HELPER(uint64_t, helper_ctlz, (uint64_t)) | |
24 | -DEF_HELPER(uint64_t, helper_cttz, (uint64_t)) | |
25 | - | |
26 | -DEF_HELPER(uint64_t, helper_mskbl, (int64_t, uint64_t)) | |
27 | -DEF_HELPER(uint64_t, helper_insbl, (int64_t, uint64_t)) | |
28 | -DEF_HELPER(uint64_t, helper_mskwl, (int64_t, uint64_t)) | |
29 | -DEF_HELPER(uint64_t, helper_inswl, (int64_t, uint64_t)) | |
30 | -DEF_HELPER(uint64_t, helper_mskll, (int64_t, uint64_t)) | |
31 | -DEF_HELPER(uint64_t, helper_insll, (int64_t, uint64_t)) | |
32 | -DEF_HELPER(uint64_t, helper_zap, (int64_t, uint64_t)) | |
33 | -DEF_HELPER(uint64_t, helper_zapnot, (int64_t, uint64_t)) | |
34 | -DEF_HELPER(uint64_t, helper_mskql, (int64_t, uint64_t)) | |
35 | -DEF_HELPER(uint64_t, helper_insql, (int64_t, uint64_t)) | |
36 | -DEF_HELPER(uint64_t, helper_mskwh, (int64_t, uint64_t)) | |
37 | -DEF_HELPER(uint64_t, helper_inswh, (int64_t, uint64_t)) | |
38 | -DEF_HELPER(uint64_t, helper_msklh, (int64_t, uint64_t)) | |
39 | -DEF_HELPER(uint64_t, helper_inslh, (int64_t, uint64_t)) | |
40 | -DEF_HELPER(uint64_t, helper_mskqh, (int64_t, uint64_t)) | |
41 | -DEF_HELPER(uint64_t, helper_insqh, (int64_t, uint64_t)) | |
42 | - | |
43 | -DEF_HELPER(uint64_t, helper_cmpbge, (uint64_t, uint64_t)) | |
44 | - | |
45 | -DEF_HELPER(uint64_t, helper_load_fpcr, (void)) | |
46 | -DEF_HELPER(void, helper_store_fpcr, (uint64_t val)) | |
47 | - | |
48 | -DEF_HELPER(uint32_t, helper_f_to_memory, (uint64_t s)) | |
49 | -DEF_HELPER(uint64_t, helper_memory_to_f, (uint32_t s)) | |
50 | -DEF_HELPER(uint64_t, helper_addf, (uint64_t, uint64_t)) | |
51 | -DEF_HELPER(uint64_t, helper_subf, (uint64_t, uint64_t)) | |
52 | -DEF_HELPER(uint64_t, helper_mulf, (uint64_t, uint64_t)) | |
53 | -DEF_HELPER(uint64_t, helper_divf, (uint64_t, uint64_t)) | |
54 | -DEF_HELPER(uint64_t, helper_sqrtf, (uint64_t)) | |
55 | - | |
56 | -DEF_HELPER(uint64_t, helper_g_to_memory, (uint64_t s)) | |
57 | -DEF_HELPER(uint64_t, helper_memory_to_g, (uint64_t s)) | |
58 | -DEF_HELPER(uint64_t, helper_addg, (uint64_t, uint64_t)) | |
59 | -DEF_HELPER(uint64_t, helper_subg, (uint64_t, uint64_t)) | |
60 | -DEF_HELPER(uint64_t, helper_mulg, (uint64_t, uint64_t)) | |
61 | -DEF_HELPER(uint64_t, helper_divg, (uint64_t, uint64_t)) | |
62 | -DEF_HELPER(uint64_t, helper_sqrtg, (uint64_t)) | |
63 | - | |
64 | -DEF_HELPER(uint32_t, helper_s_to_memory, (uint64_t s)) | |
65 | -DEF_HELPER(uint64_t, helper_memory_to_s, (uint32_t s)) | |
66 | -DEF_HELPER(uint64_t, helper_adds, (uint64_t, uint64_t)) | |
67 | -DEF_HELPER(uint64_t, helper_subs, (uint64_t, uint64_t)) | |
68 | -DEF_HELPER(uint64_t, helper_muls, (uint64_t, uint64_t)) | |
69 | -DEF_HELPER(uint64_t, helper_divs, (uint64_t, uint64_t)) | |
70 | -DEF_HELPER(uint64_t, helper_sqrts, (uint64_t)) | |
71 | - | |
72 | -DEF_HELPER(uint64_t, helper_addt, (uint64_t, uint64_t)) | |
73 | -DEF_HELPER(uint64_t, helper_subt, (uint64_t, uint64_t)) | |
74 | -DEF_HELPER(uint64_t, helper_mult, (uint64_t, uint64_t)) | |
75 | -DEF_HELPER(uint64_t, helper_divt, (uint64_t, uint64_t)) | |
76 | -DEF_HELPER(uint64_t, helper_sqrtt, (uint64_t)) | |
77 | - | |
78 | -DEF_HELPER(uint64_t, helper_cmptun, (uint64_t, uint64_t)) | |
79 | -DEF_HELPER(uint64_t, helper_cmpteq, (uint64_t, uint64_t)) | |
80 | -DEF_HELPER(uint64_t, helper_cmptle, (uint64_t, uint64_t)) | |
81 | -DEF_HELPER(uint64_t, helper_cmptlt, (uint64_t, uint64_t)) | |
82 | -DEF_HELPER(uint64_t, helper_cmpgeq, (uint64_t, uint64_t)) | |
83 | -DEF_HELPER(uint64_t, helper_cmpgle, (uint64_t, uint64_t)) | |
84 | -DEF_HELPER(uint64_t, helper_cmpglt, (uint64_t, uint64_t)) | |
85 | - | |
86 | -DEF_HELPER(uint64_t, helper_cmpfeq, (uint64_t)) | |
87 | -DEF_HELPER(uint64_t, helper_cmpfne, (uint64_t)) | |
88 | -DEF_HELPER(uint64_t, helper_cmpflt, (uint64_t)) | |
89 | -DEF_HELPER(uint64_t, helper_cmpfle, (uint64_t)) | |
90 | -DEF_HELPER(uint64_t, helper_cmpfgt, (uint64_t)) | |
91 | -DEF_HELPER(uint64_t, helper_cmpfge, (uint64_t)) | |
92 | - | |
93 | -DEF_HELPER(uint64_t, helper_cpys, (uint64_t, uint64_t)) | |
94 | -DEF_HELPER(uint64_t, helper_cpysn, (uint64_t, uint64_t)) | |
95 | -DEF_HELPER(uint64_t, helper_cpyse, (uint64_t, uint64_t)) | |
96 | - | |
97 | -DEF_HELPER(uint64_t, helper_cvtts, (uint64_t)) | |
98 | -DEF_HELPER(uint64_t, helper_cvtst, (uint64_t)) | |
99 | -DEF_HELPER(uint64_t, helper_cvttq, (uint64_t)) | |
100 | -DEF_HELPER(uint32_t, helper_cvtqs, (uint64_t)) | |
101 | -DEF_HELPER(uint64_t, helper_cvtqt, (uint64_t)) | |
102 | -DEF_HELPER(uint64_t, helper_cvtqf, (uint64_t)) | |
103 | -DEF_HELPER(uint64_t, helper_cvtgf, (uint64_t)) | |
104 | -DEF_HELPER(uint64_t, helper_cvtgq, (uint64_t)) | |
105 | -DEF_HELPER(uint64_t, helper_cvtqg, (uint64_t)) | |
106 | -DEF_HELPER(uint64_t, helper_cvtlq, (uint64_t)) | |
107 | -DEF_HELPER(uint64_t, helper_cvtql, (uint64_t)) | |
108 | -DEF_HELPER(uint64_t, helper_cvtqlv, (uint64_t)) | |
109 | -DEF_HELPER(uint64_t, helper_cvtqlsv, (uint64_t)) | |
1 | +#include "def-helper.h" | |
2 | + | |
3 | +DEF_HELPER_0(tb_flush, void) | |
4 | + | |
5 | +DEF_HELPER_2(excp, void, int, int) | |
6 | +DEF_HELPER_1(amask, i64, i64) | |
7 | +DEF_HELPER_0(load_pcc, i64) | |
8 | +DEF_HELPER_0(load_implver, i64) | |
9 | +DEF_HELPER_0(rc, i64) | |
10 | +DEF_HELPER_0(rs, i64) | |
11 | + | |
12 | +DEF_HELPER_2(addqv, i64, i64, i64) | |
13 | +DEF_HELPER_2(addlv, i64, i64, i64) | |
14 | +DEF_HELPER_2(subqv, i64, i64, i64) | |
15 | +DEF_HELPER_2(sublv, i64, i64, i64) | |
16 | +DEF_HELPER_2(mullv, i64, i64, i64) | |
17 | +DEF_HELPER_2(mulqv, i64, i64, i64) | |
18 | +DEF_HELPER_2(umulh, i64, i64, i64) | |
19 | + | |
20 | +DEF_HELPER_1(ctpop, i64, i64) | |
21 | +DEF_HELPER_1(ctlz, i64, i64) | |
22 | +DEF_HELPER_1(cttz, i64, i64) | |
23 | + | |
24 | +DEF_HELPER_2(mskbl, i64, i64, i64) | |
25 | +DEF_HELPER_2(insbl, i64, i64, i64) | |
26 | +DEF_HELPER_2(mskwl, i64, i64, i64) | |
27 | +DEF_HELPER_2(inswl, i64, i64, i64) | |
28 | +DEF_HELPER_2(mskll, i64, i64, i64) | |
29 | +DEF_HELPER_2(insll, i64, i64, i64) | |
30 | +DEF_HELPER_2(zap, i64, i64, i64) | |
31 | +DEF_HELPER_2(zapnot, i64, i64, i64) | |
32 | +DEF_HELPER_2(mskql, i64, i64, i64) | |
33 | +DEF_HELPER_2(insql, i64, i64, i64) | |
34 | +DEF_HELPER_2(mskwh, i64, i64, i64) | |
35 | +DEF_HELPER_2(inswh, i64, i64, i64) | |
36 | +DEF_HELPER_2(msklh, i64, i64, i64) | |
37 | +DEF_HELPER_2(inslh, i64, i64, i64) | |
38 | +DEF_HELPER_2(mskqh, i64, i64, i64) | |
39 | +DEF_HELPER_2(insqh, i64, i64, i64) | |
40 | + | |
41 | +DEF_HELPER_2(cmpbge, i64, i64, i64) | |
42 | + | |
43 | +DEF_HELPER_0(load_fpcr, i64) | |
44 | +DEF_HELPER_1(store_fpcr, void, i64) | |
45 | + | |
46 | +DEF_HELPER_1(f_to_memory, i32, i64) | |
47 | +DEF_HELPER_1(memory_to_f, i64, i32) | |
48 | +DEF_HELPER_2(addf, i64, i64, i64) | |
49 | +DEF_HELPER_2(subf, i64, i64, i64) | |
50 | +DEF_HELPER_2(mulf, i64, i64, i64) | |
51 | +DEF_HELPER_2(divf, i64, i64, i64) | |
52 | +DEF_HELPER_1(sqrtf, i64, i64) | |
53 | + | |
54 | +DEF_HELPER_1(g_to_memory, i64, i64) | |
55 | +DEF_HELPER_1(memory_to_g, i64, i64) | |
56 | +DEF_HELPER_2(addg, i64, i64, i64) | |
57 | +DEF_HELPER_2(subg, i64, i64, i64) | |
58 | +DEF_HELPER_2(mulg, i64, i64, i64) | |
59 | +DEF_HELPER_2(divg, i64, i64, i64) | |
60 | +DEF_HELPER_1(sqrtg, i64, i64) | |
61 | + | |
62 | +DEF_HELPER_1(s_to_memory, i32, i64) | |
63 | +DEF_HELPER_1(memory_to_s, i64, i32) | |
64 | +DEF_HELPER_2(adds, i64, i64, i64) | |
65 | +DEF_HELPER_2(subs, i64, i64, i64) | |
66 | +DEF_HELPER_2(muls, i64, i64, i64) | |
67 | +DEF_HELPER_2(divs, i64, i64, i64) | |
68 | +DEF_HELPER_1(sqrts, i64, i64) | |
69 | + | |
70 | +DEF_HELPER_2(addt, i64, i64, i64) | |
71 | +DEF_HELPER_2(subt, i64, i64, i64) | |
72 | +DEF_HELPER_2(mult, i64, i64, i64) | |
73 | +DEF_HELPER_2(divt, i64, i64, i64) | |
74 | +DEF_HELPER_1(sqrtt, i64, i64) | |
75 | + | |
76 | +DEF_HELPER_2(cmptun, i64, i64, i64) | |
77 | +DEF_HELPER_2(cmpteq, i64, i64, i64) | |
78 | +DEF_HELPER_2(cmptle, i64, i64, i64) | |
79 | +DEF_HELPER_2(cmptlt, i64, i64, i64) | |
80 | +DEF_HELPER_2(cmpgeq, i64, i64, i64) | |
81 | +DEF_HELPER_2(cmpgle, i64, i64, i64) | |
82 | +DEF_HELPER_2(cmpglt, i64, i64, i64) | |
83 | + | |
84 | +DEF_HELPER_1(cmpfeq, i64, i64) | |
85 | +DEF_HELPER_1(cmpfne, i64, i64) | |
86 | +DEF_HELPER_1(cmpflt, i64, i64) | |
87 | +DEF_HELPER_1(cmpfle, i64, i64) | |
88 | +DEF_HELPER_1(cmpfgt, i64, i64) | |
89 | +DEF_HELPER_1(cmpfge, i64, i64) | |
90 | + | |
91 | +DEF_HELPER_2(cpys, i64, i64, i64) | |
92 | +DEF_HELPER_2(cpysn, i64, i64, i64) | |
93 | +DEF_HELPER_2(cpyse, i64, i64, i64) | |
94 | + | |
95 | +DEF_HELPER_1(cvtts, i64, i64) | |
96 | +DEF_HELPER_1(cvtst, i64, i64) | |
97 | +DEF_HELPER_1(cvttq, i64, i64) | |
98 | +DEF_HELPER_1(cvtqs, i64, i64) | |
99 | +DEF_HELPER_1(cvtqt, i64, i64) | |
100 | +DEF_HELPER_1(cvtqf, i64, i64) | |
101 | +DEF_HELPER_1(cvtgf, i64, i64) | |
102 | +DEF_HELPER_1(cvtgq, i64, i64) | |
103 | +DEF_HELPER_1(cvtqg, i64, i64) | |
104 | +DEF_HELPER_1(cvtlq, i64, i64) | |
105 | +DEF_HELPER_1(cvtql, i64, i64) | |
106 | +DEF_HELPER_1(cvtqlv, i64, i64) | |
107 | +DEF_HELPER_1(cvtqlsv, i64, i64) | |
110 | 108 | |
111 | 109 | #if !defined (CONFIG_USER_ONLY) |
112 | -DEF_HELPER(void, helper_hw_rei, (void)) | |
113 | -DEF_HELPER(void, helper_hw_ret, (uint64_t)) | |
114 | -DEF_HELPER(uint64_t, helper_mfpr, (int, uint64_t)) | |
115 | -DEF_HELPER(void, helper_mtpr, (int, uint64_t)) | |
116 | -DEF_HELPER(void, helper_set_alt_mode, (void)) | |
117 | -DEF_HELPER(void, helper_restore_mode, (void)) | |
118 | - | |
119 | -DEF_HELPER(uint64_t, helper_ld_virt_to_phys, (uint64_t)) | |
120 | -DEF_HELPER(uint64_t, helper_st_virt_to_phys, (uint64_t)) | |
121 | -DEF_HELPER(void, helper_ldl_raw, (uint64_t, uint64_t)) | |
122 | -DEF_HELPER(void, helper_ldq_raw, (uint64_t, uint64_t)) | |
123 | -DEF_HELPER(void, helper_ldl_l_raw, (uint64_t, uint64_t)) | |
124 | -DEF_HELPER(void, helper_ldq_l_raw, (uint64_t, uint64_t)) | |
125 | -DEF_HELPER(void, helper_ldl_kernel, (uint64_t, uint64_t)) | |
126 | -DEF_HELPER(void, helper_ldq_kernel, (uint64_t, uint64_t)) | |
127 | -DEF_HELPER(void, helper_ldl_data, (uint64_t, uint64_t)) | |
128 | -DEF_HELPER(void, helper_ldq_data, (uint64_t, uint64_t)) | |
129 | -DEF_HELPER(void, helper_stl_raw, (uint64_t, uint64_t)) | |
130 | -DEF_HELPER(void, helper_stq_raw, (uint64_t, uint64_t)) | |
131 | -DEF_HELPER(uint64_t, helper_stl_c_raw, (uint64_t, uint64_t)) | |
132 | -DEF_HELPER(uint64_t, helper_stq_c_raw, (uint64_t, uint64_t)) | |
110 | +DEF_HELPER_0(hw_rei, void) | |
111 | +DEF_HELPER_1(hw_ret, void, i64) | |
112 | +DEF_HELPER_2(mfpr, i64, int, i64) | |
113 | +DEF_HELPER_2(mtpr, void, int, i64) | |
114 | +DEF_HELPER_0(set_alt_mode, void) | |
115 | +DEF_HELPER_0(restore_mode, void) | |
116 | + | |
117 | +DEF_HELPER_1(ld_virt_to_phys, i64, i64) | |
118 | +DEF_HELPER_1(st_virt_to_phys, i64, i64) | |
119 | +DEF_HELPER_2(ldl_raw, void, i64, i64) | |
120 | +DEF_HELPER_2(ldq_raw, void, i64, i64) | |
121 | +DEF_HELPER_2(ldl_l_raw, void, i64, i64) | |
122 | +DEF_HELPER_2(ldq_l_raw, void, i64, i64) | |
123 | +DEF_HELPER_2(ldl_kernel, void, i64, i64) | |
124 | +DEF_HELPER_2(ldq_kernel, void, i64, i64) | |
125 | +DEF_HELPER_2(ldl_data, void, i64, i64) | |
126 | +DEF_HELPER_2(ldq_data, void, i64, i64) | |
127 | +DEF_HELPER_2(stl_raw, void, i64, i64) | |
128 | +DEF_HELPER_2(stq_raw, void, i64, i64) | |
129 | +DEF_HELPER_2(stl_c_raw, i64, i64, i64) | |
130 | +DEF_HELPER_2(stq_c_raw, i64, i64, i64) | |
133 | 131 | #endif |
132 | + | |
133 | +#include "def-helper.h" | ... | ... |
target-alpha/op_helper.c
target-alpha/translate.c
... | ... | @@ -26,10 +26,13 @@ |
26 | 26 | #include "exec-all.h" |
27 | 27 | #include "disas.h" |
28 | 28 | #include "host-utils.h" |
29 | -#include "helper.h" | |
30 | 29 | #include "tcg-op.h" |
31 | 30 | #include "qemu-common.h" |
32 | 31 | |
32 | +#include "helper.h" | |
33 | +#define GEN_HELPER 1 | |
34 | +#include "helper.h" | |
35 | + | |
33 | 36 | /* #define DO_SINGLE_STEP */ |
34 | 37 | #define ALPHA_DEBUG_DISAS |
35 | 38 | /* #define DO_TB_FLUSH */ |
... | ... | @@ -45,7 +48,7 @@ struct DisasContext { |
45 | 48 | }; |
46 | 49 | |
47 | 50 | /* global register indexes */ |
48 | -static TCGv cpu_env; | |
51 | +static TCGv_ptr cpu_env; | |
49 | 52 | static TCGv cpu_ir[31]; |
50 | 53 | static TCGv cpu_fir[31]; |
51 | 54 | static TCGv cpu_pc; |
... | ... | @@ -65,30 +68,29 @@ static void alpha_translate_init(void) |
65 | 68 | if (done_init) |
66 | 69 | return; |
67 | 70 | |
68 | - cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); | |
71 | + cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
69 | 72 | |
70 | 73 | p = cpu_reg_names; |
71 | 74 | for (i = 0; i < 31; i++) { |
72 | 75 | sprintf(p, "ir%d", i); |
73 | - cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, | |
74 | - offsetof(CPUState, ir[i]), p); | |
76 | + cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
77 | + offsetof(CPUState, ir[i]), p); | |
75 | 78 | p += (i < 10) ? 4 : 5; |
76 | 79 | |
77 | 80 | sprintf(p, "fir%d", i); |
78 | - cpu_fir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, | |
79 | - offsetof(CPUState, fir[i]), p); | |
81 | + cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
82 | + offsetof(CPUState, fir[i]), p); | |
80 | 83 | p += (i < 10) ? 5 : 6; |
81 | 84 | } |
82 | 85 | |
83 | - cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, | |
84 | - offsetof(CPUState, pc), "pc"); | |
86 | + cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, | |
87 | + offsetof(CPUState, pc), "pc"); | |
85 | 88 | |
86 | - cpu_lock = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, | |
87 | - offsetof(CPUState, lock), "lock"); | |
89 | + cpu_lock = tcg_global_mem_new_i64(TCG_AREG0, | |
90 | + offsetof(CPUState, lock), "lock"); | |
88 | 91 | |
89 | 92 | /* register helpers */ |
90 | -#undef DEF_HELPER | |
91 | -#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); | |
93 | +#define GEN_HELPER 2 | |
92 | 94 | #include "helper.h" |
93 | 95 | |
94 | 96 | done_init = 1; |
... | ... | @@ -97,14 +99,14 @@ static void alpha_translate_init(void) |
97 | 99 | static always_inline void gen_excp (DisasContext *ctx, |
98 | 100 | int exception, int error_code) |
99 | 101 | { |
100 | - TCGv tmp1, tmp2; | |
102 | + TCGv_i32 tmp1, tmp2; | |
101 | 103 | |
102 | 104 | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
103 | 105 | tmp1 = tcg_const_i32(exception); |
104 | 106 | tmp2 = tcg_const_i32(error_code); |
105 | - tcg_gen_helper_0_2(helper_excp, tmp1, tmp2); | |
106 | - tcg_temp_free(tmp2); | |
107 | - tcg_temp_free(tmp1); | |
107 | + gen_helper_excp(tmp1, tmp2); | |
108 | + tcg_temp_free_i32(tmp2); | |
109 | + tcg_temp_free_i32(tmp1); | |
108 | 110 | } |
109 | 111 | |
110 | 112 | static always_inline void gen_invalid (DisasContext *ctx) |
... | ... | @@ -114,25 +116,31 @@ static always_inline void gen_invalid (DisasContext *ctx) |
114 | 116 | |
115 | 117 | static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags) |
116 | 118 | { |
117 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I32); | |
119 | + TCGv tmp = tcg_temp_new(); | |
120 | + TCGv_i32 tmp32 = tcg_temp_new_i32(); | |
118 | 121 | tcg_gen_qemu_ld32u(tmp, t1, flags); |
119 | - tcg_gen_helper_1_1(helper_memory_to_f, t0, tmp); | |
122 | + tcg_gen_trunc_i64_i32(tmp32, tmp); | |
123 | + gen_helper_memory_to_f(t0, tmp32); | |
124 | + tcg_temp_free_i32(tmp32); | |
120 | 125 | tcg_temp_free(tmp); |
121 | 126 | } |
122 | 127 | |
123 | 128 | static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags) |
124 | 129 | { |
125 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
130 | + TCGv tmp = tcg_temp_new(); | |
126 | 131 | tcg_gen_qemu_ld64(tmp, t1, flags); |
127 | - tcg_gen_helper_1_1(helper_memory_to_g, t0, tmp); | |
132 | + gen_helper_memory_to_g(t0, tmp); | |
128 | 133 | tcg_temp_free(tmp); |
129 | 134 | } |
130 | 135 | |
131 | 136 | static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags) |
132 | 137 | { |
133 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I32); | |
138 | + TCGv tmp = tcg_temp_new(); | |
139 | + TCGv_i32 tmp32 = tcg_temp_new_i32(); | |
134 | 140 | tcg_gen_qemu_ld32u(tmp, t1, flags); |
135 | - tcg_gen_helper_1_1(helper_memory_to_s, t0, tmp); | |
141 | + tcg_gen_trunc_i64_i32(tmp32, tmp); | |
142 | + gen_helper_memory_to_s(t0, tmp32); | |
143 | + tcg_temp_free_i32(tmp32); | |
136 | 144 | tcg_temp_free(tmp); |
137 | 145 | } |
138 | 146 | |
... | ... | @@ -158,7 +166,7 @@ static always_inline void gen_load_mem (DisasContext *ctx, |
158 | 166 | if (unlikely(ra == 31)) |
159 | 167 | return; |
160 | 168 | |
161 | - addr = tcg_temp_new(TCG_TYPE_I64); | |
169 | + addr = tcg_temp_new(); | |
162 | 170 | if (rb != 31) { |
163 | 171 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
164 | 172 | if (clear) |
... | ... | @@ -177,26 +185,32 @@ static always_inline void gen_load_mem (DisasContext *ctx, |
177 | 185 | |
178 | 186 | static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags) |
179 | 187 | { |
180 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I32); | |
181 | - tcg_gen_helper_1_1(helper_f_to_memory, tmp, t0); | |
188 | + TCGv_i32 tmp32 = tcg_temp_new_i32(); | |
189 | + TCGv tmp = tcg_temp_new(); | |
190 | + gen_helper_f_to_memory(tmp32, t0); | |
191 | + tcg_gen_extu_i32_i64(tmp, tmp32); | |
182 | 192 | tcg_gen_qemu_st32(tmp, t1, flags); |
183 | 193 | tcg_temp_free(tmp); |
194 | + tcg_temp_free_i32(tmp32); | |
184 | 195 | } |
185 | 196 | |
186 | 197 | static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags) |
187 | 198 | { |
188 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
189 | - tcg_gen_helper_1_1(helper_g_to_memory, tmp, t0); | |
199 | + TCGv tmp = tcg_temp_new(); | |
200 | + gen_helper_g_to_memory(tmp, t0); | |
190 | 201 | tcg_gen_qemu_st64(tmp, t1, flags); |
191 | 202 | tcg_temp_free(tmp); |
192 | 203 | } |
193 | 204 | |
194 | 205 | static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags) |
195 | 206 | { |
196 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I32); | |
197 | - tcg_gen_helper_1_1(helper_s_to_memory, tmp, t0); | |
207 | + TCGv_i32 tmp32 = tcg_temp_new_i32(); | |
208 | + TCGv tmp = tcg_temp_new(); | |
209 | + gen_helper_s_to_memory(tmp32, t0); | |
210 | + tcg_gen_extu_i32_i64(tmp, tmp32); | |
198 | 211 | tcg_gen_qemu_st32(tmp, t1, flags); |
199 | 212 | tcg_temp_free(tmp); |
213 | + tcg_temp_free_i32(tmp32); | |
200 | 214 | } |
201 | 215 | |
202 | 216 | static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags) |
... | ... | @@ -238,9 +252,9 @@ static always_inline void gen_store_mem (DisasContext *ctx, |
238 | 252 | { |
239 | 253 | TCGv addr; |
240 | 254 | if (local) |
241 | - addr = tcg_temp_local_new(TCG_TYPE_I64); | |
255 | + addr = tcg_temp_local_new(); | |
242 | 256 | else |
243 | - addr = tcg_temp_new(TCG_TYPE_I64); | |
257 | + addr = tcg_temp_new(); | |
244 | 258 | if (rb != 31) { |
245 | 259 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
246 | 260 | if (clear) |
... | ... | @@ -277,7 +291,7 @@ static always_inline void gen_bcond (DisasContext *ctx, |
277 | 291 | l2 = gen_new_label(); |
278 | 292 | if (likely(ra != 31)) { |
279 | 293 | if (mask) { |
280 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
294 | + TCGv tmp = tcg_temp_new(); | |
281 | 295 | tcg_gen_andi_i64(tmp, cpu_ir[ra], 1); |
282 | 296 | tcg_gen_brcondi_i64(cond, tmp, 0, l1); |
283 | 297 | tcg_temp_free(tmp); |
... | ... | @@ -296,21 +310,43 @@ static always_inline void gen_bcond (DisasContext *ctx, |
296 | 310 | gen_set_label(l2); |
297 | 311 | } |
298 | 312 | |
299 | -static always_inline void gen_fbcond (DisasContext *ctx, | |
300 | - void* func, | |
313 | +static always_inline void gen_fbcond (DisasContext *ctx, int opc, | |
301 | 314 | int ra, int32_t disp16) |
302 | 315 | { |
303 | 316 | int l1, l2; |
304 | 317 | TCGv tmp; |
318 | + TCGv src; | |
305 | 319 | |
306 | 320 | l1 = gen_new_label(); |
307 | 321 | l2 = gen_new_label(); |
308 | 322 | if (ra != 31) { |
309 | - tmp = tcg_temp_new(TCG_TYPE_I64); | |
310 | - tcg_gen_helper_1_1(func, tmp, cpu_fir[ra]); | |
323 | + tmp = tcg_temp_new(); | |
324 | + src = cpu_fir[ra]; | |
311 | 325 | } else { |
312 | 326 | tmp = tcg_const_i64(0); |
313 | - tcg_gen_helper_1_1(func, tmp, tmp); | |
327 | + src = tmp; | |
328 | + } | |
329 | + switch (opc) { | |
330 | + case 0x31: /* FBEQ */ | |
331 | + gen_helper_cmpfeq(tmp, src); | |
332 | + break; | |
333 | + case 0x32: /* FBLT */ | |
334 | + gen_helper_cmpflt(tmp, src); | |
335 | + break; | |
336 | + case 0x33: /* FBLE */ | |
337 | + gen_helper_cmpfle(tmp, src); | |
338 | + break; | |
339 | + case 0x35: /* FBNE */ | |
340 | + gen_helper_cmpfne(tmp, src); | |
341 | + break; | |
342 | + case 0x36: /* FBGE */ | |
343 | + gen_helper_cmpfge(tmp, src); | |
344 | + break; | |
345 | + case 0x37: /* FBGT */ | |
346 | + gen_helper_cmpfgt(tmp, src); | |
347 | + break; | |
348 | + default: | |
349 | + abort(); | |
314 | 350 | } |
315 | 351 | tcg_gen_brcondi_i64(TCG_COND_NE, tmp, 0, l1); |
316 | 352 | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
... | ... | @@ -333,7 +369,7 @@ static always_inline void gen_cmov (TCGCond inv_cond, |
333 | 369 | |
334 | 370 | if (ra != 31) { |
335 | 371 | if (mask) { |
336 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
372 | + TCGv tmp = tcg_temp_new(); | |
337 | 373 | tcg_gen_andi_i64(tmp, cpu_ir[ra], 1); |
338 | 374 | tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1); |
339 | 375 | tcg_temp_free(tmp); |
... | ... | @@ -353,70 +389,120 @@ static always_inline void gen_cmov (TCGCond inv_cond, |
353 | 389 | gen_set_label(l1); |
354 | 390 | } |
355 | 391 | |
356 | -static always_inline void gen_farith2 (void *helper, | |
357 | - int rb, int rc) | |
358 | -{ | |
359 | - if (unlikely(rc == 31)) | |
360 | - return; | |
361 | - | |
362 | - if (rb != 31) | |
363 | - tcg_gen_helper_1_1(helper, cpu_fir[rc], cpu_fir[rb]); | |
364 | - else { | |
365 | - TCGv tmp = tcg_const_i64(0); | |
366 | - tcg_gen_helper_1_1(helper, cpu_fir[rc], tmp); | |
367 | - tcg_temp_free(tmp); | |
368 | - } | |
392 | +#define FARITH2(name) \ | |
393 | +static always_inline void glue(gen_f, name)(int rb, int rc) \ | |
394 | +{ \ | |
395 | + if (unlikely(rc == 31)) \ | |
396 | + return; \ | |
397 | + \ | |
398 | + if (rb != 31) \ | |
399 | + gen_helper_ ## name (cpu_fir[rc], cpu_fir[rb]); \ | |
400 | + else { \ | |
401 | + TCGv tmp = tcg_const_i64(0); \ | |
402 | + gen_helper_ ## name (cpu_fir[rc], tmp); \ | |
403 | + tcg_temp_free(tmp); \ | |
404 | + } \ | |
369 | 405 | } |
370 | - | |
371 | -static always_inline void gen_farith3 (void *helper, | |
372 | - int ra, int rb, int rc) | |
373 | -{ | |
374 | - if (unlikely(rc == 31)) | |
375 | - return; | |
376 | - | |
377 | - if (ra != 31) { | |
378 | - if (rb != 31) | |
379 | - tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]); | |
380 | - else { | |
381 | - TCGv tmp = tcg_const_i64(0); | |
382 | - tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], tmp); | |
383 | - tcg_temp_free(tmp); | |
384 | - } | |
385 | - } else { | |
386 | - TCGv tmp = tcg_const_i64(0); | |
387 | - if (rb != 31) | |
388 | - tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, cpu_fir[rb]); | |
389 | - else | |
390 | - tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, tmp); | |
391 | - tcg_temp_free(tmp); | |
392 | - } | |
406 | +FARITH2(sqrts) | |
407 | +FARITH2(sqrtf) | |
408 | +FARITH2(sqrtg) | |
409 | +FARITH2(sqrtt) | |
410 | +FARITH2(cvtgf) | |
411 | +FARITH2(cvtgq) | |
412 | +FARITH2(cvtqf) | |
413 | +FARITH2(cvtqg) | |
414 | +FARITH2(cvtst) | |
415 | +FARITH2(cvtts) | |
416 | +FARITH2(cvttq) | |
417 | +FARITH2(cvtqs) | |
418 | +FARITH2(cvtqt) | |
419 | +FARITH2(cvtlq) | |
420 | +FARITH2(cvtql) | |
421 | +FARITH2(cvtqlv) | |
422 | +FARITH2(cvtqlsv) | |
423 | + | |
424 | +#define FARITH3(name) \ | |
425 | +static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \ | |
426 | +{ \ | |
427 | + if (unlikely(rc == 31)) \ | |
428 | + return; \ | |
429 | + \ | |
430 | + if (ra != 31) { \ | |
431 | + if (rb != 31) \ | |
432 | + gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]); \ | |
433 | + else { \ | |
434 | + TCGv tmp = tcg_const_i64(0); \ | |
435 | + gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], tmp); \ | |
436 | + tcg_temp_free(tmp); \ | |
437 | + } \ | |
438 | + } else { \ | |
439 | + TCGv tmp = tcg_const_i64(0); \ | |
440 | + if (rb != 31) \ | |
441 | + gen_helper_ ## name (cpu_fir[rc], tmp, cpu_fir[rb]); \ | |
442 | + else \ | |
443 | + gen_helper_ ## name (cpu_fir[rc], tmp, tmp); \ | |
444 | + tcg_temp_free(tmp); \ | |
445 | + } \ | |
393 | 446 | } |
394 | 447 | |
395 | -static always_inline void gen_fcmov (void *func, | |
396 | - int ra, int rb, int rc) | |
397 | -{ | |
398 | - int l1; | |
399 | - TCGv tmp; | |
400 | - | |
401 | - if (unlikely(rc == 31)) | |
402 | - return; | |
403 | - | |
404 | - l1 = gen_new_label(); | |
405 | - tmp = tcg_temp_new(TCG_TYPE_I64); | |
406 | - if (ra != 31) { | |
407 | - tmp = tcg_temp_new(TCG_TYPE_I64); | |
408 | - tcg_gen_helper_1_1(func, tmp, cpu_fir[ra]); | |
409 | - } else { | |
410 | - tmp = tcg_const_i64(0); | |
411 | - tcg_gen_helper_1_1(func, tmp, tmp); | |
412 | - } | |
413 | - tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1); | |
414 | - if (rb != 31) | |
415 | - tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); | |
416 | - else | |
417 | - tcg_gen_movi_i64(cpu_fir[rc], 0); | |
418 | - gen_set_label(l1); | |
448 | +FARITH3(addf) | |
449 | +FARITH3(subf) | |
450 | +FARITH3(mulf) | |
451 | +FARITH3(divf) | |
452 | +FARITH3(addg) | |
453 | +FARITH3(subg) | |
454 | +FARITH3(mulg) | |
455 | +FARITH3(divg) | |
456 | +FARITH3(cmpgeq) | |
457 | +FARITH3(cmpglt) | |
458 | +FARITH3(cmpgle) | |
459 | +FARITH3(adds) | |
460 | +FARITH3(subs) | |
461 | +FARITH3(muls) | |
462 | +FARITH3(divs) | |
463 | +FARITH3(addt) | |
464 | +FARITH3(subt) | |
465 | +FARITH3(mult) | |
466 | +FARITH3(divt) | |
467 | +FARITH3(cmptun) | |
468 | +FARITH3(cmpteq) | |
469 | +FARITH3(cmptlt) | |
470 | +FARITH3(cmptle) | |
471 | +FARITH3(cpys) | |
472 | +FARITH3(cpysn) | |
473 | +FARITH3(cpyse) | |
474 | + | |
475 | +#define FCMOV(name) \ | |
476 | +static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \ | |
477 | +{ \ | |
478 | + int l1; \ | |
479 | + TCGv tmp; \ | |
480 | + \ | |
481 | + if (unlikely(rc == 31)) \ | |
482 | + return; \ | |
483 | + \ | |
484 | + l1 = gen_new_label(); \ | |
485 | + tmp = tcg_temp_new(); \ | |
486 | + if (ra != 31) { \ | |
487 | + tmp = tcg_temp_new(); \ | |
488 | + gen_helper_ ## name (tmp, cpu_fir[ra]); \ | |
489 | + } else { \ | |
490 | + tmp = tcg_const_i64(0); \ | |
491 | + gen_helper_ ## name (tmp, tmp); \ | |
492 | + } \ | |
493 | + tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1); \ | |
494 | + if (rb != 31) \ | |
495 | + tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); \ | |
496 | + else \ | |
497 | + tcg_gen_movi_i64(cpu_fir[rc], 0); \ | |
498 | + gen_set_label(l1); \ | |
419 | 499 | } |
500 | +FCMOV(cmpfeq) | |
501 | +FCMOV(cmpfne) | |
502 | +FCMOV(cmpflt) | |
503 | +FCMOV(cmpfge) | |
504 | +FCMOV(cmpfle) | |
505 | +FCMOV(cmpfgt) | |
420 | 506 | |
421 | 507 | /* EXTWH, EXTWH, EXTLH, EXTQH */ |
422 | 508 | static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
... | ... | @@ -434,7 +520,7 @@ static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
434 | 520 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]); |
435 | 521 | } else { |
436 | 522 | TCGv tmp1, tmp2; |
437 | - tmp1 = tcg_temp_new(TCG_TYPE_I64); | |
523 | + tmp1 = tcg_temp_new(); | |
438 | 524 | tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7); |
439 | 525 | tcg_gen_shli_i64(tmp1, tmp1, 3); |
440 | 526 | tmp2 = tcg_const_i64(64); |
... | ... | @@ -461,7 +547,7 @@ static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
461 | 547 | if (islit) { |
462 | 548 | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8); |
463 | 549 | } else { |
464 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
550 | + TCGv tmp = tcg_temp_new(); | |
465 | 551 | tcg_gen_andi_i64(tmp, cpu_ir[rb], 7); |
466 | 552 | tcg_gen_shli_i64(tmp, tmp, 3); |
467 | 553 | tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp); |
... | ... | @@ -474,31 +560,55 @@ static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
474 | 560 | } |
475 | 561 | |
476 | 562 | /* Code to call arith3 helpers */ |
477 | -static always_inline void gen_arith3 (void *helper, | |
478 | - int ra, int rb, int rc, | |
479 | - int islit, uint8_t lit) | |
480 | -{ | |
481 | - if (unlikely(rc == 31)) | |
482 | - return; | |
483 | - | |
484 | - if (ra != 31) { | |
485 | - if (islit) { | |
486 | - TCGv tmp = tcg_const_i64(lit); | |
487 | - tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], tmp); | |
488 | - tcg_temp_free(tmp); | |
489 | - } else | |
490 | - tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); | |
491 | - } else { | |
492 | - TCGv tmp1 = tcg_const_i64(0); | |
493 | - if (islit) { | |
494 | - TCGv tmp2 = tcg_const_i64(lit); | |
495 | - tcg_gen_helper_1_2(helper, cpu_ir[rc], tmp1, tmp2); | |
496 | - tcg_temp_free(tmp2); | |
497 | - } else | |
498 | - tcg_gen_helper_1_2(helper, cpu_ir[rc], tmp1, cpu_ir[rb]); | |
499 | - tcg_temp_free(tmp1); | |
500 | - } | |
563 | +#define ARITH3(name) \ | |
564 | +static always_inline void glue(gen_, name) (int ra, int rb, int rc, \ | |
565 | + int islit, uint8_t lit) \ | |
566 | +{ \ | |
567 | + if (unlikely(rc == 31)) \ | |
568 | + return; \ | |
569 | + \ | |
570 | + if (ra != 31) { \ | |
571 | + if (islit) { \ | |
572 | + TCGv tmp = tcg_const_i64(lit); \ | |
573 | + gen_helper_ ## name(cpu_ir[rc], cpu_ir[ra], tmp); \ | |
574 | + tcg_temp_free(tmp); \ | |
575 | + } else \ | |
576 | + gen_helper_ ## name (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); \ | |
577 | + } else { \ | |
578 | + TCGv tmp1 = tcg_const_i64(0); \ | |
579 | + if (islit) { \ | |
580 | + TCGv tmp2 = tcg_const_i64(lit); \ | |
581 | + gen_helper_ ## name (cpu_ir[rc], tmp1, tmp2); \ | |
582 | + tcg_temp_free(tmp2); \ | |
583 | + } else \ | |
584 | + gen_helper_ ## name (cpu_ir[rc], tmp1, cpu_ir[rb]); \ | |
585 | + tcg_temp_free(tmp1); \ | |
586 | + } \ | |
501 | 587 | } |
588 | +ARITH3(cmpbge) | |
589 | +ARITH3(addlv) | |
590 | +ARITH3(sublv) | |
591 | +ARITH3(addqv) | |
592 | +ARITH3(subqv) | |
593 | +ARITH3(mskbl) | |
594 | +ARITH3(insbl) | |
595 | +ARITH3(mskwl) | |
596 | +ARITH3(inswl) | |
597 | +ARITH3(mskll) | |
598 | +ARITH3(insll) | |
599 | +ARITH3(zap) | |
600 | +ARITH3(zapnot) | |
601 | +ARITH3(mskql) | |
602 | +ARITH3(insql) | |
603 | +ARITH3(mskwh) | |
604 | +ARITH3(inswh) | |
605 | +ARITH3(msklh) | |
606 | +ARITH3(inslh) | |
607 | +ARITH3(mskqh) | |
608 | +ARITH3(insqh) | |
609 | +ARITH3(umulh) | |
610 | +ARITH3(mullv) | |
611 | +ARITH3(mulqv) | |
502 | 612 | |
503 | 613 | static always_inline void gen_cmp(TCGCond cond, |
504 | 614 | int ra, int rb, int rc, |
... | ... | @@ -514,7 +624,7 @@ static always_inline void gen_cmp(TCGCond cond, |
514 | 624 | l2 = gen_new_label(); |
515 | 625 | |
516 | 626 | if (ra != 31) { |
517 | - tmp = tcg_temp_new(TCG_TYPE_I64); | |
627 | + tmp = tcg_temp_new(); | |
518 | 628 | tcg_gen_mov_i64(tmp, cpu_ir[ra]); |
519 | 629 | } else |
520 | 630 | tmp = tcg_const_i64(0); |
... | ... | @@ -679,7 +789,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
679 | 789 | /* S4ADDL */ |
680 | 790 | if (likely(rc != 31)) { |
681 | 791 | if (ra != 31) { |
682 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
792 | + TCGv tmp = tcg_temp_new(); | |
683 | 793 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2); |
684 | 794 | if (islit) |
685 | 795 | tcg_gen_addi_i64(tmp, tmp, lit); |
... | ... | @@ -717,7 +827,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
717 | 827 | /* S4SUBL */ |
718 | 828 | if (likely(rc != 31)) { |
719 | 829 | if (ra != 31) { |
720 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
830 | + TCGv tmp = tcg_temp_new(); | |
721 | 831 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2); |
722 | 832 | if (islit) |
723 | 833 | tcg_gen_subi_i64(tmp, tmp, lit); |
... | ... | @@ -737,13 +847,13 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
737 | 847 | break; |
738 | 848 | case 0x0F: |
739 | 849 | /* CMPBGE */ |
740 | - gen_arith3(helper_cmpbge, ra, rb, rc, islit, lit); | |
850 | + gen_cmpbge(ra, rb, rc, islit, lit); | |
741 | 851 | break; |
742 | 852 | case 0x12: |
743 | 853 | /* S8ADDL */ |
744 | 854 | if (likely(rc != 31)) { |
745 | 855 | if (ra != 31) { |
746 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
856 | + TCGv tmp = tcg_temp_new(); | |
747 | 857 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3); |
748 | 858 | if (islit) |
749 | 859 | tcg_gen_addi_i64(tmp, tmp, lit); |
... | ... | @@ -763,7 +873,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
763 | 873 | /* S8SUBL */ |
764 | 874 | if (likely(rc != 31)) { |
765 | 875 | if (ra != 31) { |
766 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
876 | + TCGv tmp = tcg_temp_new(); | |
767 | 877 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3); |
768 | 878 | if (islit) |
769 | 879 | tcg_gen_subi_i64(tmp, tmp, lit); |
... | ... | @@ -805,7 +915,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
805 | 915 | /* S4ADDQ */ |
806 | 916 | if (likely(rc != 31)) { |
807 | 917 | if (ra != 31) { |
808 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
918 | + TCGv tmp = tcg_temp_new(); | |
809 | 919 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2); |
810 | 920 | if (islit) |
811 | 921 | tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
... | ... | @@ -840,7 +950,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
840 | 950 | /* S4SUBQ */ |
841 | 951 | if (likely(rc != 31)) { |
842 | 952 | if (ra != 31) { |
843 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
953 | + TCGv tmp = tcg_temp_new(); | |
844 | 954 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2); |
845 | 955 | if (islit) |
846 | 956 | tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
... | ... | @@ -863,7 +973,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
863 | 973 | /* S8ADDQ */ |
864 | 974 | if (likely(rc != 31)) { |
865 | 975 | if (ra != 31) { |
866 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
976 | + TCGv tmp = tcg_temp_new(); | |
867 | 977 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3); |
868 | 978 | if (islit) |
869 | 979 | tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
... | ... | @@ -882,7 +992,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
882 | 992 | /* S8SUBQ */ |
883 | 993 | if (likely(rc != 31)) { |
884 | 994 | if (ra != 31) { |
885 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); | |
995 | + TCGv tmp = tcg_temp_new(); | |
886 | 996 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3); |
887 | 997 | if (islit) |
888 | 998 | tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
... | ... | @@ -903,11 +1013,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
903 | 1013 | break; |
904 | 1014 | case 0x40: |
905 | 1015 | /* ADDL/V */ |
906 | - gen_arith3(helper_addlv, ra, rb, rc, islit, lit); | |
1016 | + gen_addlv(ra, rb, rc, islit, lit); | |
907 | 1017 | break; |
908 | 1018 | case 0x49: |
909 | 1019 | /* SUBL/V */ |
910 | - gen_arith3(helper_sublv, ra, rb, rc, islit, lit); | |
1020 | + gen_sublv(ra, rb, rc, islit, lit); | |
911 | 1021 | break; |
912 | 1022 | case 0x4D: |
913 | 1023 | /* CMPLT */ |
... | ... | @@ -915,11 +1025,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
915 | 1025 | break; |
916 | 1026 | case 0x60: |
917 | 1027 | /* ADDQ/V */ |
918 | - gen_arith3(helper_addqv, ra, rb, rc, islit, lit); | |
1028 | + gen_addqv(ra, rb, rc, islit, lit); | |
919 | 1029 | break; |
920 | 1030 | case 0x69: |
921 | 1031 | /* SUBQ/V */ |
922 | - gen_arith3(helper_subqv, ra, rb, rc, islit, lit); | |
1032 | + gen_subqv(ra, rb, rc, islit, lit); | |
923 | 1033 | break; |
924 | 1034 | case 0x6D: |
925 | 1035 | /* CMPLE */ |
... | ... | @@ -1048,7 +1158,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1048 | 1158 | if (islit) |
1049 | 1159 | tcg_gen_movi_i64(cpu_ir[rc], helper_amask(lit)); |
1050 | 1160 | else |
1051 | - tcg_gen_helper_1_1(helper_amask, cpu_ir[rc], cpu_ir[rb]); | |
1161 | + gen_helper_amask(cpu_ir[rc], cpu_ir[rb]); | |
1052 | 1162 | } |
1053 | 1163 | break; |
1054 | 1164 | case 0x64: |
... | ... | @@ -1062,7 +1172,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1062 | 1172 | case 0x6C: |
1063 | 1173 | /* IMPLVER */ |
1064 | 1174 | if (rc != 31) |
1065 | - tcg_gen_helper_1_0(helper_load_implver, cpu_ir[rc]); | |
1175 | + gen_helper_load_implver(cpu_ir[rc]); | |
1066 | 1176 | break; |
1067 | 1177 | default: |
1068 | 1178 | goto invalid_opc; |
... | ... | @@ -1072,7 +1182,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1072 | 1182 | switch (fn7) { |
1073 | 1183 | case 0x02: |
1074 | 1184 | /* MSKBL */ |
1075 | - gen_arith3(helper_mskbl, ra, rb, rc, islit, lit); | |
1185 | + gen_mskbl(ra, rb, rc, islit, lit); | |
1076 | 1186 | break; |
1077 | 1187 | case 0x06: |
1078 | 1188 | /* EXTBL */ |
... | ... | @@ -1080,11 +1190,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1080 | 1190 | break; |
1081 | 1191 | case 0x0B: |
1082 | 1192 | /* INSBL */ |
1083 | - gen_arith3(helper_insbl, ra, rb, rc, islit, lit); | |
1193 | + gen_insbl(ra, rb, rc, islit, lit); | |
1084 | 1194 | break; |
1085 | 1195 | case 0x12: |
1086 | 1196 | /* MSKWL */ |
1087 | - gen_arith3(helper_mskwl, ra, rb, rc, islit, lit); | |
1197 | + gen_mskwl(ra, rb, rc, islit, lit); | |
1088 | 1198 | break; |
1089 | 1199 | case 0x16: |
1090 | 1200 | /* EXTWL */ |
... | ... | @@ -1092,11 +1202,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1092 | 1202 | break; |
1093 | 1203 | case 0x1B: |
1094 | 1204 | /* INSWL */ |
1095 | - gen_arith3(helper_inswl, ra, rb, rc, islit, lit); | |
1205 | + gen_inswl(ra, rb, rc, islit, lit); | |
1096 | 1206 | break; |
1097 | 1207 | case 0x22: |
1098 | 1208 | /* MSKLL */ |
1099 | - gen_arith3(helper_mskll, ra, rb, rc, islit, lit); | |
1209 | + gen_mskll(ra, rb, rc, islit, lit); | |
1100 | 1210 | break; |
1101 | 1211 | case 0x26: |
1102 | 1212 | /* EXTLL */ |
... | ... | @@ -1104,19 +1214,19 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1104 | 1214 | break; |
1105 | 1215 | case 0x2B: |
1106 | 1216 | /* INSLL */ |
1107 | - gen_arith3(helper_insll, ra, rb, rc, islit, lit); | |
1217 | + gen_insll(ra, rb, rc, islit, lit); | |
1108 | 1218 | break; |
1109 | 1219 | case 0x30: |
1110 | 1220 | /* ZAP */ |
1111 | - gen_arith3(helper_zap, ra, rb, rc, islit, lit); | |
1221 | + gen_zap(ra, rb, rc, islit, lit); | |
1112 | 1222 | break; |
1113 | 1223 | case 0x31: |
1114 | 1224 | /* ZAPNOT */ |
1115 | - gen_arith3(helper_zapnot, ra, rb, rc, islit, lit); | |
1225 | + gen_zapnot(ra, rb, rc, islit, lit); | |
1116 | 1226 | break; |
1117 | 1227 | case 0x32: |
1118 | 1228 | /* MSKQL */ |
1119 | - gen_arith3(helper_mskql, ra, rb, rc, islit, lit); | |
1229 | + gen_mskql(ra, rb, rc, islit, lit); | |
1120 | 1230 | break; |
1121 | 1231 | case 0x34: |
1122 | 1232 | /* SRL */ |
... | ... | @@ -1125,7 +1235,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1125 | 1235 | if (islit) |
1126 | 1236 | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f); |
1127 | 1237 | else { |
1128 | - TCGv shift = tcg_temp_new(TCG_TYPE_I64); | |
1238 | + TCGv shift = tcg_temp_new(); | |
1129 | 1239 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f); |
1130 | 1240 | tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift); |
1131 | 1241 | tcg_temp_free(shift); |
... | ... | @@ -1145,7 +1255,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1145 | 1255 | if (islit) |
1146 | 1256 | tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f); |
1147 | 1257 | else { |
1148 | - TCGv shift = tcg_temp_new(TCG_TYPE_I64); | |
1258 | + TCGv shift = tcg_temp_new(); | |
1149 | 1259 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f); |
1150 | 1260 | tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift); |
1151 | 1261 | tcg_temp_free(shift); |
... | ... | @@ -1156,7 +1266,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1156 | 1266 | break; |
1157 | 1267 | case 0x3B: |
1158 | 1268 | /* INSQL */ |
1159 | - gen_arith3(helper_insql, ra, rb, rc, islit, lit); | |
1269 | + gen_insql(ra, rb, rc, islit, lit); | |
1160 | 1270 | break; |
1161 | 1271 | case 0x3C: |
1162 | 1272 | /* SRA */ |
... | ... | @@ -1165,7 +1275,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1165 | 1275 | if (islit) |
1166 | 1276 | tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f); |
1167 | 1277 | else { |
1168 | - TCGv shift = tcg_temp_new(TCG_TYPE_I64); | |
1278 | + TCGv shift = tcg_temp_new(); | |
1169 | 1279 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f); |
1170 | 1280 | tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift); |
1171 | 1281 | tcg_temp_free(shift); |
... | ... | @@ -1176,11 +1286,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1176 | 1286 | break; |
1177 | 1287 | case 0x52: |
1178 | 1288 | /* MSKWH */ |
1179 | - gen_arith3(helper_mskwh, ra, rb, rc, islit, lit); | |
1289 | + gen_mskwh(ra, rb, rc, islit, lit); | |
1180 | 1290 | break; |
1181 | 1291 | case 0x57: |
1182 | 1292 | /* INSWH */ |
1183 | - gen_arith3(helper_inswh, ra, rb, rc, islit, lit); | |
1293 | + gen_inswh(ra, rb, rc, islit, lit); | |
1184 | 1294 | break; |
1185 | 1295 | case 0x5A: |
1186 | 1296 | /* EXTWH */ |
... | ... | @@ -1188,11 +1298,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1188 | 1298 | break; |
1189 | 1299 | case 0x62: |
1190 | 1300 | /* MSKLH */ |
1191 | - gen_arith3(helper_msklh, ra, rb, rc, islit, lit); | |
1301 | + gen_msklh(ra, rb, rc, islit, lit); | |
1192 | 1302 | break; |
1193 | 1303 | case 0x67: |
1194 | 1304 | /* INSLH */ |
1195 | - gen_arith3(helper_inslh, ra, rb, rc, islit, lit); | |
1305 | + gen_inslh(ra, rb, rc, islit, lit); | |
1196 | 1306 | break; |
1197 | 1307 | case 0x6A: |
1198 | 1308 | /* EXTLH */ |
... | ... | @@ -1200,11 +1310,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1200 | 1310 | break; |
1201 | 1311 | case 0x72: |
1202 | 1312 | /* MSKQH */ |
1203 | - gen_arith3(helper_mskqh, ra, rb, rc, islit, lit); | |
1313 | + gen_mskqh(ra, rb, rc, islit, lit); | |
1204 | 1314 | break; |
1205 | 1315 | case 0x77: |
1206 | 1316 | /* INSQH */ |
1207 | - gen_arith3(helper_insqh, ra, rb, rc, islit, lit); | |
1317 | + gen_insqh(ra, rb, rc, islit, lit); | |
1208 | 1318 | break; |
1209 | 1319 | case 0x7A: |
1210 | 1320 | /* EXTQH */ |
... | ... | @@ -1243,15 +1353,15 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1243 | 1353 | break; |
1244 | 1354 | case 0x30: |
1245 | 1355 | /* UMULH */ |
1246 | - gen_arith3(helper_umulh, ra, rb, rc, islit, lit); | |
1356 | + gen_umulh(ra, rb, rc, islit, lit); | |
1247 | 1357 | break; |
1248 | 1358 | case 0x40: |
1249 | 1359 | /* MULL/V */ |
1250 | - gen_arith3(helper_mullv, ra, rb, rc, islit, lit); | |
1360 | + gen_mullv(ra, rb, rc, islit, lit); | |
1251 | 1361 | break; |
1252 | 1362 | case 0x60: |
1253 | 1363 | /* MULQ/V */ |
1254 | - gen_arith3(helper_mulqv, ra, rb, rc, islit, lit); | |
1364 | + gen_mulqv(ra, rb, rc, islit, lit); | |
1255 | 1365 | break; |
1256 | 1366 | default: |
1257 | 1367 | goto invalid_opc; |
... | ... | @@ -1265,10 +1375,10 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1265 | 1375 | goto invalid_opc; |
1266 | 1376 | if (likely(rc != 31)) { |
1267 | 1377 | if (ra != 31) { |
1268 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I32); | |
1378 | + TCGv_i32 tmp = tcg_temp_new_i32(); | |
1269 | 1379 | tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
1270 | - tcg_gen_helper_1_1(helper_memory_to_s, cpu_fir[rc], tmp); | |
1271 | - tcg_temp_free(tmp); | |
1380 | + gen_helper_memory_to_s(cpu_fir[rc], tmp); | |
1381 | + tcg_temp_free_i32(tmp); | |
1272 | 1382 | } else |
1273 | 1383 | tcg_gen_movi_i64(cpu_fir[rc], 0); |
1274 | 1384 | } |
... | ... | @@ -1277,13 +1387,13 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1277 | 1387 | /* SQRTF */ |
1278 | 1388 | if (!(ctx->amask & AMASK_FIX)) |
1279 | 1389 | goto invalid_opc; |
1280 | - gen_farith2(&helper_sqrtf, rb, rc); | |
1390 | + gen_fsqrtf(rb, rc); | |
1281 | 1391 | break; |
1282 | 1392 | case 0x0B: |
1283 | 1393 | /* SQRTS */ |
1284 | 1394 | if (!(ctx->amask & AMASK_FIX)) |
1285 | 1395 | goto invalid_opc; |
1286 | - gen_farith2(&helper_sqrts, rb, rc); | |
1396 | + gen_fsqrts(rb, rc); | |
1287 | 1397 | break; |
1288 | 1398 | case 0x14: |
1289 | 1399 | /* ITOFF */ |
... | ... | @@ -1291,10 +1401,10 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1291 | 1401 | goto invalid_opc; |
1292 | 1402 | if (likely(rc != 31)) { |
1293 | 1403 | if (ra != 31) { |
1294 | - TCGv tmp = tcg_temp_new(TCG_TYPE_I32); | |
1404 | + TCGv_i32 tmp = tcg_temp_new_i32(); | |
1295 | 1405 | tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
1296 | - tcg_gen_helper_1_1(helper_memory_to_f, cpu_fir[rc], tmp); | |
1297 | - tcg_temp_free(tmp); | |
1406 | + gen_helper_memory_to_f(cpu_fir[rc], tmp); | |
1407 | + tcg_temp_free_i32(tmp); | |
1298 | 1408 | } else |
1299 | 1409 | tcg_gen_movi_i64(cpu_fir[rc], 0); |
1300 | 1410 | } |
... | ... | @@ -1314,13 +1424,13 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1314 | 1424 | /* SQRTG */ |
1315 | 1425 | if (!(ctx->amask & AMASK_FIX)) |
1316 | 1426 | goto invalid_opc; |
1317 | - gen_farith2(&helper_sqrtg, rb, rc); | |
1427 | + gen_fsqrtg(rb, rc); | |
1318 | 1428 | break; |
1319 | 1429 | case 0x02B: |
1320 | 1430 | /* SQRTT */ |
1321 | 1431 | if (!(ctx->amask & AMASK_FIX)) |
1322 | 1432 | goto invalid_opc; |
1323 | - gen_farith2(&helper_sqrtt, rb, rc); | |
1433 | + gen_fsqrtt(rb, rc); | |
1324 | 1434 | break; |
1325 | 1435 | default: |
1326 | 1436 | goto invalid_opc; |
... | ... | @@ -1332,79 +1442,79 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1332 | 1442 | switch (fpfn) { /* f11 & 0x3F */ |
1333 | 1443 | case 0x00: |
1334 | 1444 | /* ADDF */ |
1335 | - gen_farith3(&helper_addf, ra, rb, rc); | |
1445 | + gen_faddf(ra, rb, rc); | |
1336 | 1446 | break; |
1337 | 1447 | case 0x01: |
1338 | 1448 | /* SUBF */ |
1339 | - gen_farith3(&helper_subf, ra, rb, rc); | |
1449 | + gen_fsubf(ra, rb, rc); | |
1340 | 1450 | break; |
1341 | 1451 | case 0x02: |
1342 | 1452 | /* MULF */ |
1343 | - gen_farith3(&helper_mulf, ra, rb, rc); | |
1453 | + gen_fmulf(ra, rb, rc); | |
1344 | 1454 | break; |
1345 | 1455 | case 0x03: |
1346 | 1456 | /* DIVF */ |
1347 | - gen_farith3(&helper_divf, ra, rb, rc); | |
1457 | + gen_fdivf(ra, rb, rc); | |
1348 | 1458 | break; |
1349 | 1459 | case 0x1E: |
1350 | 1460 | /* CVTDG */ |
1351 | 1461 | #if 0 // TODO |
1352 | - gen_farith2(&helper_cvtdg, rb, rc); | |
1462 | + gen_fcvtdg(rb, rc); | |
1353 | 1463 | #else |
1354 | 1464 | goto invalid_opc; |
1355 | 1465 | #endif |
1356 | 1466 | break; |
1357 | 1467 | case 0x20: |
1358 | 1468 | /* ADDG */ |
1359 | - gen_farith3(&helper_addg, ra, rb, rc); | |
1469 | + gen_faddg(ra, rb, rc); | |
1360 | 1470 | break; |
1361 | 1471 | case 0x21: |
1362 | 1472 | /* SUBG */ |
1363 | - gen_farith3(&helper_subg, ra, rb, rc); | |
1473 | + gen_fsubg(ra, rb, rc); | |
1364 | 1474 | break; |
1365 | 1475 | case 0x22: |
1366 | 1476 | /* MULG */ |
1367 | - gen_farith3(&helper_mulg, ra, rb, rc); | |
1477 | + gen_fmulg(ra, rb, rc); | |
1368 | 1478 | break; |
1369 | 1479 | case 0x23: |
1370 | 1480 | /* DIVG */ |
1371 | - gen_farith3(&helper_divg, ra, rb, rc); | |
1481 | + gen_fdivg(ra, rb, rc); | |
1372 | 1482 | break; |
1373 | 1483 | case 0x25: |
1374 | 1484 | /* CMPGEQ */ |
1375 | - gen_farith3(&helper_cmpgeq, ra, rb, rc); | |
1485 | + gen_fcmpgeq(ra, rb, rc); | |
1376 | 1486 | break; |
1377 | 1487 | case 0x26: |
1378 | 1488 | /* CMPGLT */ |
1379 | - gen_farith3(&helper_cmpglt, ra, rb, rc); | |
1489 | + gen_fcmpglt(ra, rb, rc); | |
1380 | 1490 | break; |
1381 | 1491 | case 0x27: |
1382 | 1492 | /* CMPGLE */ |
1383 | - gen_farith3(&helper_cmpgle, ra, rb, rc); | |
1493 | + gen_fcmpgle(ra, rb, rc); | |
1384 | 1494 | break; |
1385 | 1495 | case 0x2C: |
1386 | 1496 | /* CVTGF */ |
1387 | - gen_farith2(&helper_cvtgf, rb, rc); | |
1497 | + gen_fcvtgf(rb, rc); | |
1388 | 1498 | break; |
1389 | 1499 | case 0x2D: |
1390 | 1500 | /* CVTGD */ |
1391 | 1501 | #if 0 // TODO |
1392 | - gen_farith2(ctx, &helper_cvtgd, rb, rc); | |
1502 | + gen_fcvtgd(rb, rc); | |
1393 | 1503 | #else |
1394 | 1504 | goto invalid_opc; |
1395 | 1505 | #endif |
1396 | 1506 | break; |
1397 | 1507 | case 0x2F: |
1398 | 1508 | /* CVTGQ */ |
1399 | - gen_farith2(&helper_cvtgq, rb, rc); | |
1509 | + gen_fcvtgq(rb, rc); | |
1400 | 1510 | break; |
1401 | 1511 | case 0x3C: |
1402 | 1512 | /* CVTQF */ |
1403 | - gen_farith2(&helper_cvtqf, rb, rc); | |
1513 | + gen_fcvtqf(rb, rc); | |
1404 | 1514 | break; |
1405 | 1515 | case 0x3E: |
1406 | 1516 | /* CVTQG */ |
1407 | - gen_farith2(&helper_cvtqg, rb, rc); | |
1517 | + gen_fcvtqg(rb, rc); | |
1408 | 1518 | break; |
1409 | 1519 | default: |
1410 | 1520 | goto invalid_opc; |
... | ... | @@ -1416,73 +1526,73 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1416 | 1526 | switch (fpfn) { /* f11 & 0x3F */ |
1417 | 1527 | case 0x00: |
1418 | 1528 | /* ADDS */ |
1419 | - gen_farith3(&helper_adds, ra, rb, rc); | |
1529 | + gen_fadds(ra, rb, rc); | |
1420 | 1530 | break; |
1421 | 1531 | case 0x01: |
1422 | 1532 | /* SUBS */ |
1423 | - gen_farith3(&helper_subs, ra, rb, rc); | |
1533 | + gen_fsubs(ra, rb, rc); | |
1424 | 1534 | break; |
1425 | 1535 | case 0x02: |
1426 | 1536 | /* MULS */ |
1427 | - gen_farith3(&helper_muls, ra, rb, rc); | |
1537 | + gen_fmuls(ra, rb, rc); | |
1428 | 1538 | break; |
1429 | 1539 | case 0x03: |
1430 | 1540 | /* DIVS */ |
1431 | - gen_farith3(&helper_divs, ra, rb, rc); | |
1541 | + gen_fdivs(ra, rb, rc); | |
1432 | 1542 | break; |
1433 | 1543 | case 0x20: |
1434 | 1544 | /* ADDT */ |
1435 | - gen_farith3(&helper_addt, ra, rb, rc); | |
1545 | + gen_faddt(ra, rb, rc); | |
1436 | 1546 | break; |
1437 | 1547 | case 0x21: |
1438 | 1548 | /* SUBT */ |
1439 | - gen_farith3(&helper_subt, ra, rb, rc); | |
1549 | + gen_fsubt(ra, rb, rc); | |
1440 | 1550 | break; |
1441 | 1551 | case 0x22: |
1442 | 1552 | /* MULT */ |
1443 | - gen_farith3(&helper_mult, ra, rb, rc); | |
1553 | + gen_fmult(ra, rb, rc); | |
1444 | 1554 | break; |
1445 | 1555 | case 0x23: |
1446 | 1556 | /* DIVT */ |
1447 | - gen_farith3(&helper_divt, ra, rb, rc); | |
1557 | + gen_fdivt(ra, rb, rc); | |
1448 | 1558 | break; |
1449 | 1559 | case 0x24: |
1450 | 1560 | /* CMPTUN */ |
1451 | - gen_farith3(&helper_cmptun, ra, rb, rc); | |
1561 | + gen_fcmptun(ra, rb, rc); | |
1452 | 1562 | break; |
1453 | 1563 | case 0x25: |
1454 | 1564 | /* CMPTEQ */ |
1455 | - gen_farith3(&helper_cmpteq, ra, rb, rc); | |
1565 | + gen_fcmpteq(ra, rb, rc); | |
1456 | 1566 | break; |
1457 | 1567 | case 0x26: |
1458 | 1568 | /* CMPTLT */ |
1459 | - gen_farith3(&helper_cmptlt, ra, rb, rc); | |
1569 | + gen_fcmptlt(ra, rb, rc); | |
1460 | 1570 | break; |
1461 | 1571 | case 0x27: |
1462 | 1572 | /* CMPTLE */ |
1463 | - gen_farith3(&helper_cmptle, ra, rb, rc); | |
1573 | + gen_fcmptle(ra, rb, rc); | |
1464 | 1574 | break; |
1465 | 1575 | case 0x2C: |
1466 | 1576 | /* XXX: incorrect */ |
1467 | 1577 | if (fn11 == 0x2AC || fn11 == 0x6AC) { |
1468 | 1578 | /* CVTST */ |
1469 | - gen_farith2(&helper_cvtst, rb, rc); | |
1579 | + gen_fcvtst(rb, rc); | |
1470 | 1580 | } else { |
1471 | 1581 | /* CVTTS */ |
1472 | - gen_farith2(&helper_cvtts, rb, rc); | |
1582 | + gen_fcvtts(rb, rc); | |
1473 | 1583 | } |
1474 | 1584 | break; |
1475 | 1585 | case 0x2F: |
1476 | 1586 | /* CVTTQ */ |
1477 | - gen_farith2(&helper_cvttq, rb, rc); | |
1587 | + gen_fcvttq(rb, rc); | |
1478 | 1588 | break; |
1479 | 1589 | case 0x3C: |
1480 | 1590 | /* CVTQS */ |
1481 | - gen_farith2(&helper_cvtqs, rb, rc); | |
1591 | + gen_fcvtqs(rb, rc); | |
1482 | 1592 | break; |
1483 | 1593 | case 0x3E: |
1484 | 1594 | /* CVTQT */ |
1485 | - gen_farith2(&helper_cvtqt, rb, rc); | |
1595 | + gen_fcvtqt(rb, rc); | |
1486 | 1596 | break; |
1487 | 1597 | default: |
1488 | 1598 | goto invalid_opc; |
... | ... | @@ -1492,7 +1602,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1492 | 1602 | switch (fn11) { |
1493 | 1603 | case 0x010: |
1494 | 1604 | /* CVTLQ */ |
1495 | - gen_farith2(&helper_cvtlq, rb, rc); | |
1605 | + gen_fcvtlq(rb, rc); | |
1496 | 1606 | break; |
1497 | 1607 | case 0x020: |
1498 | 1608 | if (likely(rc != 31)) { |
... | ... | @@ -1501,67 +1611,67 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1501 | 1611 | tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); |
1502 | 1612 | else |
1503 | 1613 | /* CPYS */ |
1504 | - gen_farith3(&helper_cpys, ra, rb, rc); | |
1614 | + gen_fcpys(ra, rb, rc); | |
1505 | 1615 | } |
1506 | 1616 | break; |
1507 | 1617 | case 0x021: |
1508 | 1618 | /* CPYSN */ |
1509 | - gen_farith3(&helper_cpysn, ra, rb, rc); | |
1619 | + gen_fcpysn(ra, rb, rc); | |
1510 | 1620 | break; |
1511 | 1621 | case 0x022: |
1512 | 1622 | /* CPYSE */ |
1513 | - gen_farith3(&helper_cpyse, ra, rb, rc); | |
1623 | + gen_fcpyse(ra, rb, rc); | |
1514 | 1624 | break; |
1515 | 1625 | case 0x024: |
1516 | 1626 | /* MT_FPCR */ |
1517 | 1627 | if (likely(ra != 31)) |
1518 | - tcg_gen_helper_0_1(helper_store_fpcr, cpu_fir[ra]); | |
1628 | + gen_helper_store_fpcr(cpu_fir[ra]); | |
1519 | 1629 | else { |
1520 | 1630 | TCGv tmp = tcg_const_i64(0); |
1521 | - tcg_gen_helper_0_1(helper_store_fpcr, tmp); | |
1631 | + gen_helper_store_fpcr(tmp); | |
1522 | 1632 | tcg_temp_free(tmp); |
1523 | 1633 | } |
1524 | 1634 | break; |
1525 | 1635 | case 0x025: |
1526 | 1636 | /* MF_FPCR */ |
1527 | 1637 | if (likely(ra != 31)) |
1528 | - tcg_gen_helper_1_0(helper_load_fpcr, cpu_fir[ra]); | |
1638 | + gen_helper_load_fpcr(cpu_fir[ra]); | |
1529 | 1639 | break; |
1530 | 1640 | case 0x02A: |
1531 | 1641 | /* FCMOVEQ */ |
1532 | - gen_fcmov(&helper_cmpfeq, ra, rb, rc); | |
1642 | + gen_fcmpfeq(ra, rb, rc); | |
1533 | 1643 | break; |
1534 | 1644 | case 0x02B: |
1535 | 1645 | /* FCMOVNE */ |
1536 | - gen_fcmov(&helper_cmpfne, ra, rb, rc); | |
1646 | + gen_fcmpfne(ra, rb, rc); | |
1537 | 1647 | break; |
1538 | 1648 | case 0x02C: |
1539 | 1649 | /* FCMOVLT */ |
1540 | - gen_fcmov(&helper_cmpflt, ra, rb, rc); | |
1650 | + gen_fcmpflt(ra, rb, rc); | |
1541 | 1651 | break; |
1542 | 1652 | case 0x02D: |
1543 | 1653 | /* FCMOVGE */ |
1544 | - gen_fcmov(&helper_cmpfge, ra, rb, rc); | |
1654 | + gen_fcmpfge(ra, rb, rc); | |
1545 | 1655 | break; |
1546 | 1656 | case 0x02E: |
1547 | 1657 | /* FCMOVLE */ |
1548 | - gen_fcmov(&helper_cmpfle, ra, rb, rc); | |
1658 | + gen_fcmpfle(ra, rb, rc); | |
1549 | 1659 | break; |
1550 | 1660 | case 0x02F: |
1551 | 1661 | /* FCMOVGT */ |
1552 | - gen_fcmov(&helper_cmpfgt, ra, rb, rc); | |
1662 | + gen_fcmpfgt(ra, rb, rc); | |
1553 | 1663 | break; |
1554 | 1664 | case 0x030: |
1555 | 1665 | /* CVTQL */ |
1556 | - gen_farith2(&helper_cvtql, rb, rc); | |
1666 | + gen_fcvtql(rb, rc); | |
1557 | 1667 | break; |
1558 | 1668 | case 0x130: |
1559 | 1669 | /* CVTQL/V */ |
1560 | - gen_farith2(&helper_cvtqlv, rb, rc); | |
1670 | + gen_fcvtqlv(rb, rc); | |
1561 | 1671 | break; |
1562 | 1672 | case 0x530: |
1563 | 1673 | /* CVTQL/SV */ |
1564 | - gen_farith2(&helper_cvtqlsv, rb, rc); | |
1674 | + gen_fcvtqlsv(rb, rc); | |
1565 | 1675 | break; |
1566 | 1676 | default: |
1567 | 1677 | goto invalid_opc; |
... | ... | @@ -1598,12 +1708,12 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1598 | 1708 | case 0xC000: |
1599 | 1709 | /* RPCC */ |
1600 | 1710 | if (ra != 31) |
1601 | - tcg_gen_helper_1_0(helper_load_pcc, cpu_ir[ra]); | |
1711 | + gen_helper_load_pcc(cpu_ir[ra]); | |
1602 | 1712 | break; |
1603 | 1713 | case 0xE000: |
1604 | 1714 | /* RC */ |
1605 | 1715 | if (ra != 31) |
1606 | - tcg_gen_helper_1_0(helper_rc, cpu_ir[ra]); | |
1716 | + gen_helper_rc(cpu_ir[ra]); | |
1607 | 1717 | break; |
1608 | 1718 | case 0xE800: |
1609 | 1719 | /* ECB */ |
... | ... | @@ -1617,7 +1727,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1617 | 1727 | case 0xF000: |
1618 | 1728 | /* RS */ |
1619 | 1729 | if (ra != 31) |
1620 | - tcg_gen_helper_1_0(helper_rs, cpu_ir[ra]); | |
1730 | + gen_helper_rs(cpu_ir[ra]); | |
1621 | 1731 | break; |
1622 | 1732 | case 0xF800: |
1623 | 1733 | /* WH64 */ |
... | ... | @@ -1636,7 +1746,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1636 | 1746 | goto invalid_opc; |
1637 | 1747 | if (ra != 31) { |
1638 | 1748 | TCGv tmp = tcg_const_i32(insn & 0xFF); |
1639 | - tcg_gen_helper_1_2(helper_mfpr, cpu_ir[ra], tmp, cpu_ir[ra]); | |
1749 | + gen_helper_mfpr(cpu_ir[ra], tmp, cpu_ir[ra]); | |
1640 | 1750 | tcg_temp_free(tmp); |
1641 | 1751 | } |
1642 | 1752 | break; |
... | ... | @@ -1673,7 +1783,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1673 | 1783 | if (!ctx->pal_mode) |
1674 | 1784 | goto invalid_opc; |
1675 | 1785 | if (ra != 31) { |
1676 | - TCGv addr = tcg_temp_new(TCG_TYPE_I64); | |
1786 | + TCGv addr = tcg_temp_new(); | |
1677 | 1787 | if (rb != 31) |
1678 | 1788 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
1679 | 1789 | else |
... | ... | @@ -1681,27 +1791,27 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1681 | 1791 | switch ((insn >> 12) & 0xF) { |
1682 | 1792 | case 0x0: |
1683 | 1793 | /* Longword physical access */ |
1684 | - tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr); | |
1794 | + gen_helper_ldl_raw(cpu_ir[ra], addr); | |
1685 | 1795 | break; |
1686 | 1796 | case 0x1: |
1687 | 1797 | /* Quadword physical access */ |
1688 | - tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr); | |
1798 | + gen_helper_ldq_raw(cpu_ir[ra], addr); | |
1689 | 1799 | break; |
1690 | 1800 | case 0x2: |
1691 | 1801 | /* Longword physical access with lock */ |
1692 | - tcg_gen_helper_0_2(helper_ldl_l_raw, cpu_ir[ra], addr); | |
1802 | + gen_helper_ldl_l_raw(cpu_ir[ra], addr); | |
1693 | 1803 | break; |
1694 | 1804 | case 0x3: |
1695 | 1805 | /* Quadword physical access with lock */ |
1696 | - tcg_gen_helper_0_2(helper_ldq_l_raw, cpu_ir[ra], addr); | |
1806 | + gen_helper_ldq_l_raw(cpu_ir[ra], addr); | |
1697 | 1807 | break; |
1698 | 1808 | case 0x4: |
1699 | 1809 | /* Longword virtual PTE fetch */ |
1700 | - tcg_gen_helper_0_2(helper_ldl_kernel, cpu_ir[ra], addr); | |
1810 | + gen_helper_ldl_kernel(cpu_ir[ra], addr); | |
1701 | 1811 | break; |
1702 | 1812 | case 0x5: |
1703 | 1813 | /* Quadword virtual PTE fetch */ |
1704 | - tcg_gen_helper_0_2(helper_ldq_kernel, cpu_ir[ra], addr); | |
1814 | + gen_helper_ldq_kernel(cpu_ir[ra], addr); | |
1705 | 1815 | break; |
1706 | 1816 | case 0x6: |
1707 | 1817 | /* Incpu_ir[ra]id */ |
... | ... | @@ -1711,13 +1821,13 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1711 | 1821 | goto incpu_ir[ra]id_opc; |
1712 | 1822 | case 0x8: |
1713 | 1823 | /* Longword virtual access */ |
1714 | - tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); | |
1715 | - tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr); | |
1824 | + gen_helper_st_virt_to_phys(addr, addr); | |
1825 | + gen_helper_ldl_raw(cpu_ir[ra], addr); | |
1716 | 1826 | break; |
1717 | 1827 | case 0x9: |
1718 | 1828 | /* Quadword virtual access */ |
1719 | - tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); | |
1720 | - tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr); | |
1829 | + gen_helper_st_virt_to_phys(addr, addr); | |
1830 | + gen_helper_ldq_raw(cpu_ir[ra], addr); | |
1721 | 1831 | break; |
1722 | 1832 | case 0xA: |
1723 | 1833 | /* Longword virtual access with protection check */ |
... | ... | @@ -1729,33 +1839,33 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1729 | 1839 | break; |
1730 | 1840 | case 0xC: |
1731 | 1841 | /* Longword virtual access with altenate access mode */ |
1732 | - tcg_gen_helper_0_0(helper_set_alt_mode); | |
1733 | - tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); | |
1734 | - tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr); | |
1735 | - tcg_gen_helper_0_0(helper_restore_mode); | |
1842 | + gen_helper_set_alt_mode(); | |
1843 | + gen_helper_st_virt_to_phys(addr, addr); | |
1844 | + gen_helper_ldl_raw(cpu_ir[ra], addr); | |
1845 | + gen_helper_restore_mode(); | |
1736 | 1846 | break; |
1737 | 1847 | case 0xD: |
1738 | 1848 | /* Quadword virtual access with altenate access mode */ |
1739 | - tcg_gen_helper_0_0(helper_set_alt_mode); | |
1740 | - tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); | |
1741 | - tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr); | |
1742 | - tcg_gen_helper_0_0(helper_restore_mode); | |
1849 | + gen_helper_set_alt_mode(); | |
1850 | + gen_helper_st_virt_to_phys(addr, addr); | |
1851 | + gen_helper_ldq_raw(cpu_ir[ra], addr); | |
1852 | + gen_helper_restore_mode(); | |
1743 | 1853 | break; |
1744 | 1854 | case 0xE: |
1745 | 1855 | /* Longword virtual access with alternate access mode and |
1746 | 1856 | * protection checks |
1747 | 1857 | */ |
1748 | - tcg_gen_helper_0_0(helper_set_alt_mode); | |
1749 | - tcg_gen_helper_0_2(helper_ldl_data, cpu_ir[ra], addr); | |
1750 | - tcg_gen_helper_0_0(helper_restore_mode); | |
1858 | + gen_helper_set_alt_mode(); | |
1859 | + gen_helper_ldl_data(cpu_ir[ra], addr); | |
1860 | + gen_helper_restore_mode(); | |
1751 | 1861 | break; |
1752 | 1862 | case 0xF: |
1753 | 1863 | /* Quadword virtual access with alternate access mode and |
1754 | 1864 | * protection checks |
1755 | 1865 | */ |
1756 | - tcg_gen_helper_0_0(helper_set_alt_mode); | |
1757 | - tcg_gen_helper_0_2(helper_ldq_data, cpu_ir[ra], addr); | |
1758 | - tcg_gen_helper_0_0(helper_restore_mode); | |
1866 | + gen_helper_set_alt_mode(); | |
1867 | + gen_helper_ldq_data(cpu_ir[ra], addr); | |
1868 | + gen_helper_restore_mode(); | |
1759 | 1869 | break; |
1760 | 1870 | } |
1761 | 1871 | tcg_temp_free(addr); |
... | ... | @@ -1794,7 +1904,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1794 | 1904 | if (islit) |
1795 | 1905 | tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit)); |
1796 | 1906 | else |
1797 | - tcg_gen_helper_1_1(helper_ctpop, cpu_ir[rc], cpu_ir[rb]); | |
1907 | + gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]); | |
1798 | 1908 | } |
1799 | 1909 | break; |
1800 | 1910 | case 0x31: |
... | ... | @@ -1812,7 +1922,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1812 | 1922 | if (islit) |
1813 | 1923 | tcg_gen_movi_i64(cpu_ir[rc], clz64(lit)); |
1814 | 1924 | else |
1815 | - tcg_gen_helper_1_1(helper_ctlz, cpu_ir[rc], cpu_ir[rb]); | |
1925 | + gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]); | |
1816 | 1926 | } |
1817 | 1927 | break; |
1818 | 1928 | case 0x33: |
... | ... | @@ -1823,7 +1933,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1823 | 1933 | if (islit) |
1824 | 1934 | tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit)); |
1825 | 1935 | else |
1826 | - tcg_gen_helper_1_1(helper_cttz, cpu_ir[rc], cpu_ir[rb]); | |
1936 | + gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]); | |
1827 | 1937 | } |
1828 | 1938 | break; |
1829 | 1939 | case 0x34: |
... | ... | @@ -1926,16 +2036,16 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1926 | 2036 | if (!(ctx->amask & AMASK_FIX)) |
1927 | 2037 | goto invalid_opc; |
1928 | 2038 | if (rc != 31) { |
1929 | - TCGv tmp1 = tcg_temp_new(TCG_TYPE_I32); | |
2039 | + TCGv_i32 tmp1 = tcg_temp_new_i32(); | |
1930 | 2040 | if (ra != 31) |
1931 | - tcg_gen_helper_1_1(helper_s_to_memory, tmp1, cpu_fir[ra]); | |
2041 | + gen_helper_s_to_memory(tmp1, cpu_fir[ra]); | |
1932 | 2042 | else { |
1933 | 2043 | TCGv tmp2 = tcg_const_i64(0); |
1934 | - tcg_gen_helper_1_1(helper_s_to_memory, tmp1, tmp2); | |
2044 | + gen_helper_s_to_memory(tmp1, tmp2); | |
1935 | 2045 | tcg_temp_free(tmp2); |
1936 | 2046 | } |
1937 | 2047 | tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1); |
1938 | - tcg_temp_free(tmp1); | |
2048 | + tcg_temp_free_i32(tmp1); | |
1939 | 2049 | } |
1940 | 2050 | break; |
1941 | 2051 | default: |
... | ... | @@ -1952,10 +2062,10 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1952 | 2062 | else { |
1953 | 2063 | TCGv tmp1 = tcg_const_i32(insn & 0xFF); |
1954 | 2064 | if (ra != 31) |
1955 | - tcg_gen_helper(helper_mtpr, tmp1, cpu_ir[ra]); | |
2065 | + gen_helper_mtpr(tmp1, cpu_ir[ra]); | |
1956 | 2066 | else { |
1957 | 2067 | TCGv tmp2 = tcg_const_i64(0); |
1958 | - tcg_gen_helper(helper_mtpr, tmp1, tmp2); | |
2068 | + gen_helper_mtpr(tmp1, tmp2); | |
1959 | 2069 | tcg_temp_free(tmp2); |
1960 | 2070 | } |
1961 | 2071 | tcg_temp_free(tmp1); |
... | ... | @@ -1972,16 +2082,16 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1972 | 2082 | goto invalid_opc; |
1973 | 2083 | if (rb == 31) { |
1974 | 2084 | /* "Old" alpha */ |
1975 | - tcg_gen_helper_0_0(helper_hw_rei); | |
2085 | + gen_helper_hw_rei(); | |
1976 | 2086 | } else { |
1977 | 2087 | TCGv tmp; |
1978 | 2088 | |
1979 | 2089 | if (ra != 31) { |
1980 | - tmp = tcg_temp_new(TCG_TYPE_I64); | |
2090 | + tmp = tcg_temp_new(); | |
1981 | 2091 | tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51)); |
1982 | 2092 | } else |
1983 | 2093 | tmp = tcg_const_i64(((int64_t)insn << 51) >> 51); |
1984 | - tcg_gen_helper_0_1(helper_hw_ret, tmp); | |
2094 | + gen_helper_hw_ret(tmp); | |
1985 | 2095 | tcg_temp_free(tmp); |
1986 | 2096 | } |
1987 | 2097 | ret = 2; |
... | ... | @@ -1996,7 +2106,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
1996 | 2106 | goto invalid_opc; |
1997 | 2107 | else { |
1998 | 2108 | TCGv addr, val; |
1999 | - addr = tcg_temp_new(TCG_TYPE_I64); | |
2109 | + addr = tcg_temp_new(); | |
2000 | 2110 | if (rb != 31) |
2001 | 2111 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
2002 | 2112 | else |
... | ... | @@ -2004,35 +2114,35 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
2004 | 2114 | if (ra != 31) |
2005 | 2115 | val = cpu_ir[ra]; |
2006 | 2116 | else { |
2007 | - val = tcg_temp_new(TCG_TYPE_I64); | |
2117 | + val = tcg_temp_new(); | |
2008 | 2118 | tcg_gen_movi_i64(val, 0); |
2009 | 2119 | } |
2010 | 2120 | switch ((insn >> 12) & 0xF) { |
2011 | 2121 | case 0x0: |
2012 | 2122 | /* Longword physical access */ |
2013 | - tcg_gen_helper_0_2(helper_stl_raw, val, addr); | |
2123 | + gen_helper_stl_raw(val, addr); | |
2014 | 2124 | break; |
2015 | 2125 | case 0x1: |
2016 | 2126 | /* Quadword physical access */ |
2017 | - tcg_gen_helper_0_2(helper_stq_raw, val, addr); | |
2127 | + gen_helper_stq_raw(val, addr); | |
2018 | 2128 | break; |
2019 | 2129 | case 0x2: |
2020 | 2130 | /* Longword physical access with lock */ |
2021 | - tcg_gen_helper_1_2(helper_stl_c_raw, val, val, addr); | |
2131 | + gen_helper_stl_c_raw(val, val, addr); | |
2022 | 2132 | break; |
2023 | 2133 | case 0x3: |
2024 | 2134 | /* Quadword physical access with lock */ |
2025 | - tcg_gen_helper_1_2(helper_stq_c_raw, val, val, addr); | |
2135 | + gen_helper_stq_c_raw(val, val, addr); | |
2026 | 2136 | break; |
2027 | 2137 | case 0x4: |
2028 | 2138 | /* Longword virtual access */ |
2029 | - tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); | |
2030 | - tcg_gen_helper_0_2(helper_stl_raw, val, addr); | |
2139 | + gen_helper_st_virt_to_phys(addr, addr); | |
2140 | + gen_helper_stl_raw(val, addr); | |
2031 | 2141 | break; |
2032 | 2142 | case 0x5: |
2033 | 2143 | /* Quadword virtual access */ |
2034 | - tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); | |
2035 | - tcg_gen_helper_0_2(helper_stq_raw, val, addr); | |
2144 | + gen_helper_st_virt_to_phys(addr, addr); | |
2145 | + gen_helper_stq_raw(val, addr); | |
2036 | 2146 | break; |
2037 | 2147 | case 0x6: |
2038 | 2148 | /* Invalid */ |
... | ... | @@ -2054,17 +2164,17 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
2054 | 2164 | goto invalid_opc; |
2055 | 2165 | case 0xC: |
2056 | 2166 | /* Longword virtual access with alternate access mode */ |
2057 | - tcg_gen_helper_0_0(helper_set_alt_mode); | |
2058 | - tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); | |
2059 | - tcg_gen_helper_0_2(helper_stl_raw, val, addr); | |
2060 | - tcg_gen_helper_0_0(helper_restore_mode); | |
2167 | + gen_helper_set_alt_mode(); | |
2168 | + gen_helper_st_virt_to_phys(addr, addr); | |
2169 | + gen_helper_stl_raw(val, addr); | |
2170 | + gen_helper_restore_mode(); | |
2061 | 2171 | break; |
2062 | 2172 | case 0xD: |
2063 | 2173 | /* Quadword virtual access with alternate access mode */ |
2064 | - tcg_gen_helper_0_0(helper_set_alt_mode); | |
2065 | - tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); | |
2066 | - tcg_gen_helper_0_2(helper_stl_raw, val, addr); | |
2067 | - tcg_gen_helper_0_0(helper_restore_mode); | |
2174 | + gen_helper_set_alt_mode(); | |
2175 | + gen_helper_st_virt_to_phys(addr, addr); | |
2176 | + gen_helper_stl_raw(val, addr); | |
2177 | + gen_helper_restore_mode(); | |
2068 | 2178 | break; |
2069 | 2179 | case 0xE: |
2070 | 2180 | /* Invalid */ |
... | ... | @@ -2151,19 +2261,10 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
2151 | 2261 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2)); |
2152 | 2262 | ret = 1; |
2153 | 2263 | break; |
2154 | - case 0x31: | |
2155 | - /* FBEQ */ | |
2156 | - gen_fbcond(ctx, &helper_cmpfeq, ra, disp16); | |
2157 | - ret = 1; | |
2158 | - break; | |
2159 | - case 0x32: | |
2160 | - /* FBLT */ | |
2161 | - gen_fbcond(ctx, &helper_cmpflt, ra, disp16); | |
2162 | - ret = 1; | |
2163 | - break; | |
2164 | - case 0x33: | |
2165 | - /* FBLE */ | |
2166 | - gen_fbcond(ctx, &helper_cmpfle, ra, disp16); | |
2264 | + case 0x31: /* FBEQ */ | |
2265 | + case 0x32: /* FBLT */ | |
2266 | + case 0x33: /* FBLE */ | |
2267 | + gen_fbcond(ctx, opc, ra, disp16); | |
2167 | 2268 | ret = 1; |
2168 | 2269 | break; |
2169 | 2270 | case 0x34: |
... | ... | @@ -2173,19 +2274,10 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
2173 | 2274 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2)); |
2174 | 2275 | ret = 1; |
2175 | 2276 | break; |
2176 | - case 0x35: | |
2177 | - /* FBNE */ | |
2178 | - gen_fbcond(ctx, &helper_cmpfne, ra, disp16); | |
2179 | - ret = 1; | |
2180 | - break; | |
2181 | - case 0x36: | |
2182 | - /* FBGE */ | |
2183 | - gen_fbcond(ctx, &helper_cmpfge, ra, disp16); | |
2184 | - ret = 1; | |
2185 | - break; | |
2186 | - case 0x37: | |
2187 | - /* FBGT */ | |
2188 | - gen_fbcond(ctx, &helper_cmpfgt, ra, disp16); | |
2277 | + case 0x35: /* FBNE */ | |
2278 | + case 0x36: /* FBGE */ | |
2279 | + case 0x37: /* FBGT */ | |
2280 | + gen_fbcond(ctx, opc, ra, disp16); | |
2189 | 2281 | ret = 1; |
2190 | 2282 | break; |
2191 | 2283 | case 0x38: |
... | ... | @@ -2326,7 +2418,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, |
2326 | 2418 | tcg_gen_movi_i64(cpu_pc, ctx.pc); |
2327 | 2419 | } |
2328 | 2420 | #if defined (DO_TB_FLUSH) |
2329 | - tcg_gen_helper_0_0(helper_tb_flush); | |
2421 | + gen_helper_tb_flush(); | |
2330 | 2422 | #endif |
2331 | 2423 | if (tb->cflags & CF_LAST_IO) |
2332 | 2424 | gen_io_end(); | ... | ... |
target-arm/helpers.h
1 | -#define DEF_HELPER(name, ret, args) ret glue(helper_,name) args; | |
2 | - | |
3 | -#ifdef GEN_HELPER | |
4 | -#define DEF_HELPER_0_0(name, ret, args) \ | |
5 | -DEF_HELPER(name, ret, args) \ | |
6 | -static inline void gen_helper_##name(void) \ | |
7 | -{ \ | |
8 | - tcg_gen_helper_0_0(helper_##name); \ | |
9 | -} | |
10 | -#define DEF_HELPER_0_1(name, ret, args) \ | |
11 | -DEF_HELPER(name, ret, args) \ | |
12 | -static inline void gen_helper_##name(TCGv arg1) \ | |
13 | -{ \ | |
14 | - tcg_gen_helper_0_1(helper_##name, arg1); \ | |
15 | -} | |
16 | -#define DEF_HELPER_0_2(name, ret, args) \ | |
17 | -DEF_HELPER(name, ret, args) \ | |
18 | -static inline void gen_helper_##name(TCGv arg1, TCGv arg2) \ | |
19 | -{ \ | |
20 | - tcg_gen_helper_0_2(helper_##name, arg1, arg2); \ | |
21 | -} | |
22 | -#define DEF_HELPER_0_3(name, ret, args) \ | |
23 | -DEF_HELPER(name, ret, args) \ | |
24 | -static inline void gen_helper_##name( \ | |
25 | - TCGv arg1, TCGv arg2, TCGv arg3) \ | |
26 | -{ \ | |
27 | - tcg_gen_helper_0_3(helper_##name, arg1, arg2, arg3); \ | |
28 | -} | |
29 | -#define DEF_HELPER_1_0(name, ret, args) \ | |
30 | -DEF_HELPER(name, ret, args) \ | |
31 | -static inline void gen_helper_##name(TCGv ret) \ | |
32 | -{ \ | |
33 | - tcg_gen_helper_1_0(helper_##name, ret); \ | |
34 | -} | |
35 | -#define DEF_HELPER_1_1(name, ret, args) \ | |
36 | -DEF_HELPER(name, ret, args) \ | |
37 | -static inline void gen_helper_##name(TCGv ret, TCGv arg1) \ | |
38 | -{ \ | |
39 | - tcg_gen_helper_1_1(helper_##name, ret, arg1); \ | |
40 | -} | |
41 | -#define DEF_HELPER_1_2(name, ret, args) \ | |
42 | -DEF_HELPER(name, ret, args) \ | |
43 | -static inline void gen_helper_##name(TCGv ret, TCGv arg1, TCGv arg2) \ | |
44 | -{ \ | |
45 | - tcg_gen_helper_1_2(helper_##name, ret, arg1, arg2); \ | |
46 | -} | |
47 | -#define DEF_HELPER_1_3(name, ret, args) \ | |
48 | -DEF_HELPER(name, ret, args) \ | |
49 | -static inline void gen_helper_##name(TCGv ret, \ | |
50 | - TCGv arg1, TCGv arg2, TCGv arg3) \ | |
51 | -{ \ | |
52 | - tcg_gen_helper_1_3(helper_##name, ret, arg1, arg2, arg3); \ | |
53 | -} | |
54 | -#define DEF_HELPER_1_4(name, ret, args) \ | |
55 | -DEF_HELPER(name, ret, args) \ | |
56 | -static inline void gen_helper_##name(TCGv ret, \ | |
57 | - TCGv arg1, TCGv arg2, TCGv arg3, TCGv arg4) \ | |
58 | -{ \ | |
59 | - tcg_gen_helper_1_4(helper_##name, ret, arg1, arg2, arg3, arg4); \ | |
60 | -} | |
61 | -#else /* !GEN_HELPER */ | |
62 | -#define DEF_HELPER_0_0 DEF_HELPER | |
63 | -#define DEF_HELPER_0_1 DEF_HELPER | |
64 | -#define DEF_HELPER_0_2 DEF_HELPER | |
65 | -#define DEF_HELPER_0_3 DEF_HELPER | |
66 | -#define DEF_HELPER_1_0 DEF_HELPER | |
67 | -#define DEF_HELPER_1_1 DEF_HELPER | |
68 | -#define DEF_HELPER_1_2 DEF_HELPER | |
69 | -#define DEF_HELPER_1_3 DEF_HELPER | |
70 | -#define DEF_HELPER_1_4 DEF_HELPER | |
71 | -#define HELPER(x) glue(helper_,x) | |
72 | -#endif | |
73 | - | |
74 | -DEF_HELPER_1_1(clz, uint32_t, (uint32_t)) | |
75 | -DEF_HELPER_1_1(sxtb16, uint32_t, (uint32_t)) | |
76 | -DEF_HELPER_1_1(uxtb16, uint32_t, (uint32_t)) | |
77 | - | |
78 | -DEF_HELPER_1_2(add_setq, uint32_t, (uint32_t, uint32_t)) | |
79 | -DEF_HELPER_1_2(add_saturate, uint32_t, (uint32_t, uint32_t)) | |
80 | -DEF_HELPER_1_2(sub_saturate, uint32_t, (uint32_t, uint32_t)) | |
81 | -DEF_HELPER_1_2(add_usaturate, uint32_t, (uint32_t, uint32_t)) | |
82 | -DEF_HELPER_1_2(sub_usaturate, uint32_t, (uint32_t, uint32_t)) | |
83 | -DEF_HELPER_1_1(double_saturate, uint32_t, (int32_t)) | |
84 | -DEF_HELPER_1_2(sdiv, int32_t, (int32_t, int32_t)) | |
85 | -DEF_HELPER_1_2(udiv, uint32_t, (uint32_t, uint32_t)) | |
86 | -DEF_HELPER_1_1(rbit, uint32_t, (uint32_t)) | |
87 | -DEF_HELPER_1_1(abs, uint32_t, (uint32_t)) | |
1 | +#include "def-helper.h" | |
2 | + | |
3 | +DEF_HELPER_1(clz, i32, i32) | |
4 | +DEF_HELPER_1(sxtb16, i32, i32) | |
5 | +DEF_HELPER_1(uxtb16, i32, i32) | |
6 | + | |
7 | +DEF_HELPER_2(add_setq, i32, i32, i32) | |
8 | +DEF_HELPER_2(add_saturate, i32, i32, i32) | |
9 | +DEF_HELPER_2(sub_saturate, i32, i32, i32) | |
10 | +DEF_HELPER_2(add_usaturate, i32, i32, i32) | |
11 | +DEF_HELPER_2(sub_usaturate, i32, i32, i32) | |
12 | +DEF_HELPER_1(double_saturate, i32, s32) | |
13 | +DEF_HELPER_2(sdiv, s32, s32, s32) | |
14 | +DEF_HELPER_2(udiv, i32, i32, i32) | |
15 | +DEF_HELPER_1(rbit, i32, i32) | |
16 | +DEF_HELPER_1(abs, i32, i32) | |
88 | 17 | |
89 | 18 | #define PAS_OP(pfx) \ |
90 | - DEF_HELPER_1_3(pfx ## add8, uint32_t, (uint32_t, uint32_t, uint32_t *)) \ | |
91 | - DEF_HELPER_1_3(pfx ## sub8, uint32_t, (uint32_t, uint32_t, uint32_t *)) \ | |
92 | - DEF_HELPER_1_3(pfx ## sub16, uint32_t, (uint32_t, uint32_t, uint32_t *)) \ | |
93 | - DEF_HELPER_1_3(pfx ## add16, uint32_t, (uint32_t, uint32_t, uint32_t *)) \ | |
94 | - DEF_HELPER_1_3(pfx ## addsubx, uint32_t, (uint32_t, uint32_t, uint32_t *)) \ | |
95 | - DEF_HELPER_1_3(pfx ## subaddx, uint32_t, (uint32_t, uint32_t, uint32_t *)) | |
19 | + DEF_HELPER_3(pfx ## add8, i32, i32, i32, ptr) \ | |
20 | + DEF_HELPER_3(pfx ## sub8, i32, i32, i32, ptr) \ | |
21 | + DEF_HELPER_3(pfx ## sub16, i32, i32, i32, ptr) \ | |
22 | + DEF_HELPER_3(pfx ## add16, i32, i32, i32, ptr) \ | |
23 | + DEF_HELPER_3(pfx ## addsubx, i32, i32, i32, ptr) \ | |
24 | + DEF_HELPER_3(pfx ## subaddx, i32, i32, i32, ptr) | |
96 | 25 | |
97 | 26 | PAS_OP(s) |
98 | 27 | PAS_OP(u) |
99 | 28 | #undef PAS_OP |
100 | 29 | |
101 | 30 | #define PAS_OP(pfx) \ |
102 | - DEF_HELPER_1_2(pfx ## add8, uint32_t, (uint32_t, uint32_t)) \ | |
103 | - DEF_HELPER_1_2(pfx ## sub8, uint32_t, (uint32_t, uint32_t)) \ | |
104 | - DEF_HELPER_1_2(pfx ## sub16, uint32_t, (uint32_t, uint32_t)) \ | |
105 | - DEF_HELPER_1_2(pfx ## add16, uint32_t, (uint32_t, uint32_t)) \ | |
106 | - DEF_HELPER_1_2(pfx ## addsubx, uint32_t, (uint32_t, uint32_t)) \ | |
107 | - DEF_HELPER_1_2(pfx ## subaddx, uint32_t, (uint32_t, uint32_t)) | |
31 | + DEF_HELPER_2(pfx ## add8, i32, i32, i32) \ | |
32 | + DEF_HELPER_2(pfx ## sub8, i32, i32, i32) \ | |
33 | + DEF_HELPER_2(pfx ## sub16, i32, i32, i32) \ | |
34 | + DEF_HELPER_2(pfx ## add16, i32, i32, i32) \ | |
35 | + DEF_HELPER_2(pfx ## addsubx, i32, i32, i32) \ | |
36 | + DEF_HELPER_2(pfx ## subaddx, i32, i32, i32) | |
108 | 37 | PAS_OP(q) |
109 | 38 | PAS_OP(sh) |
110 | 39 | PAS_OP(uq) |
111 | 40 | PAS_OP(uh) |
112 | 41 | #undef PAS_OP |
113 | 42 | |
114 | -DEF_HELPER_1_2(ssat, uint32_t, (uint32_t, uint32_t)) | |
115 | -DEF_HELPER_1_2(usat, uint32_t, (uint32_t, uint32_t)) | |
116 | -DEF_HELPER_1_2(ssat16, uint32_t, (uint32_t, uint32_t)) | |
117 | -DEF_HELPER_1_2(usat16, uint32_t, (uint32_t, uint32_t)) | |
118 | - | |
119 | -DEF_HELPER_1_2(usad8, uint32_t, (uint32_t, uint32_t)) | |
120 | - | |
121 | -DEF_HELPER_1_1(logicq_cc, uint32_t, (uint64_t)) | |
122 | - | |
123 | -DEF_HELPER_1_3(sel_flags, uint32_t, (uint32_t, uint32_t, uint32_t)) | |
124 | -DEF_HELPER_0_1(exception, void, (uint32_t)) | |
125 | -DEF_HELPER_0_0(wfi, void, (void)) | |
126 | - | |
127 | -DEF_HELPER_0_2(cpsr_write, void, (uint32_t, uint32_t)) | |
128 | -DEF_HELPER_1_0(cpsr_read, uint32_t, (void)) | |
129 | - | |
130 | -DEF_HELPER_0_3(v7m_msr, void, (CPUState *, uint32_t, uint32_t)) | |
131 | -DEF_HELPER_1_2(v7m_mrs, uint32_t, (CPUState *, uint32_t)) | |
132 | - | |
133 | -DEF_HELPER_0_3(set_cp15, void, (CPUState *, uint32_t, uint32_t)) | |
134 | -DEF_HELPER_1_2(get_cp15, uint32_t, (CPUState *, uint32_t)) | |
135 | - | |
136 | -DEF_HELPER_0_3(set_cp, void, (CPUState *, uint32_t, uint32_t)) | |
137 | -DEF_HELPER_1_2(get_cp, uint32_t, (CPUState *, uint32_t)) | |
138 | - | |
139 | -DEF_HELPER_1_2(get_r13_banked, uint32_t, (CPUState *, uint32_t)) | |
140 | -DEF_HELPER_0_3(set_r13_banked, void, (CPUState *, uint32_t, uint32_t)) | |
141 | - | |
142 | -DEF_HELPER_0_2(mark_exclusive, void, (CPUState *, uint32_t)) | |
143 | -DEF_HELPER_1_2(test_exclusive, uint32_t, (CPUState *, uint32_t)) | |
144 | -DEF_HELPER_0_1(clrex, void, (CPUState *)) | |
145 | - | |
146 | -DEF_HELPER_1_1(get_user_reg, uint32_t, (uint32_t)) | |
147 | -DEF_HELPER_0_2(set_user_reg, void, (uint32_t, uint32_t)) | |
148 | - | |
149 | -DEF_HELPER_1_1(vfp_get_fpscr, uint32_t, (CPUState *)) | |
150 | -DEF_HELPER_0_2(vfp_set_fpscr, void, (CPUState *, uint32_t)) | |
151 | - | |
152 | -DEF_HELPER_1_3(vfp_adds, float32, (float32, float32, CPUState *)) | |
153 | -DEF_HELPER_1_3(vfp_addd, float64, (float64, float64, CPUState *)) | |
154 | -DEF_HELPER_1_3(vfp_subs, float32, (float32, float32, CPUState *)) | |
155 | -DEF_HELPER_1_3(vfp_subd, float64, (float64, float64, CPUState *)) | |
156 | -DEF_HELPER_1_3(vfp_muls, float32, (float32, float32, CPUState *)) | |
157 | -DEF_HELPER_1_3(vfp_muld, float64, (float64, float64, CPUState *)) | |
158 | -DEF_HELPER_1_3(vfp_divs, float32, (float32, float32, CPUState *)) | |
159 | -DEF_HELPER_1_3(vfp_divd, float64, (float64, float64, CPUState *)) | |
160 | -DEF_HELPER_1_1(vfp_negs, float32, (float32)) | |
161 | -DEF_HELPER_1_1(vfp_negd, float64, (float64)) | |
162 | -DEF_HELPER_1_1(vfp_abss, float32, (float32)) | |
163 | -DEF_HELPER_1_1(vfp_absd, float64, (float64)) | |
164 | -DEF_HELPER_1_2(vfp_sqrts, float32, (float32, CPUState *)) | |
165 | -DEF_HELPER_1_2(vfp_sqrtd, float64, (float64, CPUState *)) | |
166 | -DEF_HELPER_0_3(vfp_cmps, void, (float32, float32, CPUState *)) | |
167 | -DEF_HELPER_0_3(vfp_cmpd, void, (float64, float64, CPUState *)) | |
168 | -DEF_HELPER_0_3(vfp_cmpes, void, (float32, float32, CPUState *)) | |
169 | -DEF_HELPER_0_3(vfp_cmped, void, (float64, float64, CPUState *)) | |
170 | - | |
171 | -DEF_HELPER_1_2(vfp_fcvtds, float64, (float32, CPUState *)) | |
172 | -DEF_HELPER_1_2(vfp_fcvtsd, float32, (float64, CPUState *)) | |
173 | - | |
174 | -DEF_HELPER_1_2(vfp_uitos, float32, (float32, CPUState *)) | |
175 | -DEF_HELPER_1_2(vfp_uitod, float64, (float32, CPUState *)) | |
176 | -DEF_HELPER_1_2(vfp_sitos, float32, (float32, CPUState *)) | |
177 | -DEF_HELPER_1_2(vfp_sitod, float64, (float32, CPUState *)) | |
178 | - | |
179 | -DEF_HELPER_1_2(vfp_touis, float32, (float32, CPUState *)) | |
180 | -DEF_HELPER_1_2(vfp_touid, float32, (float64, CPUState *)) | |
181 | -DEF_HELPER_1_2(vfp_touizs, float32, (float32, CPUState *)) | |
182 | -DEF_HELPER_1_2(vfp_touizd, float32, (float64, CPUState *)) | |
183 | -DEF_HELPER_1_2(vfp_tosis, float32, (float32, CPUState *)) | |
184 | -DEF_HELPER_1_2(vfp_tosid, float32, (float64, CPUState *)) | |
185 | -DEF_HELPER_1_2(vfp_tosizs, float32, (float32, CPUState *)) | |
186 | -DEF_HELPER_1_2(vfp_tosizd, float32, (float64, CPUState *)) | |
187 | - | |
188 | -DEF_HELPER_1_3(vfp_toshs, float32, (float32, uint32_t, CPUState *)) | |
189 | -DEF_HELPER_1_3(vfp_tosls, float32, (float32, uint32_t, CPUState *)) | |
190 | -DEF_HELPER_1_3(vfp_touhs, float32, (float32, uint32_t, CPUState *)) | |
191 | -DEF_HELPER_1_3(vfp_touls, float32, (float32, uint32_t, CPUState *)) | |
192 | -DEF_HELPER_1_3(vfp_toshd, float64, (float64, uint32_t, CPUState *)) | |
193 | -DEF_HELPER_1_3(vfp_tosld, float64, (float64, uint32_t, CPUState *)) | |
194 | -DEF_HELPER_1_3(vfp_touhd, float64, (float64, uint32_t, CPUState *)) | |
195 | -DEF_HELPER_1_3(vfp_tould, float64, (float64, uint32_t, CPUState *)) | |
196 | -DEF_HELPER_1_3(vfp_shtos, float32, (float32, uint32_t, CPUState *)) | |
197 | -DEF_HELPER_1_3(vfp_sltos, float32, (float32, uint32_t, CPUState *)) | |
198 | -DEF_HELPER_1_3(vfp_uhtos, float32, (float32, uint32_t, CPUState *)) | |
199 | -DEF_HELPER_1_3(vfp_ultos, float32, (float32, uint32_t, CPUState *)) | |
200 | -DEF_HELPER_1_3(vfp_shtod, float64, (float64, uint32_t, CPUState *)) | |
201 | -DEF_HELPER_1_3(vfp_sltod, float64, (float64, uint32_t, CPUState *)) | |
202 | -DEF_HELPER_1_3(vfp_uhtod, float64, (float64, uint32_t, CPUState *)) | |
203 | -DEF_HELPER_1_3(vfp_ultod, float64, (float64, uint32_t, CPUState *)) | |
204 | - | |
205 | -DEF_HELPER_1_3(recps_f32, float32, (float32, float32, CPUState *)) | |
206 | -DEF_HELPER_1_3(rsqrts_f32, float32, (float32, float32, CPUState *)) | |
207 | -DEF_HELPER_1_2(recpe_f32, float32, (float32, CPUState *)) | |
208 | -DEF_HELPER_1_2(rsqrte_f32, float32, (float32, CPUState *)) | |
209 | -DEF_HELPER_1_2(recpe_u32, uint32_t, (uint32_t, CPUState *)) | |
210 | -DEF_HELPER_1_2(rsqrte_u32, uint32_t, (uint32_t, CPUState *)) | |
211 | -DEF_HELPER_1_4(neon_tbl, uint32_t, (uint32_t, uint32_t, uint32_t, uint32_t)) | |
212 | -DEF_HELPER_1_2(neon_add_saturate_u64, uint64_t, (uint64_t, uint64_t)) | |
213 | -DEF_HELPER_1_2(neon_add_saturate_s64, uint64_t, (uint64_t, uint64_t)) | |
214 | -DEF_HELPER_1_2(neon_sub_saturate_u64, uint64_t, (uint64_t, uint64_t)) | |
215 | -DEF_HELPER_1_2(neon_sub_saturate_s64, uint64_t, (uint64_t, uint64_t)) | |
216 | - | |
217 | -DEF_HELPER_1_2(add_cc, uint32_t, (uint32_t, uint32_t)) | |
218 | -DEF_HELPER_1_2(adc_cc, uint32_t, (uint32_t, uint32_t)) | |
219 | -DEF_HELPER_1_2(sub_cc, uint32_t, (uint32_t, uint32_t)) | |
220 | -DEF_HELPER_1_2(sbc_cc, uint32_t, (uint32_t, uint32_t)) | |
221 | - | |
222 | -DEF_HELPER_1_2(shl, uint32_t, (uint32_t, uint32_t)) | |
223 | -DEF_HELPER_1_2(shr, uint32_t, (uint32_t, uint32_t)) | |
224 | -DEF_HELPER_1_2(sar, uint32_t, (uint32_t, uint32_t)) | |
225 | -DEF_HELPER_1_2(ror, uint32_t, (uint32_t, uint32_t)) | |
226 | -DEF_HELPER_1_2(shl_cc, uint32_t, (uint32_t, uint32_t)) | |
227 | -DEF_HELPER_1_2(shr_cc, uint32_t, (uint32_t, uint32_t)) | |
228 | -DEF_HELPER_1_2(sar_cc, uint32_t, (uint32_t, uint32_t)) | |
229 | -DEF_HELPER_1_2(ror_cc, uint32_t, (uint32_t, uint32_t)) | |
43 | +DEF_HELPER_2(ssat, i32, i32, i32) | |
44 | +DEF_HELPER_2(usat, i32, i32, i32) | |
45 | +DEF_HELPER_2(ssat16, i32, i32, i32) | |
46 | +DEF_HELPER_2(usat16, i32, i32, i32) | |
47 | + | |
48 | +DEF_HELPER_2(usad8, i32, i32, i32) | |
49 | + | |
50 | +DEF_HELPER_1(logicq_cc, i32, i64) | |
51 | + | |
52 | +DEF_HELPER_3(sel_flags, i32, i32, i32, i32) | |
53 | +DEF_HELPER_1(exception, void, i32) | |
54 | +DEF_HELPER_0(wfi, void) | |
55 | + | |
56 | +DEF_HELPER_2(cpsr_write, void, i32, i32) | |
57 | +DEF_HELPER_0(cpsr_read, i32) | |
58 | + | |
59 | +DEF_HELPER_3(v7m_msr, void, env, i32, i32) | |
60 | +DEF_HELPER_2(v7m_mrs, i32, env, i32) | |
61 | + | |
62 | +DEF_HELPER_3(set_cp15, void, env, i32, i32) | |
63 | +DEF_HELPER_2(get_cp15, i32, env, i32) | |
64 | + | |
65 | +DEF_HELPER_3(set_cp, void, env, i32, i32) | |
66 | +DEF_HELPER_2(get_cp, i32, env, i32) | |
67 | + | |
68 | +DEF_HELPER_2(get_r13_banked, i32, env, i32) | |
69 | +DEF_HELPER_3(set_r13_banked, void, env, i32, i32) | |
70 | + | |
71 | +DEF_HELPER_2(mark_exclusive, void, env, i32) | |
72 | +DEF_HELPER_2(test_exclusive, i32, env, i32) | |
73 | +DEF_HELPER_1(clrex, void, env) | |
74 | + | |
75 | +DEF_HELPER_1(get_user_reg, i32, i32) | |
76 | +DEF_HELPER_2(set_user_reg, void, i32, i32) | |
77 | + | |
78 | +DEF_HELPER_1(vfp_get_fpscr, i32, env) | |
79 | +DEF_HELPER_2(vfp_set_fpscr, void, env, i32) | |
80 | + | |
81 | +DEF_HELPER_3(vfp_adds, f32, f32, f32, env) | |
82 | +DEF_HELPER_3(vfp_addd, f64, f64, f64, env) | |
83 | +DEF_HELPER_3(vfp_subs, f32, f32, f32, env) | |
84 | +DEF_HELPER_3(vfp_subd, f64, f64, f64, env) | |
85 | +DEF_HELPER_3(vfp_muls, f32, f32, f32, env) | |
86 | +DEF_HELPER_3(vfp_muld, f64, f64, f64, env) | |
87 | +DEF_HELPER_3(vfp_divs, f32, f32, f32, env) | |
88 | +DEF_HELPER_3(vfp_divd, f64, f64, f64, env) | |
89 | +DEF_HELPER_1(vfp_negs, f32, f32) | |
90 | +DEF_HELPER_1(vfp_negd, f64, f64) | |
91 | +DEF_HELPER_1(vfp_abss, f32, f32) | |
92 | +DEF_HELPER_1(vfp_absd, f64, f64) | |
93 | +DEF_HELPER_2(vfp_sqrts, f32, f32, env) | |
94 | +DEF_HELPER_2(vfp_sqrtd, f64, f64, env) | |
95 | +DEF_HELPER_3(vfp_cmps, void, f32, f32, env) | |
96 | +DEF_HELPER_3(vfp_cmpd, void, f64, f64, env) | |
97 | +DEF_HELPER_3(vfp_cmpes, void, f32, f32, env) | |
98 | +DEF_HELPER_3(vfp_cmped, void, f64, f64, env) | |
99 | + | |
100 | +DEF_HELPER_2(vfp_fcvtds, f64, f32, env) | |
101 | +DEF_HELPER_2(vfp_fcvtsd, f32, f64, env) | |
102 | + | |
103 | +DEF_HELPER_2(vfp_uitos, f32, f32, env) | |
104 | +DEF_HELPER_2(vfp_uitod, f64, f32, env) | |
105 | +DEF_HELPER_2(vfp_sitos, f32, f32, env) | |
106 | +DEF_HELPER_2(vfp_sitod, f64, f32, env) | |
107 | + | |
108 | +DEF_HELPER_2(vfp_touis, f32, f32, env) | |
109 | +DEF_HELPER_2(vfp_touid, f32, f64, env) | |
110 | +DEF_HELPER_2(vfp_touizs, f32, f32, env) | |
111 | +DEF_HELPER_2(vfp_touizd, f32, f64, env) | |
112 | +DEF_HELPER_2(vfp_tosis, f32, f32, env) | |
113 | +DEF_HELPER_2(vfp_tosid, f32, f64, env) | |
114 | +DEF_HELPER_2(vfp_tosizs, f32, f32, env) | |
115 | +DEF_HELPER_2(vfp_tosizd, f32, f64, env) | |
116 | + | |
117 | +DEF_HELPER_3(vfp_toshs, f32, f32, i32, env) | |
118 | +DEF_HELPER_3(vfp_tosls, f32, f32, i32, env) | |
119 | +DEF_HELPER_3(vfp_touhs, f32, f32, i32, env) | |
120 | +DEF_HELPER_3(vfp_touls, f32, f32, i32, env) | |
121 | +DEF_HELPER_3(vfp_toshd, f64, f64, i32, env) | |
122 | +DEF_HELPER_3(vfp_tosld, f64, f64, i32, env) | |
123 | +DEF_HELPER_3(vfp_touhd, f64, f64, i32, env) | |
124 | +DEF_HELPER_3(vfp_tould, f64, f64, i32, env) | |
125 | +DEF_HELPER_3(vfp_shtos, f32, f32, i32, env) | |
126 | +DEF_HELPER_3(vfp_sltos, f32, f32, i32, env) | |
127 | +DEF_HELPER_3(vfp_uhtos, f32, f32, i32, env) | |
128 | +DEF_HELPER_3(vfp_ultos, f32, f32, i32, env) | |
129 | +DEF_HELPER_3(vfp_shtod, f64, f64, i32, env) | |
130 | +DEF_HELPER_3(vfp_sltod, f64, f64, i32, env) | |
131 | +DEF_HELPER_3(vfp_uhtod, f64, f64, i32, env) | |
132 | +DEF_HELPER_3(vfp_ultod, f64, f64, i32, env) | |
133 | + | |
134 | +DEF_HELPER_3(recps_f32, f32, f32, f32, env) | |
135 | +DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env) | |
136 | +DEF_HELPER_2(recpe_f32, f32, f32, env) | |
137 | +DEF_HELPER_2(rsqrte_f32, f32, f32, env) | |
138 | +DEF_HELPER_2(recpe_u32, i32, i32, env) | |
139 | +DEF_HELPER_2(rsqrte_u32, i32, i32, env) | |
140 | +DEF_HELPER_4(neon_tbl, i32, i32, i32, i32, i32) | |
141 | +DEF_HELPER_2(neon_add_saturate_u64, i64, i64, i64) | |
142 | +DEF_HELPER_2(neon_add_saturate_s64, i64, i64, i64) | |
143 | +DEF_HELPER_2(neon_sub_saturate_u64, i64, i64, i64) | |
144 | +DEF_HELPER_2(neon_sub_saturate_s64, i64, i64, i64) | |
145 | + | |
146 | +DEF_HELPER_2(add_cc, i32, i32, i32) | |
147 | +DEF_HELPER_2(adc_cc, i32, i32, i32) | |
148 | +DEF_HELPER_2(sub_cc, i32, i32, i32) | |
149 | +DEF_HELPER_2(sbc_cc, i32, i32, i32) | |
150 | + | |
151 | +DEF_HELPER_2(shl, i32, i32, i32) | |
152 | +DEF_HELPER_2(shr, i32, i32, i32) | |
153 | +DEF_HELPER_2(sar, i32, i32, i32) | |
154 | +DEF_HELPER_2(ror, i32, i32, i32) | |
155 | +DEF_HELPER_2(shl_cc, i32, i32, i32) | |
156 | +DEF_HELPER_2(shr_cc, i32, i32, i32) | |
157 | +DEF_HELPER_2(sar_cc, i32, i32, i32) | |
158 | +DEF_HELPER_2(ror_cc, i32, i32, i32) | |
230 | 159 | |
231 | 160 | /* neon_helper.c */ |
232 | -DEF_HELPER_1_3(neon_qadd_u8, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
233 | -DEF_HELPER_1_3(neon_qadd_s8, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
234 | -DEF_HELPER_1_3(neon_qadd_u16, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
235 | -DEF_HELPER_1_3(neon_qadd_s16, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
236 | -DEF_HELPER_1_3(neon_qsub_u8, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
237 | -DEF_HELPER_1_3(neon_qsub_s8, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
238 | -DEF_HELPER_1_3(neon_qsub_u16, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
239 | -DEF_HELPER_1_3(neon_qsub_s16, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
240 | - | |
241 | -DEF_HELPER_1_2(neon_hadd_s8, uint32_t, (uint32_t, uint32_t)) | |
242 | -DEF_HELPER_1_2(neon_hadd_u8, uint32_t, (uint32_t, uint32_t)) | |
243 | -DEF_HELPER_1_2(neon_hadd_s16, uint32_t, (uint32_t, uint32_t)) | |
244 | -DEF_HELPER_1_2(neon_hadd_u16, uint32_t, (uint32_t, uint32_t)) | |
245 | -DEF_HELPER_1_2(neon_hadd_s32, int32_t, (int32_t, int32_t)) | |
246 | -DEF_HELPER_1_2(neon_hadd_u32, uint32_t, (uint32_t, uint32_t)) | |
247 | -DEF_HELPER_1_2(neon_rhadd_s8, uint32_t, (uint32_t, uint32_t)) | |
248 | -DEF_HELPER_1_2(neon_rhadd_u8, uint32_t, (uint32_t, uint32_t)) | |
249 | -DEF_HELPER_1_2(neon_rhadd_s16, uint32_t, (uint32_t, uint32_t)) | |
250 | -DEF_HELPER_1_2(neon_rhadd_u16, uint32_t, (uint32_t, uint32_t)) | |
251 | -DEF_HELPER_1_2(neon_rhadd_s32, int32_t, (int32_t, int32_t)) | |
252 | -DEF_HELPER_1_2(neon_rhadd_u32, uint32_t, (uint32_t, uint32_t)) | |
253 | -DEF_HELPER_1_2(neon_hsub_s8, uint32_t, (uint32_t, uint32_t)) | |
254 | -DEF_HELPER_1_2(neon_hsub_u8, uint32_t, (uint32_t, uint32_t)) | |
255 | -DEF_HELPER_1_2(neon_hsub_s16, uint32_t, (uint32_t, uint32_t)) | |
256 | -DEF_HELPER_1_2(neon_hsub_u16, uint32_t, (uint32_t, uint32_t)) | |
257 | -DEF_HELPER_1_2(neon_hsub_s32, int32_t, (int32_t, int32_t)) | |
258 | -DEF_HELPER_1_2(neon_hsub_u32, uint32_t, (uint32_t, uint32_t)) | |
259 | - | |
260 | -DEF_HELPER_1_2(neon_cgt_u8, uint32_t, (uint32_t, uint32_t)) | |
261 | -DEF_HELPER_1_2(neon_cgt_s8, uint32_t, (uint32_t, uint32_t)) | |
262 | -DEF_HELPER_1_2(neon_cgt_u16, uint32_t, (uint32_t, uint32_t)) | |
263 | -DEF_HELPER_1_2(neon_cgt_s16, uint32_t, (uint32_t, uint32_t)) | |
264 | -DEF_HELPER_1_2(neon_cgt_u32, uint32_t, (uint32_t, uint32_t)) | |
265 | -DEF_HELPER_1_2(neon_cgt_s32, uint32_t, (uint32_t, uint32_t)) | |
266 | -DEF_HELPER_1_2(neon_cge_u8, uint32_t, (uint32_t, uint32_t)) | |
267 | -DEF_HELPER_1_2(neon_cge_s8, uint32_t, (uint32_t, uint32_t)) | |
268 | -DEF_HELPER_1_2(neon_cge_u16, uint32_t, (uint32_t, uint32_t)) | |
269 | -DEF_HELPER_1_2(neon_cge_s16, uint32_t, (uint32_t, uint32_t)) | |
270 | -DEF_HELPER_1_2(neon_cge_u32, uint32_t, (uint32_t, uint32_t)) | |
271 | -DEF_HELPER_1_2(neon_cge_s32, uint32_t, (uint32_t, uint32_t)) | |
272 | - | |
273 | -DEF_HELPER_1_2(neon_min_u8, uint32_t, (uint32_t, uint32_t)) | |
274 | -DEF_HELPER_1_2(neon_min_s8, uint32_t, (uint32_t, uint32_t)) | |
275 | -DEF_HELPER_1_2(neon_min_u16, uint32_t, (uint32_t, uint32_t)) | |
276 | -DEF_HELPER_1_2(neon_min_s16, uint32_t, (uint32_t, uint32_t)) | |
277 | -DEF_HELPER_1_2(neon_min_u32, uint32_t, (uint32_t, uint32_t)) | |
278 | -DEF_HELPER_1_2(neon_min_s32, uint32_t, (uint32_t, uint32_t)) | |
279 | -DEF_HELPER_1_2(neon_max_u8, uint32_t, (uint32_t, uint32_t)) | |
280 | -DEF_HELPER_1_2(neon_max_s8, uint32_t, (uint32_t, uint32_t)) | |
281 | -DEF_HELPER_1_2(neon_max_u16, uint32_t, (uint32_t, uint32_t)) | |
282 | -DEF_HELPER_1_2(neon_max_s16, uint32_t, (uint32_t, uint32_t)) | |
283 | -DEF_HELPER_1_2(neon_max_u32, uint32_t, (uint32_t, uint32_t)) | |
284 | -DEF_HELPER_1_2(neon_max_s32, uint32_t, (uint32_t, uint32_t)) | |
285 | -DEF_HELPER_1_2(neon_pmin_u8, uint32_t, (uint32_t, uint32_t)) | |
286 | -DEF_HELPER_1_2(neon_pmin_s8, uint32_t, (uint32_t, uint32_t)) | |
287 | -DEF_HELPER_1_2(neon_pmin_u16, uint32_t, (uint32_t, uint32_t)) | |
288 | -DEF_HELPER_1_2(neon_pmin_s16, uint32_t, (uint32_t, uint32_t)) | |
289 | -DEF_HELPER_1_2(neon_pmin_u32, uint32_t, (uint32_t, uint32_t)) | |
290 | -DEF_HELPER_1_2(neon_pmin_s32, uint32_t, (uint32_t, uint32_t)) | |
291 | -DEF_HELPER_1_2(neon_pmax_u8, uint32_t, (uint32_t, uint32_t)) | |
292 | -DEF_HELPER_1_2(neon_pmax_s8, uint32_t, (uint32_t, uint32_t)) | |
293 | -DEF_HELPER_1_2(neon_pmax_u16, uint32_t, (uint32_t, uint32_t)) | |
294 | -DEF_HELPER_1_2(neon_pmax_s16, uint32_t, (uint32_t, uint32_t)) | |
295 | -DEF_HELPER_1_2(neon_pmax_u32, uint32_t, (uint32_t, uint32_t)) | |
296 | -DEF_HELPER_1_2(neon_pmax_s32, uint32_t, (uint32_t, uint32_t)) | |
297 | - | |
298 | -DEF_HELPER_1_2(neon_abd_u8, uint32_t, (uint32_t, uint32_t)) | |
299 | -DEF_HELPER_1_2(neon_abd_s8, uint32_t, (uint32_t, uint32_t)) | |
300 | -DEF_HELPER_1_2(neon_abd_u16, uint32_t, (uint32_t, uint32_t)) | |
301 | -DEF_HELPER_1_2(neon_abd_s16, uint32_t, (uint32_t, uint32_t)) | |
302 | -DEF_HELPER_1_2(neon_abd_u32, uint32_t, (uint32_t, uint32_t)) | |
303 | -DEF_HELPER_1_2(neon_abd_s32, uint32_t, (uint32_t, uint32_t)) | |
304 | - | |
305 | -DEF_HELPER_1_2(neon_shl_u8, uint32_t, (uint32_t, uint32_t)) | |
306 | -DEF_HELPER_1_2(neon_shl_s8, uint32_t, (uint32_t, uint32_t)) | |
307 | -DEF_HELPER_1_2(neon_shl_u16, uint32_t, (uint32_t, uint32_t)) | |
308 | -DEF_HELPER_1_2(neon_shl_s16, uint32_t, (uint32_t, uint32_t)) | |
309 | -DEF_HELPER_1_2(neon_shl_u32, uint32_t, (uint32_t, uint32_t)) | |
310 | -DEF_HELPER_1_2(neon_shl_s32, uint32_t, (uint32_t, uint32_t)) | |
311 | -DEF_HELPER_1_2(neon_shl_u64, uint64_t, (uint64_t, uint64_t)) | |
312 | -DEF_HELPER_1_2(neon_shl_s64, uint64_t, (uint64_t, uint64_t)) | |
313 | -DEF_HELPER_1_2(neon_rshl_u8, uint32_t, (uint32_t, uint32_t)) | |
314 | -DEF_HELPER_1_2(neon_rshl_s8, uint32_t, (uint32_t, uint32_t)) | |
315 | -DEF_HELPER_1_2(neon_rshl_u16, uint32_t, (uint32_t, uint32_t)) | |
316 | -DEF_HELPER_1_2(neon_rshl_s16, uint32_t, (uint32_t, uint32_t)) | |
317 | -DEF_HELPER_1_2(neon_rshl_u32, uint32_t, (uint32_t, uint32_t)) | |
318 | -DEF_HELPER_1_2(neon_rshl_s32, uint32_t, (uint32_t, uint32_t)) | |
319 | -DEF_HELPER_1_2(neon_rshl_u64, uint64_t, (uint64_t, uint64_t)) | |
320 | -DEF_HELPER_1_2(neon_rshl_s64, uint64_t, (uint64_t, uint64_t)) | |
321 | -DEF_HELPER_1_3(neon_qshl_u8, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
322 | -DEF_HELPER_1_3(neon_qshl_s8, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
323 | -DEF_HELPER_1_3(neon_qshl_u16, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
324 | -DEF_HELPER_1_3(neon_qshl_s16, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
325 | -DEF_HELPER_1_3(neon_qshl_u32, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
326 | -DEF_HELPER_1_3(neon_qshl_s32, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
327 | -DEF_HELPER_1_3(neon_qshl_u64, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
328 | -DEF_HELPER_1_3(neon_qshl_s64, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
329 | -DEF_HELPER_1_3(neon_qrshl_u8, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
330 | -DEF_HELPER_1_3(neon_qrshl_s8, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
331 | -DEF_HELPER_1_3(neon_qrshl_u16, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
332 | -DEF_HELPER_1_3(neon_qrshl_s16, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
333 | -DEF_HELPER_1_3(neon_qrshl_u32, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
334 | -DEF_HELPER_1_3(neon_qrshl_s32, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
335 | -DEF_HELPER_1_3(neon_qrshl_u64, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
336 | -DEF_HELPER_1_3(neon_qrshl_s64, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
337 | - | |
338 | -DEF_HELPER_1_2(neon_add_u8, uint32_t, (uint32_t, uint32_t)) | |
339 | -DEF_HELPER_1_2(neon_add_u16, uint32_t, (uint32_t, uint32_t)) | |
340 | -DEF_HELPER_1_2(neon_padd_u8, uint32_t, (uint32_t, uint32_t)) | |
341 | -DEF_HELPER_1_2(neon_padd_u16, uint32_t, (uint32_t, uint32_t)) | |
342 | -DEF_HELPER_1_2(neon_sub_u8, uint32_t, (uint32_t, uint32_t)) | |
343 | -DEF_HELPER_1_2(neon_sub_u16, uint32_t, (uint32_t, uint32_t)) | |
344 | -DEF_HELPER_1_2(neon_mul_u8, uint32_t, (uint32_t, uint32_t)) | |
345 | -DEF_HELPER_1_2(neon_mul_u16, uint32_t, (uint32_t, uint32_t)) | |
346 | -DEF_HELPER_1_2(neon_mul_p8, uint32_t, (uint32_t, uint32_t)) | |
347 | - | |
348 | -DEF_HELPER_1_2(neon_tst_u8, uint32_t, (uint32_t, uint32_t)) | |
349 | -DEF_HELPER_1_2(neon_tst_u16, uint32_t, (uint32_t, uint32_t)) | |
350 | -DEF_HELPER_1_2(neon_tst_u32, uint32_t, (uint32_t, uint32_t)) | |
351 | -DEF_HELPER_1_2(neon_ceq_u8, uint32_t, (uint32_t, uint32_t)) | |
352 | -DEF_HELPER_1_2(neon_ceq_u16, uint32_t, (uint32_t, uint32_t)) | |
353 | -DEF_HELPER_1_2(neon_ceq_u32, uint32_t, (uint32_t, uint32_t)) | |
354 | - | |
355 | -DEF_HELPER_1_1(neon_abs_s8, uint32_t, (uint32_t)) | |
356 | -DEF_HELPER_1_1(neon_abs_s16, uint32_t, (uint32_t)) | |
357 | -DEF_HELPER_1_1(neon_clz_u8, uint32_t, (uint32_t)) | |
358 | -DEF_HELPER_1_1(neon_clz_u16, uint32_t, (uint32_t)) | |
359 | -DEF_HELPER_1_1(neon_cls_s8, uint32_t, (uint32_t)) | |
360 | -DEF_HELPER_1_1(neon_cls_s16, uint32_t, (uint32_t)) | |
361 | -DEF_HELPER_1_1(neon_cls_s32, uint32_t, (uint32_t)) | |
362 | -DEF_HELPER_1_1(neon_cnt_u8, uint32_t, (uint32_t)) | |
363 | - | |
364 | -DEF_HELPER_1_3(neon_qdmulh_s16, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
365 | -DEF_HELPER_1_3(neon_qrdmulh_s16, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
366 | -DEF_HELPER_1_3(neon_qdmulh_s32, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
367 | -DEF_HELPER_1_3(neon_qrdmulh_s32, uint32_t, (CPUState *, uint32_t, uint32_t)) | |
368 | - | |
369 | -DEF_HELPER_1_1(neon_narrow_u8, uint32_t, (uint64_t)) | |
370 | -DEF_HELPER_1_1(neon_narrow_u16, uint32_t, (uint64_t)) | |
371 | -DEF_HELPER_1_2(neon_narrow_sat_u8, uint32_t, (CPUState *, uint64_t)) | |
372 | -DEF_HELPER_1_2(neon_narrow_sat_s8, uint32_t, (CPUState *, uint64_t)) | |
373 | -DEF_HELPER_1_2(neon_narrow_sat_u16, uint32_t, (CPUState *, uint64_t)) | |
374 | -DEF_HELPER_1_2(neon_narrow_sat_s16, uint32_t, (CPUState *, uint64_t)) | |
375 | -DEF_HELPER_1_2(neon_narrow_sat_u32, uint32_t, (CPUState *, uint64_t)) | |
376 | -DEF_HELPER_1_2(neon_narrow_sat_s32, uint32_t, (CPUState *, uint64_t)) | |
377 | -DEF_HELPER_1_1(neon_narrow_high_u8, uint32_t, (uint64_t)) | |
378 | -DEF_HELPER_1_1(neon_narrow_high_u16, uint32_t, (uint64_t)) | |
379 | -DEF_HELPER_1_1(neon_narrow_round_high_u8, uint32_t, (uint64_t)) | |
380 | -DEF_HELPER_1_1(neon_narrow_round_high_u16, uint32_t, (uint64_t)) | |
381 | -DEF_HELPER_1_1(neon_widen_u8, uint64_t, (uint32_t)) | |
382 | -DEF_HELPER_1_1(neon_widen_s8, uint64_t, (uint32_t)) | |
383 | -DEF_HELPER_1_1(neon_widen_u16, uint64_t, (uint32_t)) | |
384 | -DEF_HELPER_1_1(neon_widen_s16, uint64_t, (uint32_t)) | |
385 | - | |
386 | -DEF_HELPER_1_2(neon_addl_u16, uint64_t, (uint64_t, uint64_t)) | |
387 | -DEF_HELPER_1_2(neon_addl_u32, uint64_t, (uint64_t, uint64_t)) | |
388 | -DEF_HELPER_1_2(neon_paddl_u16, uint64_t, (uint64_t, uint64_t)) | |
389 | -DEF_HELPER_1_2(neon_paddl_u32, uint64_t, (uint64_t, uint64_t)) | |
390 | -DEF_HELPER_1_2(neon_subl_u16, uint64_t, (uint64_t, uint64_t)) | |
391 | -DEF_HELPER_1_2(neon_subl_u32, uint64_t, (uint64_t, uint64_t)) | |
392 | -DEF_HELPER_1_3(neon_addl_saturate_s32, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
393 | -DEF_HELPER_1_3(neon_addl_saturate_s64, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
394 | -DEF_HELPER_1_2(neon_abdl_u16, uint64_t, (uint32_t, uint32_t)) | |
395 | -DEF_HELPER_1_2(neon_abdl_s16, uint64_t, (uint32_t, uint32_t)) | |
396 | -DEF_HELPER_1_2(neon_abdl_u32, uint64_t, (uint32_t, uint32_t)) | |
397 | -DEF_HELPER_1_2(neon_abdl_s32, uint64_t, (uint32_t, uint32_t)) | |
398 | -DEF_HELPER_1_2(neon_abdl_u64, uint64_t, (uint32_t, uint32_t)) | |
399 | -DEF_HELPER_1_2(neon_abdl_s64, uint64_t, (uint32_t, uint32_t)) | |
400 | -DEF_HELPER_1_2(neon_mull_u8, uint64_t, (uint32_t, uint32_t)) | |
401 | -DEF_HELPER_1_2(neon_mull_s8, uint64_t, (uint32_t, uint32_t)) | |
402 | -DEF_HELPER_1_2(neon_mull_u16, uint64_t, (uint32_t, uint32_t)) | |
403 | -DEF_HELPER_1_2(neon_mull_s16, uint64_t, (uint32_t, uint32_t)) | |
404 | - | |
405 | -DEF_HELPER_1_1(neon_negl_u16, uint64_t, (uint64_t)) | |
406 | -DEF_HELPER_1_1(neon_negl_u32, uint64_t, (uint64_t)) | |
407 | -DEF_HELPER_1_1(neon_negl_u64, uint64_t, (uint64_t)) | |
408 | - | |
409 | -DEF_HELPER_1_2(neon_qabs_s8, uint32_t, (CPUState *, uint32_t)) | |
410 | -DEF_HELPER_1_2(neon_qabs_s16, uint32_t, (CPUState *, uint32_t)) | |
411 | -DEF_HELPER_1_2(neon_qabs_s32, uint32_t, (CPUState *, uint32_t)) | |
412 | -DEF_HELPER_1_2(neon_qneg_s8, uint32_t, (CPUState *, uint32_t)) | |
413 | -DEF_HELPER_1_2(neon_qneg_s16, uint32_t, (CPUState *, uint32_t)) | |
414 | -DEF_HELPER_1_2(neon_qneg_s32, uint32_t, (CPUState *, uint32_t)) | |
415 | - | |
416 | -DEF_HELPER_0_0(neon_trn_u8, void, (void)) | |
417 | -DEF_HELPER_0_0(neon_trn_u16, void, (void)) | |
418 | -DEF_HELPER_0_0(neon_unzip_u8, void, (void)) | |
419 | -DEF_HELPER_0_0(neon_zip_u8, void, (void)) | |
420 | -DEF_HELPER_0_0(neon_zip_u16, void, (void)) | |
421 | - | |
422 | -DEF_HELPER_1_2(neon_min_f32, uint32_t, (uint32_t, uint32_t)) | |
423 | -DEF_HELPER_1_2(neon_max_f32, uint32_t, (uint32_t, uint32_t)) | |
424 | -DEF_HELPER_1_2(neon_abd_f32, uint32_t, (uint32_t, uint32_t)) | |
425 | -DEF_HELPER_1_2(neon_add_f32, uint32_t, (uint32_t, uint32_t)) | |
426 | -DEF_HELPER_1_2(neon_sub_f32, uint32_t, (uint32_t, uint32_t)) | |
427 | -DEF_HELPER_1_2(neon_mul_f32, uint32_t, (uint32_t, uint32_t)) | |
428 | -DEF_HELPER_1_2(neon_ceq_f32, uint32_t, (uint32_t, uint32_t)) | |
429 | -DEF_HELPER_1_2(neon_cge_f32, uint32_t, (uint32_t, uint32_t)) | |
430 | -DEF_HELPER_1_2(neon_cgt_f32, uint32_t, (uint32_t, uint32_t)) | |
431 | -DEF_HELPER_1_2(neon_acge_f32, uint32_t, (uint32_t, uint32_t)) | |
432 | -DEF_HELPER_1_2(neon_acgt_f32, uint32_t, (uint32_t, uint32_t)) | |
161 | +DEF_HELPER_3(neon_qadd_u8, i32, env, i32, i32) | |
162 | +DEF_HELPER_3(neon_qadd_s8, i32, env, i32, i32) | |
163 | +DEF_HELPER_3(neon_qadd_u16, i32, env, i32, i32) | |
164 | +DEF_HELPER_3(neon_qadd_s16, i32, env, i32, i32) | |
165 | +DEF_HELPER_3(neon_qsub_u8, i32, env, i32, i32) | |
166 | +DEF_HELPER_3(neon_qsub_s8, i32, env, i32, i32) | |
167 | +DEF_HELPER_3(neon_qsub_u16, i32, env, i32, i32) | |
168 | +DEF_HELPER_3(neon_qsub_s16, i32, env, i32, i32) | |
169 | + | |
170 | +DEF_HELPER_2(neon_hadd_s8, i32, i32, i32) | |
171 | +DEF_HELPER_2(neon_hadd_u8, i32, i32, i32) | |
172 | +DEF_HELPER_2(neon_hadd_s16, i32, i32, i32) | |
173 | +DEF_HELPER_2(neon_hadd_u16, i32, i32, i32) | |
174 | +DEF_HELPER_2(neon_hadd_s32, s32, s32, s32) | |
175 | +DEF_HELPER_2(neon_hadd_u32, i32, i32, i32) | |
176 | +DEF_HELPER_2(neon_rhadd_s8, i32, i32, i32) | |
177 | +DEF_HELPER_2(neon_rhadd_u8, i32, i32, i32) | |
178 | +DEF_HELPER_2(neon_rhadd_s16, i32, i32, i32) | |
179 | +DEF_HELPER_2(neon_rhadd_u16, i32, i32, i32) | |
180 | +DEF_HELPER_2(neon_rhadd_s32, s32, s32, s32) | |
181 | +DEF_HELPER_2(neon_rhadd_u32, i32, i32, i32) | |
182 | +DEF_HELPER_2(neon_hsub_s8, i32, i32, i32) | |
183 | +DEF_HELPER_2(neon_hsub_u8, i32, i32, i32) | |
184 | +DEF_HELPER_2(neon_hsub_s16, i32, i32, i32) | |
185 | +DEF_HELPER_2(neon_hsub_u16, i32, i32, i32) | |
186 | +DEF_HELPER_2(neon_hsub_s32, s32, s32, s32) | |
187 | +DEF_HELPER_2(neon_hsub_u32, i32, i32, i32) | |
188 | + | |
189 | +DEF_HELPER_2(neon_cgt_u8, i32, i32, i32) | |
190 | +DEF_HELPER_2(neon_cgt_s8, i32, i32, i32) | |
191 | +DEF_HELPER_2(neon_cgt_u16, i32, i32, i32) | |
192 | +DEF_HELPER_2(neon_cgt_s16, i32, i32, i32) | |
193 | +DEF_HELPER_2(neon_cgt_u32, i32, i32, i32) | |
194 | +DEF_HELPER_2(neon_cgt_s32, i32, i32, i32) | |
195 | +DEF_HELPER_2(neon_cge_u8, i32, i32, i32) | |
196 | +DEF_HELPER_2(neon_cge_s8, i32, i32, i32) | |
197 | +DEF_HELPER_2(neon_cge_u16, i32, i32, i32) | |
198 | +DEF_HELPER_2(neon_cge_s16, i32, i32, i32) | |
199 | +DEF_HELPER_2(neon_cge_u32, i32, i32, i32) | |
200 | +DEF_HELPER_2(neon_cge_s32, i32, i32, i32) | |
201 | + | |
202 | +DEF_HELPER_2(neon_min_u8, i32, i32, i32) | |
203 | +DEF_HELPER_2(neon_min_s8, i32, i32, i32) | |
204 | +DEF_HELPER_2(neon_min_u16, i32, i32, i32) | |
205 | +DEF_HELPER_2(neon_min_s16, i32, i32, i32) | |
206 | +DEF_HELPER_2(neon_min_u32, i32, i32, i32) | |
207 | +DEF_HELPER_2(neon_min_s32, i32, i32, i32) | |
208 | +DEF_HELPER_2(neon_max_u8, i32, i32, i32) | |
209 | +DEF_HELPER_2(neon_max_s8, i32, i32, i32) | |
210 | +DEF_HELPER_2(neon_max_u16, i32, i32, i32) | |
211 | +DEF_HELPER_2(neon_max_s16, i32, i32, i32) | |
212 | +DEF_HELPER_2(neon_max_u32, i32, i32, i32) | |
213 | +DEF_HELPER_2(neon_max_s32, i32, i32, i32) | |
214 | +DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) | |
215 | +DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) | |
216 | +DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) | |
217 | +DEF_HELPER_2(neon_pmin_s16, i32, i32, i32) | |
218 | +DEF_HELPER_2(neon_pmax_u8, i32, i32, i32) | |
219 | +DEF_HELPER_2(neon_pmax_s8, i32, i32, i32) | |
220 | +DEF_HELPER_2(neon_pmax_u16, i32, i32, i32) | |
221 | +DEF_HELPER_2(neon_pmax_s16, i32, i32, i32) | |
222 | + | |
223 | +DEF_HELPER_2(neon_abd_u8, i32, i32, i32) | |
224 | +DEF_HELPER_2(neon_abd_s8, i32, i32, i32) | |
225 | +DEF_HELPER_2(neon_abd_u16, i32, i32, i32) | |
226 | +DEF_HELPER_2(neon_abd_s16, i32, i32, i32) | |
227 | +DEF_HELPER_2(neon_abd_u32, i32, i32, i32) | |
228 | +DEF_HELPER_2(neon_abd_s32, i32, i32, i32) | |
229 | + | |
230 | +DEF_HELPER_2(neon_shl_u8, i32, i32, i32) | |
231 | +DEF_HELPER_2(neon_shl_s8, i32, i32, i32) | |
232 | +DEF_HELPER_2(neon_shl_u16, i32, i32, i32) | |
233 | +DEF_HELPER_2(neon_shl_s16, i32, i32, i32) | |
234 | +DEF_HELPER_2(neon_shl_u32, i32, i32, i32) | |
235 | +DEF_HELPER_2(neon_shl_s32, i32, i32, i32) | |
236 | +DEF_HELPER_2(neon_shl_u64, i64, i64, i64) | |
237 | +DEF_HELPER_2(neon_shl_s64, i64, i64, i64) | |
238 | +DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) | |
239 | +DEF_HELPER_2(neon_rshl_s8, i32, i32, i32) | |
240 | +DEF_HELPER_2(neon_rshl_u16, i32, i32, i32) | |
241 | +DEF_HELPER_2(neon_rshl_s16, i32, i32, i32) | |
242 | +DEF_HELPER_2(neon_rshl_u32, i32, i32, i32) | |
243 | +DEF_HELPER_2(neon_rshl_s32, i32, i32, i32) | |
244 | +DEF_HELPER_2(neon_rshl_u64, i64, i64, i64) | |
245 | +DEF_HELPER_2(neon_rshl_s64, i64, i64, i64) | |
246 | +DEF_HELPER_3(neon_qshl_u8, i32, env, i32, i32) | |
247 | +DEF_HELPER_3(neon_qshl_s8, i32, env, i32, i32) | |
248 | +DEF_HELPER_3(neon_qshl_u16, i32, env, i32, i32) | |
249 | +DEF_HELPER_3(neon_qshl_s16, i32, env, i32, i32) | |
250 | +DEF_HELPER_3(neon_qshl_u32, i32, env, i32, i32) | |
251 | +DEF_HELPER_3(neon_qshl_s32, i32, env, i32, i32) | |
252 | +DEF_HELPER_3(neon_qshl_u64, i64, env, i64, i64) | |
253 | +DEF_HELPER_3(neon_qshl_s64, i64, env, i64, i64) | |
254 | +DEF_HELPER_3(neon_qrshl_u8, i32, env, i32, i32) | |
255 | +DEF_HELPER_3(neon_qrshl_s8, i32, env, i32, i32) | |
256 | +DEF_HELPER_3(neon_qrshl_u16, i32, env, i32, i32) | |
257 | +DEF_HELPER_3(neon_qrshl_s16, i32, env, i32, i32) | |
258 | +DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32) | |
259 | +DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32) | |
260 | +DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64) | |
261 | +DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64) | |
262 | + | |
263 | +DEF_HELPER_2(neon_add_u8, i32, i32, i32) | |
264 | +DEF_HELPER_2(neon_add_u16, i32, i32, i32) | |
265 | +DEF_HELPER_2(neon_padd_u8, i32, i32, i32) | |
266 | +DEF_HELPER_2(neon_padd_u16, i32, i32, i32) | |
267 | +DEF_HELPER_2(neon_sub_u8, i32, i32, i32) | |
268 | +DEF_HELPER_2(neon_sub_u16, i32, i32, i32) | |
269 | +DEF_HELPER_2(neon_mul_u8, i32, i32, i32) | |
270 | +DEF_HELPER_2(neon_mul_u16, i32, i32, i32) | |
271 | +DEF_HELPER_2(neon_mul_p8, i32, i32, i32) | |
272 | + | |
273 | +DEF_HELPER_2(neon_tst_u8, i32, i32, i32) | |
274 | +DEF_HELPER_2(neon_tst_u16, i32, i32, i32) | |
275 | +DEF_HELPER_2(neon_tst_u32, i32, i32, i32) | |
276 | +DEF_HELPER_2(neon_ceq_u8, i32, i32, i32) | |
277 | +DEF_HELPER_2(neon_ceq_u16, i32, i32, i32) | |
278 | +DEF_HELPER_2(neon_ceq_u32, i32, i32, i32) | |
279 | + | |
280 | +DEF_HELPER_1(neon_abs_s8, i32, i32) | |
281 | +DEF_HELPER_1(neon_abs_s16, i32, i32) | |
282 | +DEF_HELPER_1(neon_clz_u8, i32, i32) | |
283 | +DEF_HELPER_1(neon_clz_u16, i32, i32) | |
284 | +DEF_HELPER_1(neon_cls_s8, i32, i32) | |
285 | +DEF_HELPER_1(neon_cls_s16, i32, i32) | |
286 | +DEF_HELPER_1(neon_cls_s32, i32, i32) | |
287 | +DEF_HELPER_1(neon_cnt_u8, i32, i32) | |
288 | + | |
289 | +DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) | |
290 | +DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) | |
291 | +DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) | |
292 | +DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) | |
293 | + | |
294 | +DEF_HELPER_1(neon_narrow_u8, i32, i64) | |
295 | +DEF_HELPER_1(neon_narrow_u16, i32, i64) | |
296 | +DEF_HELPER_2(neon_narrow_sat_u8, i32, env, i64) | |
297 | +DEF_HELPER_2(neon_narrow_sat_s8, i32, env, i64) | |
298 | +DEF_HELPER_2(neon_narrow_sat_u16, i32, env, i64) | |
299 | +DEF_HELPER_2(neon_narrow_sat_s16, i32, env, i64) | |
300 | +DEF_HELPER_2(neon_narrow_sat_u32, i32, env, i64) | |
301 | +DEF_HELPER_2(neon_narrow_sat_s32, i32, env, i64) | |
302 | +DEF_HELPER_1(neon_narrow_high_u8, i32, i64) | |
303 | +DEF_HELPER_1(neon_narrow_high_u16, i32, i64) | |
304 | +DEF_HELPER_1(neon_narrow_round_high_u8, i32, i64) | |
305 | +DEF_HELPER_1(neon_narrow_round_high_u16, i32, i64) | |
306 | +DEF_HELPER_1(neon_widen_u8, i64, i32) | |
307 | +DEF_HELPER_1(neon_widen_s8, i64, i32) | |
308 | +DEF_HELPER_1(neon_widen_u16, i64, i32) | |
309 | +DEF_HELPER_1(neon_widen_s16, i64, i32) | |
310 | + | |
311 | +DEF_HELPER_2(neon_addl_u16, i64, i64, i64) | |
312 | +DEF_HELPER_2(neon_addl_u32, i64, i64, i64) | |
313 | +DEF_HELPER_2(neon_paddl_u16, i64, i64, i64) | |
314 | +DEF_HELPER_2(neon_paddl_u32, i64, i64, i64) | |
315 | +DEF_HELPER_2(neon_subl_u16, i64, i64, i64) | |
316 | +DEF_HELPER_2(neon_subl_u32, i64, i64, i64) | |
317 | +DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64) | |
318 | +DEF_HELPER_3(neon_addl_saturate_s64, i64, env, i64, i64) | |
319 | +DEF_HELPER_2(neon_abdl_u16, i64, i32, i32) | |
320 | +DEF_HELPER_2(neon_abdl_s16, i64, i32, i32) | |
321 | +DEF_HELPER_2(neon_abdl_u32, i64, i32, i32) | |
322 | +DEF_HELPER_2(neon_abdl_s32, i64, i32, i32) | |
323 | +DEF_HELPER_2(neon_abdl_u64, i64, i32, i32) | |
324 | +DEF_HELPER_2(neon_abdl_s64, i64, i32, i32) | |
325 | +DEF_HELPER_2(neon_mull_u8, i64, i32, i32) | |
326 | +DEF_HELPER_2(neon_mull_s8, i64, i32, i32) | |
327 | +DEF_HELPER_2(neon_mull_u16, i64, i32, i32) | |
328 | +DEF_HELPER_2(neon_mull_s16, i64, i32, i32) | |
329 | + | |
330 | +DEF_HELPER_1(neon_negl_u16, i64, i64) | |
331 | +DEF_HELPER_1(neon_negl_u32, i64, i64) | |
332 | +DEF_HELPER_1(neon_negl_u64, i64, i64) | |
333 | + | |
334 | +DEF_HELPER_2(neon_qabs_s8, i32, env, i32) | |
335 | +DEF_HELPER_2(neon_qabs_s16, i32, env, i32) | |
336 | +DEF_HELPER_2(neon_qabs_s32, i32, env, i32) | |
337 | +DEF_HELPER_2(neon_qneg_s8, i32, env, i32) | |
338 | +DEF_HELPER_2(neon_qneg_s16, i32, env, i32) | |
339 | +DEF_HELPER_2(neon_qneg_s32, i32, env, i32) | |
340 | + | |
341 | +DEF_HELPER_0(neon_trn_u8, void) | |
342 | +DEF_HELPER_0(neon_trn_u16, void) | |
343 | +DEF_HELPER_0(neon_unzip_u8, void) | |
344 | +DEF_HELPER_0(neon_zip_u8, void) | |
345 | +DEF_HELPER_0(neon_zip_u16, void) | |
346 | + | |
347 | +DEF_HELPER_2(neon_min_f32, i32, i32, i32) | |
348 | +DEF_HELPER_2(neon_max_f32, i32, i32, i32) | |
349 | +DEF_HELPER_2(neon_abd_f32, i32, i32, i32) | |
350 | +DEF_HELPER_2(neon_add_f32, i32, i32, i32) | |
351 | +DEF_HELPER_2(neon_sub_f32, i32, i32, i32) | |
352 | +DEF_HELPER_2(neon_mul_f32, i32, i32, i32) | |
353 | +DEF_HELPER_2(neon_ceq_f32, i32, i32, i32) | |
354 | +DEF_HELPER_2(neon_cge_f32, i32, i32, i32) | |
355 | +DEF_HELPER_2(neon_cgt_f32, i32, i32, i32) | |
356 | +DEF_HELPER_2(neon_acge_f32, i32, i32, i32) | |
357 | +DEF_HELPER_2(neon_acgt_f32, i32, i32, i32) | |
433 | 358 | |
434 | 359 | /* iwmmxt_helper.c */ |
435 | -DEF_HELPER_1_2(iwmmxt_maddsq, uint64_t, (uint64_t, uint64_t)) | |
436 | -DEF_HELPER_1_2(iwmmxt_madduq, uint64_t, (uint64_t, uint64_t)) | |
437 | -DEF_HELPER_1_2(iwmmxt_sadb, uint64_t, (uint64_t, uint64_t)) | |
438 | -DEF_HELPER_1_2(iwmmxt_sadw, uint64_t, (uint64_t, uint64_t)) | |
439 | -DEF_HELPER_1_2(iwmmxt_mulslw, uint64_t, (uint64_t, uint64_t)) | |
440 | -DEF_HELPER_1_2(iwmmxt_mulshw, uint64_t, (uint64_t, uint64_t)) | |
441 | -DEF_HELPER_1_2(iwmmxt_mululw, uint64_t, (uint64_t, uint64_t)) | |
442 | -DEF_HELPER_1_2(iwmmxt_muluhw, uint64_t, (uint64_t, uint64_t)) | |
443 | -DEF_HELPER_1_2(iwmmxt_macsw, uint64_t, (uint64_t, uint64_t)) | |
444 | -DEF_HELPER_1_2(iwmmxt_macuw, uint64_t, (uint64_t, uint64_t)) | |
445 | -DEF_HELPER_1_1(iwmmxt_setpsr_nz, uint32_t, (uint64_t)) | |
360 | +DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64) | |
361 | +DEF_HELPER_2(iwmmxt_madduq, i64, i64, i64) | |
362 | +DEF_HELPER_2(iwmmxt_sadb, i64, i64, i64) | |
363 | +DEF_HELPER_2(iwmmxt_sadw, i64, i64, i64) | |
364 | +DEF_HELPER_2(iwmmxt_mulslw, i64, i64, i64) | |
365 | +DEF_HELPER_2(iwmmxt_mulshw, i64, i64, i64) | |
366 | +DEF_HELPER_2(iwmmxt_mululw, i64, i64, i64) | |
367 | +DEF_HELPER_2(iwmmxt_muluhw, i64, i64, i64) | |
368 | +DEF_HELPER_2(iwmmxt_macsw, i64, i64, i64) | |
369 | +DEF_HELPER_2(iwmmxt_macuw, i64, i64, i64) | |
370 | +DEF_HELPER_1(iwmmxt_setpsr_nz, i32, i64) | |
446 | 371 | |
447 | 372 | #define DEF_IWMMXT_HELPER_SIZE_ENV(name) \ |
448 | -DEF_HELPER_1_3(iwmmxt_##name##b, uint64_t, (CPUState *, uint64_t, uint64_t)) \ | |
449 | -DEF_HELPER_1_3(iwmmxt_##name##w, uint64_t, (CPUState *, uint64_t, uint64_t)) \ | |
450 | -DEF_HELPER_1_3(iwmmxt_##name##l, uint64_t, (CPUState *, uint64_t, uint64_t)) \ | |
373 | +DEF_HELPER_3(iwmmxt_##name##b, i64, env, i64, i64) \ | |
374 | +DEF_HELPER_3(iwmmxt_##name##w, i64, env, i64, i64) \ | |
375 | +DEF_HELPER_3(iwmmxt_##name##l, i64, env, i64, i64) \ | |
451 | 376 | |
452 | 377 | DEF_IWMMXT_HELPER_SIZE_ENV(unpackl) |
453 | 378 | DEF_IWMMXT_HELPER_SIZE_ENV(unpackh) |
454 | 379 | |
455 | -DEF_HELPER_1_2(iwmmxt_unpacklub, uint64_t, (CPUState *, uint64_t)) | |
456 | -DEF_HELPER_1_2(iwmmxt_unpackluw, uint64_t, (CPUState *, uint64_t)) | |
457 | -DEF_HELPER_1_2(iwmmxt_unpacklul, uint64_t, (CPUState *, uint64_t)) | |
458 | -DEF_HELPER_1_2(iwmmxt_unpackhub, uint64_t, (CPUState *, uint64_t)) | |
459 | -DEF_HELPER_1_2(iwmmxt_unpackhuw, uint64_t, (CPUState *, uint64_t)) | |
460 | -DEF_HELPER_1_2(iwmmxt_unpackhul, uint64_t, (CPUState *, uint64_t)) | |
461 | -DEF_HELPER_1_2(iwmmxt_unpacklsb, uint64_t, (CPUState *, uint64_t)) | |
462 | -DEF_HELPER_1_2(iwmmxt_unpacklsw, uint64_t, (CPUState *, uint64_t)) | |
463 | -DEF_HELPER_1_2(iwmmxt_unpacklsl, uint64_t, (CPUState *, uint64_t)) | |
464 | -DEF_HELPER_1_2(iwmmxt_unpackhsb, uint64_t, (CPUState *, uint64_t)) | |
465 | -DEF_HELPER_1_2(iwmmxt_unpackhsw, uint64_t, (CPUState *, uint64_t)) | |
466 | -DEF_HELPER_1_2(iwmmxt_unpackhsl, uint64_t, (CPUState *, uint64_t)) | |
380 | +DEF_HELPER_2(iwmmxt_unpacklub, i64, env, i64) | |
381 | +DEF_HELPER_2(iwmmxt_unpackluw, i64, env, i64) | |
382 | +DEF_HELPER_2(iwmmxt_unpacklul, i64, env, i64) | |
383 | +DEF_HELPER_2(iwmmxt_unpackhub, i64, env, i64) | |
384 | +DEF_HELPER_2(iwmmxt_unpackhuw, i64, env, i64) | |
385 | +DEF_HELPER_2(iwmmxt_unpackhul, i64, env, i64) | |
386 | +DEF_HELPER_2(iwmmxt_unpacklsb, i64, env, i64) | |
387 | +DEF_HELPER_2(iwmmxt_unpacklsw, i64, env, i64) | |
388 | +DEF_HELPER_2(iwmmxt_unpacklsl, i64, env, i64) | |
389 | +DEF_HELPER_2(iwmmxt_unpackhsb, i64, env, i64) | |
390 | +DEF_HELPER_2(iwmmxt_unpackhsw, i64, env, i64) | |
391 | +DEF_HELPER_2(iwmmxt_unpackhsl, i64, env, i64) | |
467 | 392 | |
468 | 393 | DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq) |
469 | 394 | DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu) |
... | ... | @@ -481,59 +406,51 @@ DEF_IWMMXT_HELPER_SIZE_ENV(addu) |
481 | 406 | DEF_IWMMXT_HELPER_SIZE_ENV(subs) |
482 | 407 | DEF_IWMMXT_HELPER_SIZE_ENV(adds) |
483 | 408 | |
484 | -DEF_HELPER_1_3(iwmmxt_avgb0, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
485 | -DEF_HELPER_1_3(iwmmxt_avgb1, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
486 | -DEF_HELPER_1_3(iwmmxt_avgw0, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
487 | -DEF_HELPER_1_3(iwmmxt_avgw1, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
488 | - | |
489 | -DEF_HELPER_1_2(iwmmxt_msadb, uint64_t, (uint64_t, uint64_t)) | |
490 | - | |
491 | -DEF_HELPER_1_3(iwmmxt_align, uint64_t, (uint64_t, uint64_t, uint32_t)) | |
492 | -DEF_HELPER_1_4(iwmmxt_insr, uint64_t, (uint64_t, uint32_t, uint32_t, uint32_t)) | |
493 | - | |
494 | -DEF_HELPER_1_1(iwmmxt_bcstb, uint64_t, (uint32_t)) | |
495 | -DEF_HELPER_1_1(iwmmxt_bcstw, uint64_t, (uint32_t)) | |
496 | -DEF_HELPER_1_1(iwmmxt_bcstl, uint64_t, (uint32_t)) | |
497 | - | |
498 | -DEF_HELPER_1_1(iwmmxt_addcb, uint64_t, (uint64_t)) | |
499 | -DEF_HELPER_1_1(iwmmxt_addcw, uint64_t, (uint64_t)) | |
500 | -DEF_HELPER_1_1(iwmmxt_addcl, uint64_t, (uint64_t)) | |
501 | - | |
502 | -DEF_HELPER_1_1(iwmmxt_msbb, uint32_t, (uint64_t)) | |
503 | -DEF_HELPER_1_1(iwmmxt_msbw, uint32_t, (uint64_t)) | |
504 | -DEF_HELPER_1_1(iwmmxt_msbl, uint32_t, (uint64_t)) | |
505 | - | |
506 | -DEF_HELPER_1_3(iwmmxt_srlw, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
507 | -DEF_HELPER_1_3(iwmmxt_srll, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
508 | -DEF_HELPER_1_3(iwmmxt_srlq, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
509 | -DEF_HELPER_1_3(iwmmxt_sllw, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
510 | -DEF_HELPER_1_3(iwmmxt_slll, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
511 | -DEF_HELPER_1_3(iwmmxt_sllq, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
512 | -DEF_HELPER_1_3(iwmmxt_sraw, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
513 | -DEF_HELPER_1_3(iwmmxt_sral, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
514 | -DEF_HELPER_1_3(iwmmxt_sraq, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
515 | -DEF_HELPER_1_3(iwmmxt_rorw, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
516 | -DEF_HELPER_1_3(iwmmxt_rorl, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
517 | -DEF_HELPER_1_3(iwmmxt_rorq, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
518 | -DEF_HELPER_1_3(iwmmxt_shufh, uint64_t, (CPUState *, uint64_t, uint32_t)) | |
519 | - | |
520 | -DEF_HELPER_1_3(iwmmxt_packuw, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
521 | -DEF_HELPER_1_3(iwmmxt_packul, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
522 | -DEF_HELPER_1_3(iwmmxt_packuq, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
523 | -DEF_HELPER_1_3(iwmmxt_packsw, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
524 | -DEF_HELPER_1_3(iwmmxt_packsl, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
525 | -DEF_HELPER_1_3(iwmmxt_packsq, uint64_t, (CPUState *, uint64_t, uint64_t)) | |
526 | - | |
527 | -DEF_HELPER_1_3(iwmmxt_muladdsl, uint64_t, (uint64_t, uint32_t, uint32_t)) | |
528 | -DEF_HELPER_1_3(iwmmxt_muladdsw, uint64_t, (uint64_t, uint32_t, uint32_t)) | |
529 | -DEF_HELPER_1_3(iwmmxt_muladdswl, uint64_t, (uint64_t, uint32_t, uint32_t)) | |
530 | - | |
531 | -#undef DEF_HELPER | |
532 | -#undef DEF_HELPER_0_0 | |
533 | -#undef DEF_HELPER_0_1 | |
534 | -#undef DEF_HELPER_0_2 | |
535 | -#undef DEF_HELPER_1_0 | |
536 | -#undef DEF_HELPER_1_1 | |
537 | -#undef DEF_HELPER_1_2 | |
538 | -#undef DEF_HELPER_1_3 | |
539 | -#undef GEN_HELPER | |
409 | +DEF_HELPER_3(iwmmxt_avgb0, i64, env, i64, i64) | |
410 | +DEF_HELPER_3(iwmmxt_avgb1, i64, env, i64, i64) | |
411 | +DEF_HELPER_3(iwmmxt_avgw0, i64, env, i64, i64) | |
412 | +DEF_HELPER_3(iwmmxt_avgw1, i64, env, i64, i64) | |
413 | + | |
414 | +DEF_HELPER_2(iwmmxt_msadb, i64, i64, i64) | |
415 | + | |
416 | +DEF_HELPER_3(iwmmxt_align, i64, i64, i64, i32) | |
417 | +DEF_HELPER_4(iwmmxt_insr, i64, i64, i32, i32, i32) | |
418 | + | |
419 | +DEF_HELPER_1(iwmmxt_bcstb, i64, i32) | |
420 | +DEF_HELPER_1(iwmmxt_bcstw, i64, i32) | |
421 | +DEF_HELPER_1(iwmmxt_bcstl, i64, i32) | |
422 | + | |
423 | +DEF_HELPER_1(iwmmxt_addcb, i64, i64) | |
424 | +DEF_HELPER_1(iwmmxt_addcw, i64, i64) | |
425 | +DEF_HELPER_1(iwmmxt_addcl, i64, i64) | |
426 | + | |
427 | +DEF_HELPER_1(iwmmxt_msbb, i32, i64) | |
428 | +DEF_HELPER_1(iwmmxt_msbw, i32, i64) | |
429 | +DEF_HELPER_1(iwmmxt_msbl, i32, i64) | |
430 | + | |
431 | +DEF_HELPER_3(iwmmxt_srlw, i64, env, i64, i32) | |
432 | +DEF_HELPER_3(iwmmxt_srll, i64, env, i64, i32) | |
433 | +DEF_HELPER_3(iwmmxt_srlq, i64, env, i64, i32) | |
434 | +DEF_HELPER_3(iwmmxt_sllw, i64, env, i64, i32) | |
435 | +DEF_HELPER_3(iwmmxt_slll, i64, env, i64, i32) | |
436 | +DEF_HELPER_3(iwmmxt_sllq, i64, env, i64, i32) | |
437 | +DEF_HELPER_3(iwmmxt_sraw, i64, env, i64, i32) | |
438 | +DEF_HELPER_3(iwmmxt_sral, i64, env, i64, i32) | |
439 | +DEF_HELPER_3(iwmmxt_sraq, i64, env, i64, i32) | |
440 | +DEF_HELPER_3(iwmmxt_rorw, i64, env, i64, i32) | |
441 | +DEF_HELPER_3(iwmmxt_rorl, i64, env, i64, i32) | |
442 | +DEF_HELPER_3(iwmmxt_rorq, i64, env, i64, i32) | |
443 | +DEF_HELPER_3(iwmmxt_shufh, i64, env, i64, i32) | |
444 | + | |
445 | +DEF_HELPER_3(iwmmxt_packuw, i64, env, i64, i64) | |
446 | +DEF_HELPER_3(iwmmxt_packul, i64, env, i64, i64) | |
447 | +DEF_HELPER_3(iwmmxt_packuq, i64, env, i64, i64) | |
448 | +DEF_HELPER_3(iwmmxt_packsw, i64, env, i64, i64) | |
449 | +DEF_HELPER_3(iwmmxt_packsl, i64, env, i64, i64) | |
450 | +DEF_HELPER_3(iwmmxt_packsq, i64, env, i64, i64) | |
451 | + | |
452 | +DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) | |
453 | +DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) | |
454 | +DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) | |
455 | + | |
456 | +#include "def-helper.h" | ... | ... |
target-arm/op_addsub.h
... | ... | @@ -8,9 +8,9 @@ |
8 | 8 | */ |
9 | 9 | |
10 | 10 | #ifdef ARITH_GE |
11 | -#define GE_ARG , uint32_t *gep | |
11 | +#define GE_ARG , void *gep | |
12 | 12 | #define DECLARE_GE uint32_t ge = 0 |
13 | -#define SET_GE *gep = ge | |
13 | +#define SET_GE *(uint32_t *)gep = ge | |
14 | 14 | #else |
15 | 15 | #define GE_ARG |
16 | 16 | #define DECLARE_GE do{}while(0) | ... | ... |
target-arm/translate.c
... | ... | @@ -31,6 +31,7 @@ |
31 | 31 | #include "tcg-op.h" |
32 | 32 | #include "qemu-log.h" |
33 | 33 | |
34 | +#include "helpers.h" | |
34 | 35 | #define GEN_HELPER 1 |
35 | 36 | #include "helpers.h" |
36 | 37 | |
... | ... | @@ -73,13 +74,14 @@ typedef struct DisasContext { |
73 | 74 | #define DISAS_WFI 4 |
74 | 75 | #define DISAS_SWI 5 |
75 | 76 | |
76 | -static TCGv cpu_env; | |
77 | +static TCGv_ptr cpu_env; | |
77 | 78 | /* We reuse the same 64-bit temporaries for efficiency. */ |
78 | -static TCGv cpu_V0, cpu_V1, cpu_M0; | |
79 | +static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; | |
79 | 80 | |
80 | 81 | /* FIXME: These should be removed. */ |
81 | 82 | static TCGv cpu_T[2]; |
82 | -static TCGv cpu_F0s, cpu_F1s, cpu_F0d, cpu_F1d; | |
83 | +static TCGv cpu_F0s, cpu_F1s; | |
84 | +static TCGv_i64 cpu_F0d, cpu_F1d; | |
83 | 85 | |
84 | 86 | #define ICOUNT_TEMP cpu_T[0] |
85 | 87 | #include "gen-icount.h" |
... | ... | @@ -87,10 +89,13 @@ static TCGv cpu_F0s, cpu_F1s, cpu_F0d, cpu_F1d; |
87 | 89 | /* initialize TCG globals. */ |
88 | 90 | void arm_translate_init(void) |
89 | 91 | { |
90 | - cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); | |
92 | + cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
93 | + | |
94 | + cpu_T[0] = tcg_global_reg_new_i32(TCG_AREG1, "T0"); | |
95 | + cpu_T[1] = tcg_global_reg_new_i32(TCG_AREG2, "T1"); | |
91 | 96 | |
92 | - cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG1, "T0"); | |
93 | - cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG2, "T1"); | |
97 | +#define GEN_HELPER 2 | |
98 | +#include "helpers.h" | |
94 | 99 | } |
95 | 100 | |
96 | 101 | /* The code generator doesn't like lots of temporaries, so maintain our own |
... | ... | @@ -100,16 +105,16 @@ static int num_temps; |
100 | 105 | static TCGv temps[MAX_TEMPS]; |
101 | 106 | |
102 | 107 | /* Allocate a temporary variable. */ |
103 | -static TCGv new_tmp(void) | |
108 | +static TCGv_i32 new_tmp(void) | |
104 | 109 | { |
105 | 110 | TCGv tmp; |
106 | 111 | if (num_temps == MAX_TEMPS) |
107 | 112 | abort(); |
108 | 113 | |
109 | - if (GET_TCGV(temps[num_temps])) | |
114 | + if (GET_TCGV_I32(temps[num_temps])) | |
110 | 115 | return temps[num_temps++]; |
111 | 116 | |
112 | - tmp = tcg_temp_new(TCG_TYPE_I32); | |
117 | + tmp = tcg_temp_new_i32(); | |
113 | 118 | temps[num_temps++] = tmp; |
114 | 119 | return tmp; |
115 | 120 | } |
... | ... | @@ -120,11 +125,11 @@ static void dead_tmp(TCGv tmp) |
120 | 125 | int i; |
121 | 126 | num_temps--; |
122 | 127 | i = num_temps; |
123 | - if (GET_TCGV(temps[i]) == GET_TCGV(tmp)) | |
128 | + if (TCGV_EQUAL(temps[i], tmp)) | |
124 | 129 | return; |
125 | 130 | |
126 | 131 | /* Shuffle this temp to the last slot. */ |
127 | - while (GET_TCGV(temps[i]) != GET_TCGV(tmp)) | |
132 | + while (!TCGV_EQUAL(temps[i], tmp)) | |
128 | 133 | i--; |
129 | 134 | while (i < num_temps) { |
130 | 135 | temps[i] = temps[i + 1]; |
... | ... | @@ -324,10 +329,10 @@ static void gen_roundqd(TCGv a, TCGv b) |
324 | 329 | /* FIXME: Most targets have native widening multiplication. |
325 | 330 | It would be good to use that instead of a full wide multiply. */ |
326 | 331 | /* 32x32->64 multiply. Marks inputs as dead. */ |
327 | -static TCGv gen_mulu_i64_i32(TCGv a, TCGv b) | |
332 | +static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b) | |
328 | 333 | { |
329 | - TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64); | |
330 | - TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); | |
334 | + TCGv_i64 tmp1 = tcg_temp_new_i64(); | |
335 | + TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
331 | 336 | |
332 | 337 | tcg_gen_extu_i32_i64(tmp1, a); |
333 | 338 | dead_tmp(a); |
... | ... | @@ -337,10 +342,10 @@ static TCGv gen_mulu_i64_i32(TCGv a, TCGv b) |
337 | 342 | return tmp1; |
338 | 343 | } |
339 | 344 | |
340 | -static TCGv gen_muls_i64_i32(TCGv a, TCGv b) | |
345 | +static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b) | |
341 | 346 | { |
342 | - TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64); | |
343 | - TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); | |
347 | + TCGv_i64 tmp1 = tcg_temp_new_i64(); | |
348 | + TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
344 | 349 | |
345 | 350 | tcg_gen_ext_i32_i64(tmp1, a); |
346 | 351 | dead_tmp(a); |
... | ... | @@ -353,8 +358,8 @@ static TCGv gen_muls_i64_i32(TCGv a, TCGv b) |
353 | 358 | /* Unsigned 32x32->64 multiply. */ |
354 | 359 | static void gen_op_mull_T0_T1(void) |
355 | 360 | { |
356 | - TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64); | |
357 | - TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); | |
361 | + TCGv_i64 tmp1 = tcg_temp_new_i64(); | |
362 | + TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
358 | 363 | |
359 | 364 | tcg_gen_extu_i32_i64(tmp1, cpu_T[0]); |
360 | 365 | tcg_gen_extu_i32_i64(tmp2, cpu_T[1]); |
... | ... | @@ -367,8 +372,8 @@ static void gen_op_mull_T0_T1(void) |
367 | 372 | /* Signed 32x32->64 multiply. */ |
368 | 373 | static void gen_imull(TCGv a, TCGv b) |
369 | 374 | { |
370 | - TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64); | |
371 | - TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); | |
375 | + TCGv_i64 tmp1 = tcg_temp_new_i64(); | |
376 | + TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
372 | 377 | |
373 | 378 | tcg_gen_ext_i32_i64(tmp1, a); |
374 | 379 | tcg_gen_ext_i32_i64(tmp2, b); |
... | ... | @@ -580,17 +585,17 @@ static inline void gen_arm_shift_reg(TCGv var, int shiftop, |
580 | 585 | } |
581 | 586 | static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b) |
582 | 587 | { |
583 | - TCGv tmp; | |
588 | + TCGv_ptr tmp; | |
584 | 589 | |
585 | 590 | switch (op1) { |
586 | 591 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) |
587 | 592 | case 1: |
588 | - tmp = tcg_temp_new(TCG_TYPE_PTR); | |
593 | + tmp = tcg_temp_new_ptr(); | |
589 | 594 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
590 | 595 | PAS_OP(s) |
591 | 596 | break; |
592 | 597 | case 5: |
593 | - tmp = tcg_temp_new(TCG_TYPE_PTR); | |
598 | + tmp = tcg_temp_new_ptr(); | |
594 | 599 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
595 | 600 | PAS_OP(u) |
596 | 601 | break; |
... | ... | @@ -625,17 +630,17 @@ static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b) |
625 | 630 | } |
626 | 631 | static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b) |
627 | 632 | { |
628 | - TCGv tmp; | |
633 | + TCGv_ptr tmp; | |
629 | 634 | |
630 | 635 | switch (op1) { |
631 | 636 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) |
632 | 637 | case 0: |
633 | - tmp = tcg_temp_new(TCG_TYPE_PTR); | |
638 | + tmp = tcg_temp_new_ptr(); | |
634 | 639 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
635 | 640 | PAS_OP(s) |
636 | 641 | break; |
637 | 642 | case 4: |
638 | - tmp = tcg_temp_new(TCG_TYPE_PTR); | |
643 | + tmp = tcg_temp_new_ptr(); | |
639 | 644 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
640 | 645 | PAS_OP(u) |
641 | 646 | break; |
... | ... | @@ -1181,12 +1186,12 @@ static void neon_store_reg(int reg, int pass, TCGv var) |
1181 | 1186 | dead_tmp(var); |
1182 | 1187 | } |
1183 | 1188 | |
1184 | -static inline void neon_load_reg64(TCGv var, int reg) | |
1189 | +static inline void neon_load_reg64(TCGv_i64 var, int reg) | |
1185 | 1190 | { |
1186 | 1191 | tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); |
1187 | 1192 | } |
1188 | 1193 | |
1189 | -static inline void neon_store_reg64(TCGv var, int reg) | |
1194 | +static inline void neon_store_reg64(TCGv_i64 var, int reg) | |
1190 | 1195 | { |
1191 | 1196 | tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); |
1192 | 1197 | } |
... | ... | @@ -1222,12 +1227,12 @@ static inline void gen_mov_vreg_F0(int dp, int reg) |
1222 | 1227 | |
1223 | 1228 | #define ARM_CP_RW_BIT (1 << 20) |
1224 | 1229 | |
1225 | -static inline void iwmmxt_load_reg(TCGv var, int reg) | |
1230 | +static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) | |
1226 | 1231 | { |
1227 | 1232 | tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); |
1228 | 1233 | } |
1229 | 1234 | |
1230 | -static inline void iwmmxt_store_reg(TCGv var, int reg) | |
1235 | +static inline void iwmmxt_store_reg(TCGv_i64 var, int reg) | |
1231 | 1236 | { |
1232 | 1237 | tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); |
1233 | 1238 | } |
... | ... | @@ -3907,7 +3912,7 @@ static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c) |
3907 | 3912 | tcg_gen_or_i32(dest, t, f); |
3908 | 3913 | } |
3909 | 3914 | |
3910 | -static inline void gen_neon_narrow(int size, TCGv dest, TCGv src) | |
3915 | +static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src) | |
3911 | 3916 | { |
3912 | 3917 | switch (size) { |
3913 | 3918 | case 0: gen_helper_neon_narrow_u8(dest, src); break; |
... | ... | @@ -3917,7 +3922,7 @@ static inline void gen_neon_narrow(int size, TCGv dest, TCGv src) |
3917 | 3922 | } |
3918 | 3923 | } |
3919 | 3924 | |
3920 | -static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv src) | |
3925 | +static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src) | |
3921 | 3926 | { |
3922 | 3927 | switch (size) { |
3923 | 3928 | case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break; |
... | ... | @@ -3927,7 +3932,7 @@ static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv src) |
3927 | 3932 | } |
3928 | 3933 | } |
3929 | 3934 | |
3930 | -static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv src) | |
3935 | +static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src) | |
3931 | 3936 | { |
3932 | 3937 | switch (size) { |
3933 | 3938 | case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break; |
... | ... | @@ -3971,7 +3976,7 @@ static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift, |
3971 | 3976 | } |
3972 | 3977 | } |
3973 | 3978 | |
3974 | -static inline void gen_neon_widen(TCGv dest, TCGv src, int size, int u) | |
3979 | +static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u) | |
3975 | 3980 | { |
3976 | 3981 | if (u) { |
3977 | 3982 | switch (size) { |
... | ... | @@ -4011,7 +4016,7 @@ static inline void gen_neon_subl(int size) |
4011 | 4016 | } |
4012 | 4017 | } |
4013 | 4018 | |
4014 | -static inline void gen_neon_negl(TCGv var, int size) | |
4019 | +static inline void gen_neon_negl(TCGv_i64 var, int size) | |
4015 | 4020 | { |
4016 | 4021 | switch (size) { |
4017 | 4022 | case 0: gen_helper_neon_negl_u16(var, var); break; |
... | ... | @@ -4021,7 +4026,7 @@ static inline void gen_neon_negl(TCGv var, int size) |
4021 | 4026 | } |
4022 | 4027 | } |
4023 | 4028 | |
4024 | -static inline void gen_neon_addl_saturate(TCGv op0, TCGv op1, int size) | |
4029 | +static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size) | |
4025 | 4030 | { |
4026 | 4031 | switch (size) { |
4027 | 4032 | case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break; |
... | ... | @@ -4030,9 +4035,9 @@ static inline void gen_neon_addl_saturate(TCGv op0, TCGv op1, int size) |
4030 | 4035 | } |
4031 | 4036 | } |
4032 | 4037 | |
4033 | -static inline void gen_neon_mull(TCGv dest, TCGv a, TCGv b, int size, int u) | |
4038 | +static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u) | |
4034 | 4039 | { |
4035 | - TCGv tmp; | |
4040 | + TCGv_i64 tmp; | |
4036 | 4041 | |
4037 | 4042 | switch ((size << 1) | u) { |
4038 | 4043 | case 0: gen_helper_neon_mull_s8(dest, a, b); break; |
... | ... | @@ -4076,6 +4081,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) |
4076 | 4081 | TCGv tmp; |
4077 | 4082 | TCGv tmp2; |
4078 | 4083 | TCGv tmp3; |
4084 | + TCGv_i64 tmp64; | |
4079 | 4085 | |
4080 | 4086 | if (!vfp_enabled(env)) |
4081 | 4087 | return 1; |
... | ... | @@ -4632,12 +4638,15 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) |
4632 | 4638 | imm = (uint16_t)shift; |
4633 | 4639 | imm |= imm << 16; |
4634 | 4640 | tmp2 = tcg_const_i32(imm); |
4641 | + TCGV_UNUSED_I64(tmp64); | |
4635 | 4642 | break; |
4636 | 4643 | case 2: |
4637 | 4644 | imm = (uint32_t)shift; |
4638 | 4645 | tmp2 = tcg_const_i32(imm); |
4646 | + TCGV_UNUSED_I64(tmp64); | |
4639 | 4647 | case 3: |
4640 | - tmp2 = tcg_const_i64(shift); | |
4648 | + tmp64 = tcg_const_i64(shift); | |
4649 | + TCGV_UNUSED(tmp2); | |
4641 | 4650 | break; |
4642 | 4651 | default: |
4643 | 4652 | abort(); |
... | ... | @@ -4648,14 +4657,14 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) |
4648 | 4657 | neon_load_reg64(cpu_V0, rm + pass); |
4649 | 4658 | if (q) { |
4650 | 4659 | if (u) |
4651 | - gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp2); | |
4660 | + gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64); | |
4652 | 4661 | else |
4653 | - gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp2); | |
4662 | + gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64); | |
4654 | 4663 | } else { |
4655 | 4664 | if (u) |
4656 | - gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp2); | |
4665 | + gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64); | |
4657 | 4666 | else |
4658 | - gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp2); | |
4667 | + gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64); | |
4659 | 4668 | } |
4660 | 4669 | } else { |
4661 | 4670 | tmp = neon_load_reg(rm + pass, 0); |
... | ... | @@ -5130,16 +5139,16 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) |
5130 | 5139 | neon_load_reg64(cpu_V1, rm); |
5131 | 5140 | } |
5132 | 5141 | } else if (q) { |
5133 | - tmp = tcg_temp_new(TCG_TYPE_I64); | |
5142 | + tmp64 = tcg_temp_new_i64(); | |
5134 | 5143 | if (imm < 8) { |
5135 | 5144 | neon_load_reg64(cpu_V0, rn); |
5136 | - neon_load_reg64(tmp, rn + 1); | |
5145 | + neon_load_reg64(tmp64, rn + 1); | |
5137 | 5146 | } else { |
5138 | 5147 | neon_load_reg64(cpu_V0, rn + 1); |
5139 | - neon_load_reg64(tmp, rm); | |
5148 | + neon_load_reg64(tmp64, rm); | |
5140 | 5149 | } |
5141 | 5150 | tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8); |
5142 | - tcg_gen_shli_i64(cpu_V1, tmp, 64 - ((imm & 7) * 8)); | |
5151 | + tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8)); | |
5143 | 5152 | tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); |
5144 | 5153 | if (imm < 8) { |
5145 | 5154 | neon_load_reg64(cpu_V1, rm); |
... | ... | @@ -5148,13 +5157,14 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) |
5148 | 5157 | imm -= 8; |
5149 | 5158 | } |
5150 | 5159 | tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8)); |
5151 | - tcg_gen_shri_i64(tmp, tmp, imm * 8); | |
5152 | - tcg_gen_or_i64(cpu_V1, cpu_V1, tmp); | |
5160 | + tcg_gen_shri_i64(tmp64, tmp64, imm * 8); | |
5161 | + tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64); | |
5153 | 5162 | } else { |
5163 | + /* BUGFIX */ | |
5154 | 5164 | neon_load_reg64(cpu_V0, rn); |
5155 | - tcg_gen_shri_i32(cpu_V0, cpu_V0, imm * 8); | |
5165 | + tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8); | |
5156 | 5166 | neon_load_reg64(cpu_V1, rm); |
5157 | - tcg_gen_shli_i32(cpu_V1, cpu_V1, 64 - (imm * 8)); | |
5167 | + tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8)); | |
5158 | 5168 | tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); |
5159 | 5169 | } |
5160 | 5170 | neon_store_reg64(cpu_V0, rd); |
... | ... | @@ -5578,7 +5588,7 @@ static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn) |
5578 | 5588 | |
5579 | 5589 | |
5580 | 5590 | /* Store a 64-bit value to a register pair. Clobbers val. */ |
5581 | -static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv val) | |
5591 | +static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) | |
5582 | 5592 | { |
5583 | 5593 | TCGv tmp; |
5584 | 5594 | tmp = new_tmp(); |
... | ... | @@ -5591,13 +5601,13 @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv val) |
5591 | 5601 | } |
5592 | 5602 | |
5593 | 5603 | /* load a 32-bit value from a register and perform a 64-bit accumulate. */ |
5594 | -static void gen_addq_lo(DisasContext *s, TCGv val, int rlow) | |
5604 | +static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow) | |
5595 | 5605 | { |
5596 | - TCGv tmp; | |
5606 | + TCGv_i64 tmp; | |
5597 | 5607 | TCGv tmp2; |
5598 | 5608 | |
5599 | 5609 | /* Load value and extend to 64 bits. */ |
5600 | - tmp = tcg_temp_new(TCG_TYPE_I64); | |
5610 | + tmp = tcg_temp_new_i64(); | |
5601 | 5611 | tmp2 = load_reg(s, rlow); |
5602 | 5612 | tcg_gen_extu_i32_i64(tmp, tmp2); |
5603 | 5613 | dead_tmp(tmp2); |
... | ... | @@ -5605,16 +5615,16 @@ static void gen_addq_lo(DisasContext *s, TCGv val, int rlow) |
5605 | 5615 | } |
5606 | 5616 | |
5607 | 5617 | /* load and add a 64-bit value from a register pair. */ |
5608 | -static void gen_addq(DisasContext *s, TCGv val, int rlow, int rhigh) | |
5618 | +static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) | |
5609 | 5619 | { |
5610 | - TCGv tmp; | |
5620 | + TCGv_i64 tmp; | |
5611 | 5621 | TCGv tmpl; |
5612 | 5622 | TCGv tmph; |
5613 | 5623 | |
5614 | 5624 | /* Load 64-bit value rd:rn. */ |
5615 | 5625 | tmpl = load_reg(s, rlow); |
5616 | 5626 | tmph = load_reg(s, rhigh); |
5617 | - tmp = tcg_temp_new(TCG_TYPE_I64); | |
5627 | + tmp = tcg_temp_new_i64(); | |
5618 | 5628 | tcg_gen_concat_i32_i64(tmp, tmpl, tmph); |
5619 | 5629 | dead_tmp(tmpl); |
5620 | 5630 | dead_tmp(tmph); |
... | ... | @@ -5622,7 +5632,7 @@ static void gen_addq(DisasContext *s, TCGv val, int rlow, int rhigh) |
5622 | 5632 | } |
5623 | 5633 | |
5624 | 5634 | /* Set N and Z flags from a 64-bit value. */ |
5625 | -static void gen_logicq_cc(TCGv val) | |
5635 | +static void gen_logicq_cc(TCGv_i64 val) | |
5626 | 5636 | { |
5627 | 5637 | TCGv tmp = new_tmp(); |
5628 | 5638 | gen_helper_logicq_cc(tmp, val); |
... | ... | @@ -5637,6 +5647,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) |
5637 | 5647 | TCGv tmp2; |
5638 | 5648 | TCGv tmp3; |
5639 | 5649 | TCGv addr; |
5650 | + TCGv_i64 tmp64; | |
5640 | 5651 | |
5641 | 5652 | insn = ldl_code(s->pc); |
5642 | 5653 | s->pc += 4; |
... | ... | @@ -5971,10 +5982,10 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) |
5971 | 5982 | tcg_gen_sari_i32(tmp2, tmp2, 16); |
5972 | 5983 | else |
5973 | 5984 | gen_sxth(tmp2); |
5974 | - tmp2 = gen_muls_i64_i32(tmp, tmp2); | |
5975 | - tcg_gen_shri_i64(tmp2, tmp2, 16); | |
5985 | + tmp64 = gen_muls_i64_i32(tmp, tmp2); | |
5986 | + tcg_gen_shri_i64(tmp64, tmp64, 16); | |
5976 | 5987 | tmp = new_tmp(); |
5977 | - tcg_gen_trunc_i64_i32(tmp, tmp2); | |
5988 | + tcg_gen_trunc_i64_i32(tmp, tmp64); | |
5978 | 5989 | if ((sh & 2) == 0) { |
5979 | 5990 | tmp2 = load_reg(s, rn); |
5980 | 5991 | gen_helper_add_setq(tmp, tmp, tmp2); |
... | ... | @@ -5988,11 +5999,11 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) |
5988 | 5999 | gen_mulxy(tmp, tmp2, sh & 2, sh & 4); |
5989 | 6000 | dead_tmp(tmp2); |
5990 | 6001 | if (op1 == 2) { |
5991 | - tmp2 = tcg_temp_new(TCG_TYPE_I64); | |
5992 | - tcg_gen_ext_i32_i64(tmp2, tmp); | |
6002 | + tmp64 = tcg_temp_new_i64(); | |
6003 | + tcg_gen_ext_i32_i64(tmp64, tmp); | |
5993 | 6004 | dead_tmp(tmp); |
5994 | - gen_addq(s, tmp2, rn, rd); | |
5995 | - gen_storeq_reg(s, rn, rd, tmp2); | |
6005 | + gen_addq(s, tmp64, rn, rd); | |
6006 | + gen_storeq_reg(s, rn, rd, tmp64); | |
5996 | 6007 | } else { |
5997 | 6008 | if (op1 == 0) { |
5998 | 6009 | tmp2 = load_reg(s, rn); |
... | ... | @@ -6205,19 +6216,19 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) |
6205 | 6216 | tmp = load_reg(s, rs); |
6206 | 6217 | tmp2 = load_reg(s, rm); |
6207 | 6218 | if (insn & (1 << 22)) |
6208 | - tmp = gen_muls_i64_i32(tmp, tmp2); | |
6219 | + tmp64 = gen_muls_i64_i32(tmp, tmp2); | |
6209 | 6220 | else |
6210 | - tmp = gen_mulu_i64_i32(tmp, tmp2); | |
6221 | + tmp64 = gen_mulu_i64_i32(tmp, tmp2); | |
6211 | 6222 | if (insn & (1 << 21)) /* mult accumulate */ |
6212 | - gen_addq(s, tmp, rn, rd); | |
6223 | + gen_addq(s, tmp64, rn, rd); | |
6213 | 6224 | if (!(insn & (1 << 23))) { /* double accumulate */ |
6214 | 6225 | ARCH(6); |
6215 | - gen_addq_lo(s, tmp, rn); | |
6216 | - gen_addq_lo(s, tmp, rd); | |
6226 | + gen_addq_lo(s, tmp64, rn); | |
6227 | + gen_addq_lo(s, tmp64, rd); | |
6217 | 6228 | } |
6218 | 6229 | if (insn & (1 << 20)) |
6219 | - gen_logicq_cc(tmp); | |
6220 | - gen_storeq_reg(s, rn, rd, tmp); | |
6230 | + gen_logicq_cc(tmp64); | |
6231 | + gen_storeq_reg(s, rn, rd, tmp64); | |
6221 | 6232 | break; |
6222 | 6233 | } |
6223 | 6234 | } else { |
... | ... | @@ -6515,12 +6526,12 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) |
6515 | 6526 | tmp2 = load_reg(s, rs); |
6516 | 6527 | if (insn & (1 << 20)) { |
6517 | 6528 | /* Signed multiply most significant [accumulate]. */ |
6518 | - tmp2 = gen_muls_i64_i32(tmp, tmp2); | |
6529 | + tmp64 = gen_muls_i64_i32(tmp, tmp2); | |
6519 | 6530 | if (insn & (1 << 5)) |
6520 | - tcg_gen_addi_i64(tmp2, tmp2, 0x80000000u); | |
6521 | - tcg_gen_shri_i64(tmp2, tmp2, 32); | |
6531 | + tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u); | |
6532 | + tcg_gen_shri_i64(tmp64, tmp64, 32); | |
6522 | 6533 | tmp = new_tmp(); |
6523 | - tcg_gen_trunc_i64_i32(tmp, tmp2); | |
6534 | + tcg_gen_trunc_i64_i32(tmp, tmp64); | |
6524 | 6535 | if (rn != 15) { |
6525 | 6536 | tmp2 = load_reg(s, rn); |
6526 | 6537 | if (insn & (1 << 6)) { |
... | ... | @@ -6544,11 +6555,11 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) |
6544 | 6555 | dead_tmp(tmp2); |
6545 | 6556 | if (insn & (1 << 22)) { |
6546 | 6557 | /* smlald, smlsld */ |
6547 | - tmp2 = tcg_temp_new(TCG_TYPE_I64); | |
6548 | - tcg_gen_ext_i32_i64(tmp2, tmp); | |
6558 | + tmp64 = tcg_temp_new_i64(); | |
6559 | + tcg_gen_ext_i32_i64(tmp64, tmp); | |
6549 | 6560 | dead_tmp(tmp); |
6550 | - gen_addq(s, tmp2, rd, rn); | |
6551 | - gen_storeq_reg(s, rd, rn, tmp2); | |
6561 | + gen_addq(s, tmp64, rd, rn); | |
6562 | + gen_storeq_reg(s, rd, rn, tmp64); | |
6552 | 6563 | } else { |
6553 | 6564 | /* smuad, smusd, smlad, smlsd */ |
6554 | 6565 | if (rd != 15) |
... | ... | @@ -6917,6 +6928,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) |
6917 | 6928 | TCGv tmp2; |
6918 | 6929 | TCGv tmp3; |
6919 | 6930 | TCGv addr; |
6931 | + TCGv_i64 tmp64; | |
6920 | 6932 | int op; |
6921 | 6933 | int shiftop; |
6922 | 6934 | int conds; |
... | ... | @@ -7393,10 +7405,10 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) |
7393 | 7405 | tcg_gen_sari_i32(tmp2, tmp2, 16); |
7394 | 7406 | else |
7395 | 7407 | gen_sxth(tmp2); |
7396 | - tmp2 = gen_muls_i64_i32(tmp, tmp2); | |
7397 | - tcg_gen_shri_i64(tmp2, tmp2, 16); | |
7408 | + tmp64 = gen_muls_i64_i32(tmp, tmp2); | |
7409 | + tcg_gen_shri_i64(tmp64, tmp64, 16); | |
7398 | 7410 | tmp = new_tmp(); |
7399 | - tcg_gen_trunc_i64_i32(tmp, tmp2); | |
7411 | + tcg_gen_trunc_i64_i32(tmp, tmp64); | |
7400 | 7412 | if (rs != 15) |
7401 | 7413 | { |
7402 | 7414 | tmp2 = load_reg(s, rs); |
... | ... | @@ -7460,36 +7472,38 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) |
7460 | 7472 | tcg_gen_add_i32(tmp, tmp, tmp2); |
7461 | 7473 | } |
7462 | 7474 | dead_tmp(tmp2); |
7463 | - tmp2 = tcg_temp_new(TCG_TYPE_I64); | |
7464 | - gen_addq(s, tmp, rs, rd); | |
7465 | - gen_storeq_reg(s, rs, rd, tmp); | |
7475 | + /* BUGFIX */ | |
7476 | + tmp64 = tcg_temp_new_i64(); | |
7477 | + tcg_gen_ext_i32_i64(tmp64, tmp); | |
7478 | + dead_tmp(tmp); | |
7479 | + gen_addq(s, tmp64, rs, rd); | |
7480 | + gen_storeq_reg(s, rs, rd, tmp64); | |
7466 | 7481 | } else { |
7467 | 7482 | if (op & 0x20) { |
7468 | 7483 | /* Unsigned 64-bit multiply */ |
7469 | - tmp = gen_mulu_i64_i32(tmp, tmp2); | |
7484 | + tmp64 = gen_mulu_i64_i32(tmp, tmp2); | |
7470 | 7485 | } else { |
7471 | 7486 | if (op & 8) { |
7472 | 7487 | /* smlalxy */ |
7473 | 7488 | gen_mulxy(tmp, tmp2, op & 2, op & 1); |
7474 | 7489 | dead_tmp(tmp2); |
7475 | - tmp2 = tcg_temp_new(TCG_TYPE_I64); | |
7476 | - tcg_gen_ext_i32_i64(tmp2, tmp); | |
7490 | + tmp64 = tcg_temp_new_i64(); | |
7491 | + tcg_gen_ext_i32_i64(tmp64, tmp); | |
7477 | 7492 | dead_tmp(tmp); |
7478 | - tmp = tmp2; | |
7479 | 7493 | } else { |
7480 | 7494 | /* Signed 64-bit multiply */ |
7481 | - tmp = gen_muls_i64_i32(tmp, tmp2); | |
7495 | + tmp64 = gen_muls_i64_i32(tmp, tmp2); | |
7482 | 7496 | } |
7483 | 7497 | } |
7484 | 7498 | if (op & 4) { |
7485 | 7499 | /* umaal */ |
7486 | - gen_addq_lo(s, tmp, rs); | |
7487 | - gen_addq_lo(s, tmp, rd); | |
7500 | + gen_addq_lo(s, tmp64, rs); | |
7501 | + gen_addq_lo(s, tmp64, rd); | |
7488 | 7502 | } else if (op & 0x40) { |
7489 | 7503 | /* 64-bit accumulate. */ |
7490 | - gen_addq(s, tmp, rs, rd); | |
7504 | + gen_addq(s, tmp64, rs, rd); | |
7491 | 7505 | } |
7492 | - gen_storeq_reg(s, rs, rd, tmp); | |
7506 | + gen_storeq_reg(s, rs, rd, tmp64); | |
7493 | 7507 | } |
7494 | 7508 | break; |
7495 | 7509 | } |
... | ... | @@ -8618,14 +8632,14 @@ static inline void gen_intermediate_code_internal(CPUState *env, |
8618 | 8632 | dc->user = (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR; |
8619 | 8633 | } |
8620 | 8634 | #endif |
8621 | - cpu_F0s = tcg_temp_new(TCG_TYPE_I32); | |
8622 | - cpu_F1s = tcg_temp_new(TCG_TYPE_I32); | |
8623 | - cpu_F0d = tcg_temp_new(TCG_TYPE_I64); | |
8624 | - cpu_F1d = tcg_temp_new(TCG_TYPE_I64); | |
8635 | + cpu_F0s = tcg_temp_new_i32(); | |
8636 | + cpu_F1s = tcg_temp_new_i32(); | |
8637 | + cpu_F0d = tcg_temp_new_i64(); | |
8638 | + cpu_F1d = tcg_temp_new_i64(); | |
8625 | 8639 | cpu_V0 = cpu_F0d; |
8626 | 8640 | cpu_V1 = cpu_F1d; |
8627 | 8641 | /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ |
8628 | - cpu_M0 = tcg_temp_new(TCG_TYPE_I64); | |
8642 | + cpu_M0 = tcg_temp_new_i64(); | |
8629 | 8643 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
8630 | 8644 | lj = -1; |
8631 | 8645 | num_insns = 0; | ... | ... |
target-cris/helper.h
1 | -#define TCG_HELPER_PROTO | |
1 | +#include "def-helper.h" | |
2 | 2 | |
3 | -void TCG_HELPER_PROTO helper_raise_exception(uint32_t index); | |
4 | -void TCG_HELPER_PROTO helper_tlb_flush_pid(uint32_t pid); | |
5 | -void TCG_HELPER_PROTO helper_spc_write(uint32_t pid); | |
6 | -void TCG_HELPER_PROTO helper_dump(uint32_t a0, uint32_t a1, uint32_t a2); | |
7 | -void TCG_HELPER_PROTO helper_rfe(void); | |
8 | -void TCG_HELPER_PROTO helper_rfn(void); | |
3 | +DEF_HELPER_1(raise_exception, void, i32) | |
4 | +DEF_HELPER_1(tlb_flush_pid, void, i32) | |
5 | +DEF_HELPER_1(spc_write, void, i32) | |
6 | +DEF_HELPER_3(dump, void, i32, i32, i32) | |
7 | +DEF_HELPER_0(rfe, void); | |
8 | +DEF_HELPER_0(rfn, void); | |
9 | 9 | |
10 | -void TCG_HELPER_PROTO helper_movl_sreg_reg (uint32_t sreg, uint32_t reg); | |
11 | -void TCG_HELPER_PROTO helper_movl_reg_sreg (uint32_t reg, uint32_t sreg); | |
10 | +DEF_HELPER_2(movl_sreg_reg, void, i32, i32) | |
11 | +DEF_HELPER_2(movl_reg_sreg, void, i32, i32) | |
12 | 12 | |
13 | -void TCG_HELPER_PROTO helper_evaluate_flags_muls(void); | |
14 | -void TCG_HELPER_PROTO helper_evaluate_flags_mulu(void); | |
15 | -void TCG_HELPER_PROTO helper_evaluate_flags_mcp(void); | |
16 | -void TCG_HELPER_PROTO helper_evaluate_flags_alu_4(void); | |
17 | -void TCG_HELPER_PROTO helper_evaluate_flags_move_4 (void); | |
18 | -void TCG_HELPER_PROTO helper_evaluate_flags_move_2 (void); | |
19 | -void TCG_HELPER_PROTO helper_evaluate_flags (void); | |
20 | -void TCG_HELPER_PROTO helper_top_evaluate_flags(void); | |
13 | +DEF_HELPER_0(evaluate_flags_muls, void) | |
14 | +DEF_HELPER_0(evaluate_flags_mulu, void) | |
15 | +DEF_HELPER_0(evaluate_flags_mcp, void) | |
16 | +DEF_HELPER_0(evaluate_flags_alu_4, void) | |
17 | +DEF_HELPER_0(evaluate_flags_move_4, void) | |
18 | +DEF_HELPER_0(evaluate_flags_move_2, void) | |
19 | +DEF_HELPER_0(evaluate_flags, void) | |
20 | +DEF_HELPER_0(top_evaluate_flags, void) | |
21 | + | |
22 | +#include "def-helper.h" | ... | ... |
target-cris/translate.c
... | ... | @@ -39,6 +39,9 @@ |
39 | 39 | #include "crisv32-decode.h" |
40 | 40 | #include "qemu-common.h" |
41 | 41 | |
42 | +#define GEN_HELPER 1 | |
43 | +#include "helper.h" | |
44 | + | |
42 | 45 | #define DISAS_CRIS 0 |
43 | 46 | #if DISAS_CRIS |
44 | 47 | #define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x |
... | ... | @@ -61,7 +64,7 @@ |
61 | 64 | #define CC_MASK_NZVC 0xf |
62 | 65 | #define CC_MASK_RNZV 0x10e |
63 | 66 | |
64 | -static TCGv cpu_env; | |
67 | +static TCGv_ptr cpu_env; | |
65 | 68 | static TCGv cpu_R[16]; |
66 | 69 | static TCGv cpu_PR[16]; |
67 | 70 | static TCGv cc_x; |
... | ... | @@ -212,9 +215,9 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn) |
212 | 215 | tcg_gen_andi_tl(cpu_PR[r], tn, 3); |
213 | 216 | else { |
214 | 217 | if (r == PR_PID) |
215 | - tcg_gen_helper_0_1(helper_tlb_flush_pid, tn); | |
218 | + gen_helper_tlb_flush_pid(tn); | |
216 | 219 | if (dc->tb_flags & S_FLAG && r == PR_SPC) |
217 | - tcg_gen_helper_0_1(helper_spc_write, tn); | |
220 | + gen_helper_spc_write(tn); | |
218 | 221 | else if (r == PR_CCS) |
219 | 222 | dc->cpustate_changed = 1; |
220 | 223 | tcg_gen_mov_tl(cpu_PR[r], tn); |
... | ... | @@ -223,14 +226,16 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn) |
223 | 226 | |
224 | 227 | static inline void t_gen_raise_exception(uint32_t index) |
225 | 228 | { |
226 | - tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index)); | |
229 | + TCGv_i32 tmp = tcg_const_i32(index); | |
230 | + gen_helper_raise_exception(tmp); | |
231 | + tcg_temp_free_i32(tmp); | |
227 | 232 | } |
228 | 233 | |
229 | 234 | static void t_gen_lsl(TCGv d, TCGv a, TCGv b) |
230 | 235 | { |
231 | 236 | TCGv t0, t_31; |
232 | 237 | |
233 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
238 | + t0 = tcg_temp_new(); | |
234 | 239 | t_31 = tcg_const_tl(31); |
235 | 240 | tcg_gen_shl_tl(d, a, b); |
236 | 241 | |
... | ... | @@ -246,8 +251,8 @@ static void t_gen_lsr(TCGv d, TCGv a, TCGv b) |
246 | 251 | { |
247 | 252 | TCGv t0, t_31; |
248 | 253 | |
249 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
250 | - t_31 = tcg_temp_new(TCG_TYPE_TL); | |
254 | + t0 = tcg_temp_new(); | |
255 | + t_31 = tcg_temp_new(); | |
251 | 256 | tcg_gen_shr_tl(d, a, b); |
252 | 257 | |
253 | 258 | tcg_gen_movi_tl(t_31, 31); |
... | ... | @@ -263,8 +268,8 @@ static void t_gen_asr(TCGv d, TCGv a, TCGv b) |
263 | 268 | { |
264 | 269 | TCGv t0, t_31; |
265 | 270 | |
266 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
267 | - t_31 = tcg_temp_new(TCG_TYPE_TL); | |
271 | + t0 = tcg_temp_new(); | |
272 | + t_31 = tcg_temp_new(); | |
268 | 273 | tcg_gen_sar_tl(d, a, b); |
269 | 274 | |
270 | 275 | tcg_gen_movi_tl(t_31, 31); |
... | ... | @@ -278,30 +283,30 @@ static void t_gen_asr(TCGv d, TCGv a, TCGv b) |
278 | 283 | /* 64-bit signed mul, lower result in d and upper in d2. */ |
279 | 284 | static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b) |
280 | 285 | { |
281 | - TCGv t0, t1; | |
286 | + TCGv_i64 t0, t1; | |
282 | 287 | |
283 | - t0 = tcg_temp_new(TCG_TYPE_I64); | |
284 | - t1 = tcg_temp_new(TCG_TYPE_I64); | |
288 | + t0 = tcg_temp_new_i64(); | |
289 | + t1 = tcg_temp_new_i64(); | |
285 | 290 | |
286 | - tcg_gen_ext32s_i64(t0, a); | |
287 | - tcg_gen_ext32s_i64(t1, b); | |
291 | + tcg_gen_ext_i32_i64(t0, a); | |
292 | + tcg_gen_ext_i32_i64(t1, b); | |
288 | 293 | tcg_gen_mul_i64(t0, t0, t1); |
289 | 294 | |
290 | 295 | tcg_gen_trunc_i64_i32(d, t0); |
291 | 296 | tcg_gen_shri_i64(t0, t0, 32); |
292 | 297 | tcg_gen_trunc_i64_i32(d2, t0); |
293 | 298 | |
294 | - tcg_temp_free(t0); | |
295 | - tcg_temp_free(t1); | |
299 | + tcg_temp_free_i64(t0); | |
300 | + tcg_temp_free_i64(t1); | |
296 | 301 | } |
297 | 302 | |
298 | 303 | /* 64-bit unsigned muls, lower result in d and upper in d2. */ |
299 | 304 | static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b) |
300 | 305 | { |
301 | - TCGv t0, t1; | |
306 | + TCGv_i64 t0, t1; | |
302 | 307 | |
303 | - t0 = tcg_temp_new(TCG_TYPE_I64); | |
304 | - t1 = tcg_temp_new(TCG_TYPE_I64); | |
308 | + t0 = tcg_temp_new_i64(); | |
309 | + t1 = tcg_temp_new_i64(); | |
305 | 310 | |
306 | 311 | tcg_gen_extu_i32_i64(t0, a); |
307 | 312 | tcg_gen_extu_i32_i64(t1, b); |
... | ... | @@ -311,18 +316,18 @@ static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b) |
311 | 316 | tcg_gen_shri_i64(t0, t0, 32); |
312 | 317 | tcg_gen_trunc_i64_i32(d2, t0); |
313 | 318 | |
314 | - tcg_temp_free(t0); | |
315 | - tcg_temp_free(t1); | |
319 | + tcg_temp_free_i64(t0); | |
320 | + tcg_temp_free_i64(t1); | |
316 | 321 | } |
317 | 322 | |
318 | 323 | /* 32bit branch-free binary search for counting leading zeros. */ |
319 | 324 | static void t_gen_lz_i32(TCGv d, TCGv x) |
320 | 325 | { |
321 | - TCGv y, m, n; | |
326 | + TCGv_i32 y, m, n; | |
322 | 327 | |
323 | - y = tcg_temp_new(TCG_TYPE_I32); | |
324 | - m = tcg_temp_new(TCG_TYPE_I32); | |
325 | - n = tcg_temp_new(TCG_TYPE_I32); | |
328 | + y = tcg_temp_new_i32(); | |
329 | + m = tcg_temp_new_i32(); | |
330 | + n = tcg_temp_new_i32(); | |
326 | 331 | |
327 | 332 | /* y = -(x >> 16) */ |
328 | 333 | tcg_gen_shri_i32(y, x, 16); |
... | ... | @@ -413,9 +418,9 @@ static void t_gen_btst(TCGv d, TCGv a, TCGv b) |
413 | 418 | */ |
414 | 419 | |
415 | 420 | l1 = gen_new_label(); |
416 | - sbit = tcg_temp_new(TCG_TYPE_TL); | |
417 | - bset = tcg_temp_new(TCG_TYPE_TL); | |
418 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
421 | + sbit = tcg_temp_new(); | |
422 | + bset = tcg_temp_new(); | |
423 | + t0 = tcg_temp_new(); | |
419 | 424 | |
420 | 425 | /* Compute bset and sbit. */ |
421 | 426 | tcg_gen_andi_tl(sbit, b, 31); |
... | ... | @@ -463,7 +468,7 @@ static inline void t_gen_add_flag(TCGv d, int flag) |
463 | 468 | { |
464 | 469 | TCGv c; |
465 | 470 | |
466 | - c = tcg_temp_new(TCG_TYPE_TL); | |
471 | + c = tcg_temp_new(); | |
467 | 472 | t_gen_mov_TN_preg(c, PR_CCS); |
468 | 473 | /* Propagate carry into d. */ |
469 | 474 | tcg_gen_andi_tl(c, c, 1 << flag); |
... | ... | @@ -479,7 +484,7 @@ static inline void t_gen_addx_carry(DisasContext *dc, TCGv d) |
479 | 484 | if (dc->flags_x) { |
480 | 485 | TCGv c; |
481 | 486 | |
482 | - c = tcg_temp_new(TCG_TYPE_TL); | |
487 | + c = tcg_temp_new(); | |
483 | 488 | t_gen_mov_TN_preg(c, PR_CCS); |
484 | 489 | /* C flag is already at bit 0. */ |
485 | 490 | tcg_gen_andi_tl(c, c, C_FLAG); |
... | ... | @@ -489,8 +494,8 @@ static inline void t_gen_addx_carry(DisasContext *dc, TCGv d) |
489 | 494 | } else { |
490 | 495 | TCGv x, c; |
491 | 496 | |
492 | - x = tcg_temp_new(TCG_TYPE_TL); | |
493 | - c = tcg_temp_new(TCG_TYPE_TL); | |
497 | + x = tcg_temp_new(); | |
498 | + c = tcg_temp_new(); | |
494 | 499 | t_gen_mov_TN_preg(x, PR_CCS); |
495 | 500 | tcg_gen_mov_tl(c, x); |
496 | 501 | |
... | ... | @@ -512,7 +517,7 @@ static inline void t_gen_subx_carry(DisasContext *dc, TCGv d) |
512 | 517 | if (dc->flags_x) { |
513 | 518 | TCGv c; |
514 | 519 | |
515 | - c = tcg_temp_new(TCG_TYPE_TL); | |
520 | + c = tcg_temp_new(); | |
516 | 521 | t_gen_mov_TN_preg(c, PR_CCS); |
517 | 522 | /* C flag is already at bit 0. */ |
518 | 523 | tcg_gen_andi_tl(c, c, C_FLAG); |
... | ... | @@ -522,8 +527,8 @@ static inline void t_gen_subx_carry(DisasContext *dc, TCGv d) |
522 | 527 | } else { |
523 | 528 | TCGv x, c; |
524 | 529 | |
525 | - x = tcg_temp_new(TCG_TYPE_TL); | |
526 | - c = tcg_temp_new(TCG_TYPE_TL); | |
530 | + x = tcg_temp_new(); | |
531 | + c = tcg_temp_new(); | |
527 | 532 | t_gen_mov_TN_preg(x, PR_CCS); |
528 | 533 | tcg_gen_mov_tl(c, x); |
529 | 534 | |
... | ... | @@ -545,8 +550,8 @@ static inline void t_gen_swapb(TCGv d, TCGv s) |
545 | 550 | { |
546 | 551 | TCGv t, org_s; |
547 | 552 | |
548 | - t = tcg_temp_new(TCG_TYPE_TL); | |
549 | - org_s = tcg_temp_new(TCG_TYPE_TL); | |
553 | + t = tcg_temp_new(); | |
554 | + org_s = tcg_temp_new(); | |
550 | 555 | |
551 | 556 | /* d and s may refer to the same object. */ |
552 | 557 | tcg_gen_mov_tl(org_s, s); |
... | ... | @@ -564,7 +569,7 @@ static inline void t_gen_swapw(TCGv d, TCGv s) |
564 | 569 | { |
565 | 570 | TCGv t; |
566 | 571 | /* d and s refer the same object. */ |
567 | - t = tcg_temp_new(TCG_TYPE_TL); | |
572 | + t = tcg_temp_new(); | |
568 | 573 | tcg_gen_mov_tl(t, s); |
569 | 574 | tcg_gen_shli_tl(d, t, 16); |
570 | 575 | tcg_gen_shri_tl(t, t, 16); |
... | ... | @@ -601,8 +606,8 @@ static inline void t_gen_swapr(TCGv d, TCGv s) |
601 | 606 | TCGv t, org_s; |
602 | 607 | |
603 | 608 | /* d and s refer the same object. */ |
604 | - t = tcg_temp_new(TCG_TYPE_TL); | |
605 | - org_s = tcg_temp_new(TCG_TYPE_TL); | |
609 | + t = tcg_temp_new(); | |
610 | + org_s = tcg_temp_new(); | |
606 | 611 | tcg_gen_mov_tl(org_s, s); |
607 | 612 | |
608 | 613 | tcg_gen_shli_tl(t, org_s, bitrev[0].shift); |
... | ... | @@ -626,7 +631,7 @@ static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false) |
626 | 631 | int l1; |
627 | 632 | |
628 | 633 | l1 = gen_new_label(); |
629 | - btaken = tcg_temp_new(TCG_TYPE_TL); | |
634 | + btaken = tcg_temp_new(); | |
630 | 635 | |
631 | 636 | /* Conditional jmp. */ |
632 | 637 | tcg_gen_mov_tl(btaken, env_btaken); |
... | ... | @@ -692,13 +697,13 @@ static void cris_evaluate_flags(DisasContext *dc) |
692 | 697 | switch (dc->cc_op) |
693 | 698 | { |
694 | 699 | case CC_OP_MCP: |
695 | - tcg_gen_helper_0_0(helper_evaluate_flags_mcp); | |
700 | + gen_helper_evaluate_flags_mcp(); | |
696 | 701 | break; |
697 | 702 | case CC_OP_MULS: |
698 | - tcg_gen_helper_0_0(helper_evaluate_flags_muls); | |
703 | + gen_helper_evaluate_flags_muls(); | |
699 | 704 | break; |
700 | 705 | case CC_OP_MULU: |
701 | - tcg_gen_helper_0_0(helper_evaluate_flags_mulu); | |
706 | + gen_helper_evaluate_flags_mulu(); | |
702 | 707 | break; |
703 | 708 | case CC_OP_MOVE: |
704 | 709 | case CC_OP_AND: |
... | ... | @@ -710,13 +715,13 @@ static void cris_evaluate_flags(DisasContext *dc) |
710 | 715 | switch (dc->cc_size) |
711 | 716 | { |
712 | 717 | case 4: |
713 | - tcg_gen_helper_0_0(helper_evaluate_flags_move_4); | |
718 | + gen_helper_evaluate_flags_move_4(); | |
714 | 719 | break; |
715 | 720 | case 2: |
716 | - tcg_gen_helper_0_0(helper_evaluate_flags_move_2); | |
721 | + gen_helper_evaluate_flags_move_2(); | |
717 | 722 | break; |
718 | 723 | default: |
719 | - tcg_gen_helper_0_0(helper_evaluate_flags); | |
724 | + gen_helper_evaluate_flags(); | |
720 | 725 | break; |
721 | 726 | } |
722 | 727 | break; |
... | ... | @@ -728,10 +733,10 @@ static void cris_evaluate_flags(DisasContext *dc) |
728 | 733 | switch (dc->cc_size) |
729 | 734 | { |
730 | 735 | case 4: |
731 | - tcg_gen_helper_0_0(helper_evaluate_flags_alu_4); | |
736 | + gen_helper_evaluate_flags_alu_4(); | |
732 | 737 | break; |
733 | 738 | default: |
734 | - tcg_gen_helper_0_0(helper_evaluate_flags); | |
739 | + gen_helper_evaluate_flags(); | |
735 | 740 | break; |
736 | 741 | } |
737 | 742 | } |
... | ... | @@ -927,16 +932,16 @@ static void cris_alu(DisasContext *dc, int op, |
927 | 932 | writeback = 1; |
928 | 933 | |
929 | 934 | if (op == CC_OP_BOUND || op == CC_OP_BTST) |
930 | - tmp = tcg_temp_local_new(TCG_TYPE_TL); | |
935 | + tmp = tcg_temp_local_new(); | |
931 | 936 | |
932 | 937 | if (op == CC_OP_CMP) { |
933 | - tmp = tcg_temp_new(TCG_TYPE_TL); | |
938 | + tmp = tcg_temp_new(); | |
934 | 939 | writeback = 0; |
935 | 940 | } else if (size == 4) { |
936 | 941 | tmp = d; |
937 | 942 | writeback = 0; |
938 | 943 | } else |
939 | - tmp = tcg_temp_new(TCG_TYPE_TL); | |
944 | + tmp = tcg_temp_new(); | |
940 | 945 | |
941 | 946 | |
942 | 947 | cris_pre_alu_update_cc(dc, op, op_a, op_b, size); |
... | ... | @@ -951,7 +956,7 @@ static void cris_alu(DisasContext *dc, int op, |
951 | 956 | tcg_gen_andi_tl(d, d, ~0xffff); |
952 | 957 | tcg_gen_or_tl(d, d, tmp); |
953 | 958 | } |
954 | - if (GET_TCGV(tmp) != GET_TCGV(d)) | |
959 | + if (!TCGV_EQUAL(tmp, d)) | |
955 | 960 | tcg_temp_free(tmp); |
956 | 961 | } |
957 | 962 | |
... | ... | @@ -1088,7 +1093,7 @@ static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond) |
1088 | 1093 | { |
1089 | 1094 | TCGv tmp; |
1090 | 1095 | |
1091 | - tmp = tcg_temp_new(TCG_TYPE_TL); | |
1096 | + tmp = tcg_temp_new(); | |
1092 | 1097 | tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS], |
1093 | 1098 | C_FLAG | Z_FLAG); |
1094 | 1099 | /* Overlay the C flag on top of the Z. */ |
... | ... | @@ -1121,8 +1126,8 @@ static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond) |
1121 | 1126 | { |
1122 | 1127 | TCGv n, z; |
1123 | 1128 | |
1124 | - n = tcg_temp_new(TCG_TYPE_TL); | |
1125 | - z = tcg_temp_new(TCG_TYPE_TL); | |
1129 | + n = tcg_temp_new(); | |
1130 | + z = tcg_temp_new(); | |
1126 | 1131 | |
1127 | 1132 | /* To avoid a shift we overlay everything on |
1128 | 1133 | the V flag. */ |
... | ... | @@ -1145,8 +1150,8 @@ static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond) |
1145 | 1150 | { |
1146 | 1151 | TCGv n, z; |
1147 | 1152 | |
1148 | - n = tcg_temp_new(TCG_TYPE_TL); | |
1149 | - z = tcg_temp_new(TCG_TYPE_TL); | |
1153 | + n = tcg_temp_new(); | |
1154 | + z = tcg_temp_new(); | |
1150 | 1155 | |
1151 | 1156 | /* To avoid a shift we overlay everything on |
1152 | 1157 | the V flag. */ |
... | ... | @@ -1215,6 +1220,18 @@ static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type) |
1215 | 1220 | tcg_gen_movi_tl(env_btaken, 1); |
1216 | 1221 | } |
1217 | 1222 | |
1223 | +static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr) | |
1224 | +{ | |
1225 | + int mem_index = cpu_mmu_index(dc->env); | |
1226 | + | |
1227 | + /* If we get a fault on a delayslot we must keep the jmp state in | |
1228 | + the cpu-state to be able to re-execute the jmp. */ | |
1229 | + if (dc->delayed_branch == 1) | |
1230 | + cris_store_direct_jmp(dc); | |
1231 | + | |
1232 | + tcg_gen_qemu_ld64(dst, addr, mem_index); | |
1233 | +} | |
1234 | + | |
1218 | 1235 | static void gen_load(DisasContext *dc, TCGv dst, TCGv addr, |
1219 | 1236 | unsigned int size, int sign) |
1220 | 1237 | { |
... | ... | @@ -1240,8 +1257,8 @@ static void gen_load(DisasContext *dc, TCGv dst, TCGv addr, |
1240 | 1257 | else if (size == 4) { |
1241 | 1258 | tcg_gen_qemu_ld32u(dst, addr, mem_index); |
1242 | 1259 | } |
1243 | - else if (size == 8) { | |
1244 | - tcg_gen_qemu_ld64(dst, addr, mem_index); | |
1260 | + else { | |
1261 | + abort(); | |
1245 | 1262 | } |
1246 | 1263 | } |
1247 | 1264 | |
... | ... | @@ -1284,7 +1301,7 @@ static inline void t_gen_sext(TCGv d, TCGv s, int size) |
1284 | 1301 | tcg_gen_ext8s_i32(d, s); |
1285 | 1302 | else if (size == 2) |
1286 | 1303 | tcg_gen_ext16s_i32(d, s); |
1287 | - else if(GET_TCGV(d) != GET_TCGV(s)) | |
1304 | + else if(!TCGV_EQUAL(d, s)) | |
1288 | 1305 | tcg_gen_mov_tl(d, s); |
1289 | 1306 | } |
1290 | 1307 | |
... | ... | @@ -1294,7 +1311,7 @@ static inline void t_gen_zext(TCGv d, TCGv s, int size) |
1294 | 1311 | tcg_gen_ext8u_i32(d, s); |
1295 | 1312 | else if (size == 2) |
1296 | 1313 | tcg_gen_ext16u_i32(d, s); |
1297 | - else if (GET_TCGV(d) != GET_TCGV(s)) | |
1314 | + else if (!TCGV_EQUAL(d, s)) | |
1298 | 1315 | tcg_gen_mov_tl(d, s); |
1299 | 1316 | } |
1300 | 1317 | |
... | ... | @@ -1546,7 +1563,7 @@ static unsigned int dec_btstq(DisasContext *dc) |
1546 | 1563 | DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2)); |
1547 | 1564 | |
1548 | 1565 | cris_cc_mask(dc, CC_MASK_NZ); |
1549 | - l0 = tcg_temp_local_new(TCG_TYPE_TL); | |
1566 | + l0 = tcg_temp_local_new(); | |
1550 | 1567 | cris_alu(dc, CC_OP_BTST, |
1551 | 1568 | l0, cpu_R[dc->op2], tcg_const_tl(dc->op1), 4); |
1552 | 1569 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
... | ... | @@ -1613,7 +1630,7 @@ static unsigned int dec_move_r(DisasContext *dc) |
1613 | 1630 | else { |
1614 | 1631 | TCGv t0; |
1615 | 1632 | |
1616 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
1633 | + t0 = tcg_temp_new(); | |
1617 | 1634 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); |
1618 | 1635 | cris_alu(dc, CC_OP_MOVE, |
1619 | 1636 | cpu_R[dc->op2], |
... | ... | @@ -1653,8 +1670,8 @@ static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t) |
1653 | 1670 | t[0] = cpu_R[dc->op2]; |
1654 | 1671 | t[1] = cpu_R[dc->op1]; |
1655 | 1672 | } else { |
1656 | - t[0] = tcg_temp_new(TCG_TYPE_TL); | |
1657 | - t[1] = tcg_temp_new(TCG_TYPE_TL); | |
1673 | + t[0] = tcg_temp_new(); | |
1674 | + t[1] = tcg_temp_new(); | |
1658 | 1675 | } |
1659 | 1676 | } |
1660 | 1677 | |
... | ... | @@ -1689,7 +1706,7 @@ static unsigned int dec_lz_r(DisasContext *dc) |
1689 | 1706 | DIS(fprintf (logfile, "lz $r%u, $r%u\n", |
1690 | 1707 | dc->op1, dc->op2)); |
1691 | 1708 | cris_cc_mask(dc, CC_MASK_NZ); |
1692 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
1709 | + t0 = tcg_temp_new(); | |
1693 | 1710 | dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0); |
1694 | 1711 | cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
1695 | 1712 | tcg_temp_free(t0); |
... | ... | @@ -1812,7 +1829,7 @@ static unsigned int dec_bound_r(DisasContext *dc) |
1812 | 1829 | DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n", |
1813 | 1830 | memsize_char(size), dc->op1, dc->op2)); |
1814 | 1831 | cris_cc_mask(dc, CC_MASK_NZ); |
1815 | - l0 = tcg_temp_local_new(TCG_TYPE_TL); | |
1832 | + l0 = tcg_temp_local_new(); | |
1816 | 1833 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0); |
1817 | 1834 | cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4); |
1818 | 1835 | tcg_temp_free(l0); |
... | ... | @@ -1842,7 +1859,7 @@ static unsigned int dec_abs_r(DisasContext *dc) |
1842 | 1859 | dc->op1, dc->op2)); |
1843 | 1860 | cris_cc_mask(dc, CC_MASK_NZ); |
1844 | 1861 | |
1845 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
1862 | + t0 = tcg_temp_new(); | |
1846 | 1863 | tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31); |
1847 | 1864 | tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0); |
1848 | 1865 | tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0); |
... | ... | @@ -1916,7 +1933,7 @@ static unsigned int dec_swap_r(DisasContext *dc) |
1916 | 1933 | swapmode_name(dc->op2, modename), dc->op1)); |
1917 | 1934 | |
1918 | 1935 | cris_cc_mask(dc, CC_MASK_NZ); |
1919 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
1936 | + t0 = tcg_temp_new(); | |
1920 | 1937 | t_gen_mov_TN_reg(t0, dc->op1); |
1921 | 1938 | if (dc->op2 & 8) |
1922 | 1939 | tcg_gen_not_tl(t0, t0); |
... | ... | @@ -1952,7 +1969,7 @@ static unsigned int dec_addi_r(DisasContext *dc) |
1952 | 1969 | DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n", |
1953 | 1970 | memsize_char(memsize_zz(dc)), dc->op2, dc->op1)); |
1954 | 1971 | cris_cc_mask(dc, 0); |
1955 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
1972 | + t0 = tcg_temp_new(); | |
1956 | 1973 | tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize)); |
1957 | 1974 | tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0); |
1958 | 1975 | tcg_temp_free(t0); |
... | ... | @@ -1965,7 +1982,7 @@ static unsigned int dec_addi_acr(DisasContext *dc) |
1965 | 1982 | DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n", |
1966 | 1983 | memsize_char(memsize_zz(dc)), dc->op2, dc->op1)); |
1967 | 1984 | cris_cc_mask(dc, 0); |
1968 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
1985 | + t0 = tcg_temp_new(); | |
1969 | 1986 | tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize)); |
1970 | 1987 | tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0); |
1971 | 1988 | tcg_temp_free(t0); |
... | ... | @@ -1994,7 +2011,7 @@ static unsigned int dec_btst_r(DisasContext *dc) |
1994 | 2011 | dc->op1, dc->op2)); |
1995 | 2012 | cris_cc_mask(dc, CC_MASK_NZ); |
1996 | 2013 | |
1997 | - l0 = tcg_temp_local_new(TCG_TYPE_TL); | |
2014 | + l0 = tcg_temp_local_new(); | |
1998 | 2015 | cris_alu(dc, CC_OP_BTST, l0, cpu_R[dc->op2], cpu_R[dc->op1], 4); |
1999 | 2016 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
2000 | 2017 | t_gen_mov_preg_TN(dc, PR_CCS, l0); |
... | ... | @@ -2027,7 +2044,7 @@ static unsigned int dec_movu_r(DisasContext *dc) |
2027 | 2044 | dc->op1, dc->op2)); |
2028 | 2045 | |
2029 | 2046 | cris_cc_mask(dc, CC_MASK_NZ); |
2030 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
2047 | + t0 = tcg_temp_new(); | |
2031 | 2048 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); |
2032 | 2049 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
2033 | 2050 | tcg_temp_free(t0); |
... | ... | @@ -2044,7 +2061,7 @@ static unsigned int dec_movs_r(DisasContext *dc) |
2044 | 2061 | dc->op1, dc->op2)); |
2045 | 2062 | |
2046 | 2063 | cris_cc_mask(dc, CC_MASK_NZ); |
2047 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
2064 | + t0 = tcg_temp_new(); | |
2048 | 2065 | /* Size can only be qi or hi. */ |
2049 | 2066 | t_gen_sext(t0, cpu_R[dc->op1], size); |
2050 | 2067 | cris_alu(dc, CC_OP_MOVE, |
... | ... | @@ -2063,7 +2080,7 @@ static unsigned int dec_addu_r(DisasContext *dc) |
2063 | 2080 | dc->op1, dc->op2)); |
2064 | 2081 | |
2065 | 2082 | cris_cc_mask(dc, CC_MASK_NZVC); |
2066 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
2083 | + t0 = tcg_temp_new(); | |
2067 | 2084 | /* Size can only be qi or hi. */ |
2068 | 2085 | t_gen_zext(t0, cpu_R[dc->op1], size); |
2069 | 2086 | cris_alu(dc, CC_OP_ADD, |
... | ... | @@ -2082,7 +2099,7 @@ static unsigned int dec_adds_r(DisasContext *dc) |
2082 | 2099 | dc->op1, dc->op2)); |
2083 | 2100 | |
2084 | 2101 | cris_cc_mask(dc, CC_MASK_NZVC); |
2085 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
2102 | + t0 = tcg_temp_new(); | |
2086 | 2103 | /* Size can only be qi or hi. */ |
2087 | 2104 | t_gen_sext(t0, cpu_R[dc->op1], size); |
2088 | 2105 | cris_alu(dc, CC_OP_ADD, |
... | ... | @@ -2101,7 +2118,7 @@ static unsigned int dec_subu_r(DisasContext *dc) |
2101 | 2118 | dc->op1, dc->op2)); |
2102 | 2119 | |
2103 | 2120 | cris_cc_mask(dc, CC_MASK_NZVC); |
2104 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
2121 | + t0 = tcg_temp_new(); | |
2105 | 2122 | /* Size can only be qi or hi. */ |
2106 | 2123 | t_gen_zext(t0, cpu_R[dc->op1], size); |
2107 | 2124 | cris_alu(dc, CC_OP_SUB, |
... | ... | @@ -2120,7 +2137,7 @@ static unsigned int dec_subs_r(DisasContext *dc) |
2120 | 2137 | dc->op1, dc->op2)); |
2121 | 2138 | |
2122 | 2139 | cris_cc_mask(dc, CC_MASK_NZVC); |
2123 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
2140 | + t0 = tcg_temp_new(); | |
2124 | 2141 | /* Size can only be qi or hi. */ |
2125 | 2142 | t_gen_sext(t0, cpu_R[dc->op1], size); |
2126 | 2143 | cris_alu(dc, CC_OP_SUB, |
... | ... | @@ -2203,16 +2220,14 @@ static unsigned int dec_move_rs(DisasContext *dc) |
2203 | 2220 | { |
2204 | 2221 | DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2)); |
2205 | 2222 | cris_cc_mask(dc, 0); |
2206 | - tcg_gen_helper_0_2(helper_movl_sreg_reg, | |
2207 | - tcg_const_tl(dc->op2), tcg_const_tl(dc->op1)); | |
2223 | + gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1)); | |
2208 | 2224 | return 2; |
2209 | 2225 | } |
2210 | 2226 | static unsigned int dec_move_sr(DisasContext *dc) |
2211 | 2227 | { |
2212 | 2228 | DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1)); |
2213 | 2229 | cris_cc_mask(dc, 0); |
2214 | - tcg_gen_helper_0_2(helper_movl_reg_sreg, | |
2215 | - tcg_const_tl(dc->op1), tcg_const_tl(dc->op2)); | |
2230 | + gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2)); | |
2216 | 2231 | return 2; |
2217 | 2232 | } |
2218 | 2233 | |
... | ... | @@ -2222,12 +2237,12 @@ static unsigned int dec_move_rp(DisasContext *dc) |
2222 | 2237 | DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2)); |
2223 | 2238 | cris_cc_mask(dc, 0); |
2224 | 2239 | |
2225 | - t[0] = tcg_temp_new(TCG_TYPE_TL); | |
2240 | + t[0] = tcg_temp_new(); | |
2226 | 2241 | if (dc->op2 == PR_CCS) { |
2227 | 2242 | cris_evaluate_flags(dc); |
2228 | 2243 | t_gen_mov_TN_reg(t[0], dc->op1); |
2229 | 2244 | if (dc->tb_flags & U_FLAG) { |
2230 | - t[1] = tcg_temp_new(TCG_TYPE_TL); | |
2245 | + t[1] = tcg_temp_new(); | |
2231 | 2246 | /* User space is not allowed to touch all flags. */ |
2232 | 2247 | tcg_gen_andi_tl(t[0], t[0], 0x39f); |
2233 | 2248 | tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f); |
... | ... | @@ -2255,7 +2270,7 @@ static unsigned int dec_move_pr(DisasContext *dc) |
2255 | 2270 | if (dc->op2 == PR_CCS) |
2256 | 2271 | cris_evaluate_flags(dc); |
2257 | 2272 | |
2258 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
2273 | + t0 = tcg_temp_new(); | |
2259 | 2274 | t_gen_mov_TN_preg(t0, dc->op2); |
2260 | 2275 | cris_alu(dc, CC_OP_MOVE, |
2261 | 2276 | cpu_R[dc->op1], cpu_R[dc->op1], t0, preg_sizes[dc->op2]); |
... | ... | @@ -2282,7 +2297,7 @@ static unsigned int dec_move_mr(DisasContext *dc) |
2282 | 2297 | else { |
2283 | 2298 | TCGv t0; |
2284 | 2299 | |
2285 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
2300 | + t0 = tcg_temp_new(); | |
2286 | 2301 | insn_len = dec_prep_move_m(dc, 0, memsize, t0); |
2287 | 2302 | cris_cc_mask(dc, CC_MASK_NZ); |
2288 | 2303 | cris_alu(dc, CC_OP_MOVE, |
... | ... | @@ -2295,8 +2310,8 @@ static unsigned int dec_move_mr(DisasContext *dc) |
2295 | 2310 | |
2296 | 2311 | static inline void cris_alu_m_alloc_temps(TCGv *t) |
2297 | 2312 | { |
2298 | - t[0] = tcg_temp_new(TCG_TYPE_TL); | |
2299 | - t[1] = tcg_temp_new(TCG_TYPE_TL); | |
2313 | + t[0] = tcg_temp_new(); | |
2314 | + t[1] = tcg_temp_new(); | |
2300 | 2315 | } |
2301 | 2316 | |
2302 | 2317 | static inline void cris_alu_m_free_temps(TCGv *t) |
... | ... | @@ -2580,8 +2595,8 @@ static unsigned int dec_bound_m(DisasContext *dc) |
2580 | 2595 | dc->op1, dc->postinc ? "+]" : "]", |
2581 | 2596 | dc->op2)); |
2582 | 2597 | |
2583 | - l[0] = tcg_temp_local_new(TCG_TYPE_TL); | |
2584 | - l[1] = tcg_temp_local_new(TCG_TYPE_TL); | |
2598 | + l[0] = tcg_temp_local_new(); | |
2599 | + l[1] = tcg_temp_local_new(); | |
2585 | 2600 | insn_len = dec_prep_alu_m(dc, 0, memsize, l[0], l[1]); |
2586 | 2601 | cris_cc_mask(dc, CC_MASK_NZ); |
2587 | 2602 | cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4); |
... | ... | @@ -2694,7 +2709,7 @@ static unsigned int dec_move_pm(DisasContext *dc) |
2694 | 2709 | /* prepare store. Address in T0, value in T1. */ |
2695 | 2710 | if (dc->op2 == PR_CCS) |
2696 | 2711 | cris_evaluate_flags(dc); |
2697 | - t0 = tcg_temp_new(TCG_TYPE_TL); | |
2712 | + t0 = tcg_temp_new(); | |
2698 | 2713 | t_gen_mov_TN_preg(t0, dc->op2); |
2699 | 2714 | cris_flush_cc_state(dc); |
2700 | 2715 | gen_store(dc, cpu_R[dc->op1], t0, memsize); |
... | ... | @@ -2708,7 +2723,8 @@ static unsigned int dec_move_pm(DisasContext *dc) |
2708 | 2723 | |
2709 | 2724 | static unsigned int dec_movem_mr(DisasContext *dc) |
2710 | 2725 | { |
2711 | - TCGv tmp[16]; | |
2726 | + TCGv_i64 tmp[16]; | |
2727 | + TCGv tmp32; | |
2712 | 2728 | TCGv addr; |
2713 | 2729 | int i; |
2714 | 2730 | int nr = dc->op2 + 1; |
... | ... | @@ -2716,18 +2732,18 @@ static unsigned int dec_movem_mr(DisasContext *dc) |
2716 | 2732 | DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1, |
2717 | 2733 | dc->postinc ? "+]" : "]", dc->op2)); |
2718 | 2734 | |
2719 | - addr = tcg_temp_new(TCG_TYPE_TL); | |
2735 | + addr = tcg_temp_new(); | |
2720 | 2736 | /* There are probably better ways of doing this. */ |
2721 | 2737 | cris_flush_cc_state(dc); |
2722 | 2738 | for (i = 0; i < (nr >> 1); i++) { |
2723 | - tmp[i] = tcg_temp_new(TCG_TYPE_I64); | |
2739 | + tmp[i] = tcg_temp_new_i64(); | |
2724 | 2740 | tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); |
2725 | - gen_load(dc, tmp[i], addr, 8, 0); | |
2741 | + gen_load64(dc, tmp[i], addr); | |
2726 | 2742 | } |
2727 | 2743 | if (nr & 1) { |
2728 | - tmp[i] = tcg_temp_new(TCG_TYPE_I32); | |
2744 | + tmp32 = tcg_temp_new_i32(); | |
2729 | 2745 | tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); |
2730 | - gen_load(dc, tmp[i], addr, 4, 0); | |
2746 | + gen_load(dc, tmp32, addr, 4, 0); | |
2731 | 2747 | } |
2732 | 2748 | tcg_temp_free(addr); |
2733 | 2749 | |
... | ... | @@ -2735,11 +2751,11 @@ static unsigned int dec_movem_mr(DisasContext *dc) |
2735 | 2751 | tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]); |
2736 | 2752 | tcg_gen_shri_i64(tmp[i], tmp[i], 32); |
2737 | 2753 | tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]); |
2738 | - tcg_temp_free(tmp[i]); | |
2754 | + tcg_temp_free_i64(tmp[i]); | |
2739 | 2755 | } |
2740 | 2756 | if (nr & 1) { |
2741 | - tcg_gen_mov_tl(cpu_R[dc->op2], tmp[i]); | |
2742 | - tcg_temp_free(tmp[i]); | |
2757 | + tcg_gen_mov_tl(cpu_R[dc->op2], tmp32); | |
2758 | + tcg_temp_free(tmp32); | |
2743 | 2759 | } |
2744 | 2760 | |
2745 | 2761 | /* writeback the updated pointer value. */ |
... | ... | @@ -2762,8 +2778,8 @@ static unsigned int dec_movem_rm(DisasContext *dc) |
2762 | 2778 | |
2763 | 2779 | cris_flush_cc_state(dc); |
2764 | 2780 | |
2765 | - tmp = tcg_temp_new(TCG_TYPE_TL); | |
2766 | - addr = tcg_temp_new(TCG_TYPE_TL); | |
2781 | + tmp = tcg_temp_new(); | |
2782 | + addr = tcg_temp_new(); | |
2767 | 2783 | tcg_gen_movi_tl(tmp, 4); |
2768 | 2784 | tcg_gen_mov_tl(addr, cpu_R[dc->op1]); |
2769 | 2785 | for (i = 0; i <= dc->op2; i++) { |
... | ... | @@ -2960,14 +2976,14 @@ static unsigned int dec_rfe_etc(DisasContext *dc) |
2960 | 2976 | /* rfe. */ |
2961 | 2977 | DIS(fprintf(logfile, "rfe\n")); |
2962 | 2978 | cris_evaluate_flags(dc); |
2963 | - tcg_gen_helper_0_0(helper_rfe); | |
2979 | + gen_helper_rfe(); | |
2964 | 2980 | dc->is_jmp = DISAS_UPDATE; |
2965 | 2981 | break; |
2966 | 2982 | case 5: |
2967 | 2983 | /* rfn. */ |
2968 | 2984 | DIS(fprintf(logfile, "rfn\n")); |
2969 | 2985 | cris_evaluate_flags(dc); |
2970 | - tcg_gen_helper_0_0(helper_rfn); | |
2986 | + gen_helper_rfn(); | |
2971 | 2987 | dc->is_jmp = DISAS_UPDATE; |
2972 | 2988 | break; |
2973 | 2989 | case 6: |
... | ... | @@ -3502,63 +3518,49 @@ CPUCRISState *cpu_cris_init (const char *cpu_model) |
3502 | 3518 | |
3503 | 3519 | tcg_initialized = 1; |
3504 | 3520 | |
3505 | - cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); | |
3506 | - cc_x = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
3521 | + cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
3522 | + cc_x = tcg_global_mem_new(TCG_AREG0, | |
3507 | 3523 | offsetof(CPUState, cc_x), "cc_x"); |
3508 | - cc_src = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
3524 | + cc_src = tcg_global_mem_new(TCG_AREG0, | |
3509 | 3525 | offsetof(CPUState, cc_src), "cc_src"); |
3510 | - cc_dest = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
3526 | + cc_dest = tcg_global_mem_new(TCG_AREG0, | |
3511 | 3527 | offsetof(CPUState, cc_dest), |
3512 | 3528 | "cc_dest"); |
3513 | - cc_result = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
3529 | + cc_result = tcg_global_mem_new(TCG_AREG0, | |
3514 | 3530 | offsetof(CPUState, cc_result), |
3515 | 3531 | "cc_result"); |
3516 | - cc_op = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
3532 | + cc_op = tcg_global_mem_new(TCG_AREG0, | |
3517 | 3533 | offsetof(CPUState, cc_op), "cc_op"); |
3518 | - cc_size = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
3534 | + cc_size = tcg_global_mem_new(TCG_AREG0, | |
3519 | 3535 | offsetof(CPUState, cc_size), |
3520 | 3536 | "cc_size"); |
3521 | - cc_mask = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
3537 | + cc_mask = tcg_global_mem_new(TCG_AREG0, | |
3522 | 3538 | offsetof(CPUState, cc_mask), |
3523 | 3539 | "cc_mask"); |
3524 | 3540 | |
3525 | - env_pc = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
3541 | + env_pc = tcg_global_mem_new(TCG_AREG0, | |
3526 | 3542 | offsetof(CPUState, pc), |
3527 | 3543 | "pc"); |
3528 | - env_btarget = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
3544 | + env_btarget = tcg_global_mem_new(TCG_AREG0, | |
3529 | 3545 | offsetof(CPUState, btarget), |
3530 | 3546 | "btarget"); |
3531 | - env_btaken = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
3547 | + env_btaken = tcg_global_mem_new(TCG_AREG0, | |
3532 | 3548 | offsetof(CPUState, btaken), |
3533 | 3549 | "btaken"); |
3534 | 3550 | for (i = 0; i < 16; i++) { |
3535 | - cpu_R[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
3551 | + cpu_R[i] = tcg_global_mem_new(TCG_AREG0, | |
3536 | 3552 | offsetof(CPUState, regs[i]), |
3537 | 3553 | regnames[i]); |
3538 | 3554 | } |
3539 | 3555 | for (i = 0; i < 16; i++) { |
3540 | - cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
3556 | + cpu_PR[i] = tcg_global_mem_new(TCG_AREG0, | |
3541 | 3557 | offsetof(CPUState, pregs[i]), |
3542 | 3558 | pregnames[i]); |
3543 | 3559 | } |
3544 | 3560 | |
3545 | - TCG_HELPER(helper_raise_exception); | |
3546 | - TCG_HELPER(helper_dump); | |
3547 | - | |
3548 | - TCG_HELPER(helper_tlb_flush_pid); | |
3549 | - TCG_HELPER(helper_movl_sreg_reg); | |
3550 | - TCG_HELPER(helper_movl_reg_sreg); | |
3551 | - TCG_HELPER(helper_rfe); | |
3552 | - TCG_HELPER(helper_rfn); | |
3561 | +#define GEN_HELPER 2 | |
3562 | +#include "helper.h" | |
3553 | 3563 | |
3554 | - TCG_HELPER(helper_evaluate_flags_muls); | |
3555 | - TCG_HELPER(helper_evaluate_flags_mulu); | |
3556 | - TCG_HELPER(helper_evaluate_flags_mcp); | |
3557 | - TCG_HELPER(helper_evaluate_flags_alu_4); | |
3558 | - TCG_HELPER(helper_evaluate_flags_move_4); | |
3559 | - TCG_HELPER(helper_evaluate_flags_move_2); | |
3560 | - TCG_HELPER(helper_evaluate_flags); | |
3561 | - TCG_HELPER(helper_top_evaluate_flags); | |
3562 | 3564 | return env; |
3563 | 3565 | } |
3564 | 3566 | ... | ... |
target-i386/cpu.h
... | ... | @@ -780,8 +780,6 @@ typedef struct CCTable { |
780 | 780 | int (*compute_c)(void); /* return the C flag */ |
781 | 781 | } CCTable; |
782 | 782 | |
783 | -extern CCTable cc_table[]; | |
784 | - | |
785 | 783 | #if defined(CONFIG_USER_ONLY) |
786 | 784 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
787 | 785 | { | ... | ... |
target-i386/exec.h
... | ... | @@ -290,7 +290,7 @@ extern const uint8_t rclb_table[32]; |
290 | 290 | |
291 | 291 | static inline uint32_t compute_eflags(void) |
292 | 292 | { |
293 | - return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
293 | + return env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); | |
294 | 294 | } |
295 | 295 | |
296 | 296 | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */ | ... | ... |
target-i386/helper.c
target-i386/helper.h
1 | -#ifndef DEF_HELPER | |
2 | -#define DEF_HELPER(ret, name, params) ret name params; | |
3 | -#endif | |
1 | +#include "def-helper.h" | |
2 | + | |
3 | +DEF_HELPER_FLAGS_1(cc_compute_all, TCG_CALL_PURE, i32, int) | |
4 | +DEF_HELPER_FLAGS_1(cc_compute_c, TCG_CALL_PURE, i32, int) | |
4 | 5 | |
5 | -DEF_HELPER(void, helper_lock, (void)) | |
6 | -DEF_HELPER(void, helper_unlock, (void)) | |
7 | -DEF_HELPER(void, helper_write_eflags, (target_ulong t0, uint32_t update_mask)) | |
8 | -DEF_HELPER(target_ulong, helper_read_eflags, (void)) | |
9 | -DEF_HELPER(void, helper_divb_AL, (target_ulong t0)) | |
10 | -DEF_HELPER(void, helper_idivb_AL, (target_ulong t0)) | |
11 | -DEF_HELPER(void, helper_divw_AX, (target_ulong t0)) | |
12 | -DEF_HELPER(void, helper_idivw_AX, (target_ulong t0)) | |
13 | -DEF_HELPER(void, helper_divl_EAX, (target_ulong t0)) | |
14 | -DEF_HELPER(void, helper_idivl_EAX, (target_ulong t0)) | |
6 | +DEF_HELPER_0(lock, void) | |
7 | +DEF_HELPER_0(unlock, void) | |
8 | +DEF_HELPER_2(write_eflags, void, tl, i32) | |
9 | +DEF_HELPER_0(read_eflags, tl) | |
10 | +DEF_HELPER_1(divb_AL, void, tl) | |
11 | +DEF_HELPER_1(idivb_AL, void, tl) | |
12 | +DEF_HELPER_1(divw_AX, void, tl) | |
13 | +DEF_HELPER_1(idivw_AX, void, tl) | |
14 | +DEF_HELPER_1(divl_EAX, void, tl) | |
15 | +DEF_HELPER_1(idivl_EAX, void, tl) | |
15 | 16 | #ifdef TARGET_X86_64 |
16 | -DEF_HELPER(void, helper_mulq_EAX_T0, (target_ulong t0)) | |
17 | -DEF_HELPER(void, helper_imulq_EAX_T0, (target_ulong t0)) | |
18 | -DEF_HELPER(target_ulong, helper_imulq_T0_T1, (target_ulong t0, target_ulong t1)) | |
19 | -DEF_HELPER(void, helper_divq_EAX, (target_ulong t0)) | |
20 | -DEF_HELPER(void, helper_idivq_EAX, (target_ulong t0)) | |
17 | +DEF_HELPER_1(mulq_EAX_T0, void, tl) | |
18 | +DEF_HELPER_1(imulq_EAX_T0, void, tl) | |
19 | +DEF_HELPER_2(imulq_T0_T1, tl, tl, tl) | |
20 | +DEF_HELPER_1(divq_EAX, void, tl) | |
21 | +DEF_HELPER_1(idivq_EAX, void, tl) | |
21 | 22 | #endif |
22 | 23 | |
23 | -DEF_HELPER(void, helper_aam, (int base)) | |
24 | -DEF_HELPER(void, helper_aad, (int base)) | |
25 | -DEF_HELPER(void, helper_aaa, (void)) | |
26 | -DEF_HELPER(void, helper_aas, (void)) | |
27 | -DEF_HELPER(void, helper_daa, (void)) | |
28 | -DEF_HELPER(void, helper_das, (void)) | |
24 | +DEF_HELPER_1(aam, void, int) | |
25 | +DEF_HELPER_1(aad, void, int) | |
26 | +DEF_HELPER_0(aaa, void) | |
27 | +DEF_HELPER_0(aas, void) | |
28 | +DEF_HELPER_0(daa, void) | |
29 | +DEF_HELPER_0(das, void) | |
29 | 30 | |
30 | -DEF_HELPER(target_ulong, helper_lsl, (target_ulong selector1)) | |
31 | -DEF_HELPER(target_ulong, helper_lar, (target_ulong selector1)) | |
32 | -DEF_HELPER(void, helper_verr, (target_ulong selector1)) | |
33 | -DEF_HELPER(void, helper_verw, (target_ulong selector1)) | |
34 | -DEF_HELPER(void, helper_lldt, (int selector)) | |
35 | -DEF_HELPER(void, helper_ltr, (int selector)) | |
36 | -DEF_HELPER(void, helper_load_seg, (int seg_reg, int selector)) | |
37 | -DEF_HELPER(void, helper_ljmp_protected, (int new_cs, target_ulong new_eip, | |
38 | - int next_eip_addend)) | |
39 | -DEF_HELPER(void, helper_lcall_real, (int new_cs, target_ulong new_eip1, | |
40 | - int shift, int next_eip)) | |
41 | -DEF_HELPER(void, helper_lcall_protected, (int new_cs, target_ulong new_eip, | |
42 | - int shift, int next_eip_addend)) | |
43 | -DEF_HELPER(void, helper_iret_real, (int shift)) | |
44 | -DEF_HELPER(void, helper_iret_protected, (int shift, int next_eip)) | |
45 | -DEF_HELPER(void, helper_lret_protected, (int shift, int addend)) | |
46 | -DEF_HELPER(target_ulong, helper_read_crN, (int reg)) | |
47 | -DEF_HELPER(void, helper_write_crN, (int reg, target_ulong t0)) | |
48 | -DEF_HELPER(void, helper_lmsw, (target_ulong t0)) | |
49 | -DEF_HELPER(void, helper_clts, (void)) | |
50 | -DEF_HELPER(void, helper_movl_drN_T0, (int reg, target_ulong t0)) | |
51 | -DEF_HELPER(void, helper_invlpg, (target_ulong addr)) | |
31 | +DEF_HELPER_1(lsl, tl, tl) | |
32 | +DEF_HELPER_1(lar, tl, tl) | |
33 | +DEF_HELPER_1(verr, void, tl) | |
34 | +DEF_HELPER_1(verw, void, tl) | |
35 | +DEF_HELPER_1(lldt, void, int) | |
36 | +DEF_HELPER_1(ltr, void, int) | |
37 | +DEF_HELPER_2(load_seg, void, int, int) | |
38 | +DEF_HELPER_3(ljmp_protected, void, int, tl, int) | |
39 | +DEF_HELPER_4(lcall_real, void, int, tl, int, int) | |
40 | +DEF_HELPER_4(lcall_protected, void, int, tl, int, int) | |
41 | +DEF_HELPER_1(iret_real, void, int) | |
42 | +DEF_HELPER_2(iret_protected, void, int, int) | |
43 | +DEF_HELPER_2(lret_protected, void, int, int) | |
44 | +DEF_HELPER_1(read_crN, tl, int) | |
45 | +DEF_HELPER_2(write_crN, void, int, tl) | |
46 | +DEF_HELPER_1(lmsw, void, tl) | |
47 | +DEF_HELPER_0(clts, void) | |
48 | +DEF_HELPER_2(movl_drN_T0, void, int, tl) | |
49 | +DEF_HELPER_1(invlpg, void, tl) | |
52 | 50 | |
53 | -DEF_HELPER(void, helper_enter_level, (int level, int data32, target_ulong t1)) | |
51 | +DEF_HELPER_3(enter_level, void, int, int, tl) | |
54 | 52 | #ifdef TARGET_X86_64 |
55 | -DEF_HELPER(void, helper_enter64_level, (int level, int data64, target_ulong t1)) | |
53 | +DEF_HELPER_3(enter64_level, void, int, int, tl) | |
56 | 54 | #endif |
57 | -DEF_HELPER(void, helper_sysenter, (void)) | |
58 | -DEF_HELPER(void, helper_sysexit, (int dflag)) | |
55 | +DEF_HELPER_0(sysenter, void) | |
56 | +DEF_HELPER_1(sysexit, void, int) | |
59 | 57 | #ifdef TARGET_X86_64 |
60 | -DEF_HELPER(void, helper_syscall, (int next_eip_addend)) | |
61 | -DEF_HELPER(void, helper_sysret, (int dflag)) | |
58 | +DEF_HELPER_1(syscall, void, int) | |
59 | +DEF_HELPER_1(sysret, void, int) | |
62 | 60 | #endif |
63 | -DEF_HELPER(void, helper_hlt, (int next_eip_addend)) | |
64 | -DEF_HELPER(void, helper_monitor, (target_ulong ptr)) | |
65 | -DEF_HELPER(void, helper_mwait, (int next_eip_addend)) | |
66 | -DEF_HELPER(void, helper_debug, (void)) | |
67 | -DEF_HELPER(void, helper_raise_interrupt, (int intno, int next_eip_addend)) | |
68 | -DEF_HELPER(void, helper_raise_exception, (int exception_index)) | |
69 | -DEF_HELPER(void, helper_cli, (void)) | |
70 | -DEF_HELPER(void, helper_sti, (void)) | |
71 | -DEF_HELPER(void, helper_set_inhibit_irq, (void)) | |
72 | -DEF_HELPER(void, helper_reset_inhibit_irq, (void)) | |
73 | -DEF_HELPER(void, helper_boundw, (target_ulong a0, int v)) | |
74 | -DEF_HELPER(void, helper_boundl, (target_ulong a0, int v)) | |
75 | -DEF_HELPER(void, helper_rsm, (void)) | |
76 | -DEF_HELPER(void, helper_into, (int next_eip_addend)) | |
77 | -DEF_HELPER(void, helper_cmpxchg8b, (target_ulong a0)) | |
61 | +DEF_HELPER_1(hlt, void, int) | |
62 | +DEF_HELPER_1(monitor, void, tl) | |
63 | +DEF_HELPER_1(mwait, void, int) | |
64 | +DEF_HELPER_0(debug, void) | |
65 | +DEF_HELPER_2(raise_interrupt, void, int, int) | |
66 | +DEF_HELPER_1(raise_exception, void, int) | |
67 | +DEF_HELPER_0(cli, void) | |
68 | +DEF_HELPER_0(sti, void) | |
69 | +DEF_HELPER_0(set_inhibit_irq, void) | |
70 | +DEF_HELPER_0(reset_inhibit_irq, void) | |
71 | +DEF_HELPER_2(boundw, void, tl, int) | |
72 | +DEF_HELPER_2(boundl, void, tl, int) | |
73 | +DEF_HELPER_0(rsm, void) | |
74 | +DEF_HELPER_1(into, void, int) | |
75 | +DEF_HELPER_1(cmpxchg8b, void, tl) | |
78 | 76 | #ifdef TARGET_X86_64 |
79 | -DEF_HELPER(void, helper_cmpxchg16b, (target_ulong a0)) | |
77 | +DEF_HELPER_1(cmpxchg16b, void, tl) | |
80 | 78 | #endif |
81 | -DEF_HELPER(void, helper_single_step, (void)) | |
82 | -DEF_HELPER(void, helper_cpuid, (void)) | |
83 | -DEF_HELPER(void, helper_rdtsc, (void)) | |
84 | -DEF_HELPER(void, helper_rdpmc, (void)) | |
85 | -DEF_HELPER(void, helper_rdmsr, (void)) | |
86 | -DEF_HELPER(void, helper_wrmsr, (void)) | |
79 | +DEF_HELPER_0(single_step, void) | |
80 | +DEF_HELPER_0(cpuid, void) | |
81 | +DEF_HELPER_0(rdtsc, void) | |
82 | +DEF_HELPER_0(rdpmc, void) | |
83 | +DEF_HELPER_0(rdmsr, void) | |
84 | +DEF_HELPER_0(wrmsr, void) | |
87 | 85 | |
88 | -DEF_HELPER(void, helper_check_iob, (uint32_t t0)) | |
89 | -DEF_HELPER(void, helper_check_iow, (uint32_t t0)) | |
90 | -DEF_HELPER(void, helper_check_iol, (uint32_t t0)) | |
91 | -DEF_HELPER(void, helper_outb, (uint32_t port, uint32_t data)) | |
92 | -DEF_HELPER(target_ulong, helper_inb, (uint32_t port)) | |
93 | -DEF_HELPER(void, helper_outw, (uint32_t port, uint32_t data)) | |
94 | -DEF_HELPER(target_ulong, helper_inw, (uint32_t port)) | |
95 | -DEF_HELPER(void, helper_outl, (uint32_t port, uint32_t data)) | |
96 | -DEF_HELPER(target_ulong, helper_inl, (uint32_t port)) | |
86 | +DEF_HELPER_1(check_iob, void, i32) | |
87 | +DEF_HELPER_1(check_iow, void, i32) | |
88 | +DEF_HELPER_1(check_iol, void, i32) | |
89 | +DEF_HELPER_2(outb, void, i32, i32) | |
90 | +DEF_HELPER_1(inb, tl, i32) | |
91 | +DEF_HELPER_2(outw, void, i32, i32) | |
92 | +DEF_HELPER_1(inw, tl, i32) | |
93 | +DEF_HELPER_2(outl, void, i32, i32) | |
94 | +DEF_HELPER_1(inl, tl, i32) | |
97 | 95 | |
98 | -DEF_HELPER(void, helper_svm_check_intercept_param, (uint32_t type, uint64_t param)) | |
99 | -DEF_HELPER(void, helper_vmexit, (uint32_t exit_code, uint64_t exit_info_1)) | |
100 | -DEF_HELPER(void, helper_svm_check_io, (uint32_t port, uint32_t param, | |
101 | - uint32_t next_eip_addend)) | |
102 | -DEF_HELPER(void, helper_vmrun, (int aflag, int next_eip_addend)) | |
103 | -DEF_HELPER(void, helper_vmmcall, (void)) | |
104 | -DEF_HELPER(void, helper_vmload, (int aflag)) | |
105 | -DEF_HELPER(void, helper_vmsave, (int aflag)) | |
106 | -DEF_HELPER(void, helper_stgi, (void)) | |
107 | -DEF_HELPER(void, helper_clgi, (void)) | |
108 | -DEF_HELPER(void, helper_skinit, (void)) | |
109 | -DEF_HELPER(void, helper_invlpga, (int aflag)) | |
96 | +DEF_HELPER_2(svm_check_intercept_param, void, i32, i64) | |
97 | +DEF_HELPER_2(vmexit, void, i32, i64) | |
98 | +DEF_HELPER_3(svm_check_io, void, i32, i32, i32) | |
99 | +DEF_HELPER_2(vmrun, void, int, int) | |
100 | +DEF_HELPER_0(vmmcall, void) | |
101 | +DEF_HELPER_1(vmload, void, int) | |
102 | +DEF_HELPER_1(vmsave, void, int) | |
103 | +DEF_HELPER_0(stgi, void) | |
104 | +DEF_HELPER_0(clgi, void) | |
105 | +DEF_HELPER_0(skinit, void) | |
106 | +DEF_HELPER_1(invlpga, void, int) | |
110 | 107 | |
111 | 108 | /* x86 FPU */ |
112 | 109 | |
113 | -DEF_HELPER(void, helper_flds_FT0, (uint32_t val)) | |
114 | -DEF_HELPER(void, helper_fldl_FT0, (uint64_t val)) | |
115 | -DEF_HELPER(void, helper_fildl_FT0, (int32_t val)) | |
116 | -DEF_HELPER(void, helper_flds_ST0, (uint32_t val)) | |
117 | -DEF_HELPER(void, helper_fldl_ST0, (uint64_t val)) | |
118 | -DEF_HELPER(void, helper_fildl_ST0, (int32_t val)) | |
119 | -DEF_HELPER(void, helper_fildll_ST0, (int64_t val)) | |
120 | -DEF_HELPER(uint32_t, helper_fsts_ST0, (void)) | |
121 | -DEF_HELPER(uint64_t, helper_fstl_ST0, (void)) | |
122 | -DEF_HELPER(int32_t, helper_fist_ST0, (void)) | |
123 | -DEF_HELPER(int32_t, helper_fistl_ST0, (void)) | |
124 | -DEF_HELPER(int64_t, helper_fistll_ST0, (void)) | |
125 | -DEF_HELPER(int32_t, helper_fistt_ST0, (void)) | |
126 | -DEF_HELPER(int32_t, helper_fisttl_ST0, (void)) | |
127 | -DEF_HELPER(int64_t, helper_fisttll_ST0, (void)) | |
128 | -DEF_HELPER(void, helper_fldt_ST0, (target_ulong ptr)) | |
129 | -DEF_HELPER(void, helper_fstt_ST0, (target_ulong ptr)) | |
130 | -DEF_HELPER(void, helper_fpush, (void)) | |
131 | -DEF_HELPER(void, helper_fpop, (void)) | |
132 | -DEF_HELPER(void, helper_fdecstp, (void)) | |
133 | -DEF_HELPER(void, helper_fincstp, (void)) | |
134 | -DEF_HELPER(void, helper_ffree_STN, (int st_index)) | |
135 | -DEF_HELPER(void, helper_fmov_ST0_FT0, (void)) | |
136 | -DEF_HELPER(void, helper_fmov_FT0_STN, (int st_index)) | |
137 | -DEF_HELPER(void, helper_fmov_ST0_STN, (int st_index)) | |
138 | -DEF_HELPER(void, helper_fmov_STN_ST0, (int st_index)) | |
139 | -DEF_HELPER(void, helper_fxchg_ST0_STN, (int st_index)) | |
140 | -DEF_HELPER(void, helper_fcom_ST0_FT0, (void)) | |
141 | -DEF_HELPER(void, helper_fucom_ST0_FT0, (void)) | |
142 | -DEF_HELPER(void, helper_fcomi_ST0_FT0, (void)) | |
143 | -DEF_HELPER(void, helper_fucomi_ST0_FT0, (void)) | |
144 | -DEF_HELPER(void, helper_fadd_ST0_FT0, (void)) | |
145 | -DEF_HELPER(void, helper_fmul_ST0_FT0, (void)) | |
146 | -DEF_HELPER(void, helper_fsub_ST0_FT0, (void)) | |
147 | -DEF_HELPER(void, helper_fsubr_ST0_FT0, (void)) | |
148 | -DEF_HELPER(void, helper_fdiv_ST0_FT0, (void)) | |
149 | -DEF_HELPER(void, helper_fdivr_ST0_FT0, (void)) | |
150 | -DEF_HELPER(void, helper_fadd_STN_ST0, (int st_index)) | |
151 | -DEF_HELPER(void, helper_fmul_STN_ST0, (int st_index)) | |
152 | -DEF_HELPER(void, helper_fsub_STN_ST0, (int st_index)) | |
153 | -DEF_HELPER(void, helper_fsubr_STN_ST0, (int st_index)) | |
154 | -DEF_HELPER(void, helper_fdiv_STN_ST0, (int st_index)) | |
155 | -DEF_HELPER(void, helper_fdivr_STN_ST0, (int st_index)) | |
156 | -DEF_HELPER(void, helper_fchs_ST0, (void)) | |
157 | -DEF_HELPER(void, helper_fabs_ST0, (void)) | |
158 | -DEF_HELPER(void, helper_fxam_ST0, (void)) | |
159 | -DEF_HELPER(void, helper_fld1_ST0, (void)) | |
160 | -DEF_HELPER(void, helper_fldl2t_ST0, (void)) | |
161 | -DEF_HELPER(void, helper_fldl2e_ST0, (void)) | |
162 | -DEF_HELPER(void, helper_fldpi_ST0, (void)) | |
163 | -DEF_HELPER(void, helper_fldlg2_ST0, (void)) | |
164 | -DEF_HELPER(void, helper_fldln2_ST0, (void)) | |
165 | -DEF_HELPER(void, helper_fldz_ST0, (void)) | |
166 | -DEF_HELPER(void, helper_fldz_FT0, (void)) | |
167 | -DEF_HELPER(uint32_t, helper_fnstsw, (void)) | |
168 | -DEF_HELPER(uint32_t, helper_fnstcw, (void)) | |
169 | -DEF_HELPER(void, helper_fldcw, (uint32_t val)) | |
170 | -DEF_HELPER(void, helper_fclex, (void)) | |
171 | -DEF_HELPER(void, helper_fwait, (void)) | |
172 | -DEF_HELPER(void, helper_fninit, (void)) | |
173 | -DEF_HELPER(void, helper_fbld_ST0, (target_ulong ptr)) | |
174 | -DEF_HELPER(void, helper_fbst_ST0, (target_ulong ptr)) | |
175 | -DEF_HELPER(void, helper_f2xm1, (void)) | |
176 | -DEF_HELPER(void, helper_fyl2x, (void)) | |
177 | -DEF_HELPER(void, helper_fptan, (void)) | |
178 | -DEF_HELPER(void, helper_fpatan, (void)) | |
179 | -DEF_HELPER(void, helper_fxtract, (void)) | |
180 | -DEF_HELPER(void, helper_fprem1, (void)) | |
181 | -DEF_HELPER(void, helper_fprem, (void)) | |
182 | -DEF_HELPER(void, helper_fyl2xp1, (void)) | |
183 | -DEF_HELPER(void, helper_fsqrt, (void)) | |
184 | -DEF_HELPER(void, helper_fsincos, (void)) | |
185 | -DEF_HELPER(void, helper_frndint, (void)) | |
186 | -DEF_HELPER(void, helper_fscale, (void)) | |
187 | -DEF_HELPER(void, helper_fsin, (void)) | |
188 | -DEF_HELPER(void, helper_fcos, (void)) | |
189 | -DEF_HELPER(void, helper_fstenv, (target_ulong ptr, int data32)) | |
190 | -DEF_HELPER(void, helper_fldenv, (target_ulong ptr, int data32)) | |
191 | -DEF_HELPER(void, helper_fsave, (target_ulong ptr, int data32)) | |
192 | -DEF_HELPER(void, helper_frstor, (target_ulong ptr, int data32)) | |
193 | -DEF_HELPER(void, helper_fxsave, (target_ulong ptr, int data64)) | |
194 | -DEF_HELPER(void, helper_fxrstor, (target_ulong ptr, int data64)) | |
195 | -DEF_HELPER(target_ulong, helper_bsf, (target_ulong t0)) | |
196 | -DEF_HELPER(target_ulong, helper_bsr, (target_ulong t0)) | |
110 | +DEF_HELPER_1(flds_FT0, void, i32) | |
111 | +DEF_HELPER_1(fldl_FT0, void, i64) | |
112 | +DEF_HELPER_1(fildl_FT0, void, s32) | |
113 | +DEF_HELPER_1(flds_ST0, void, i32) | |
114 | +DEF_HELPER_1(fldl_ST0, void, i64) | |
115 | +DEF_HELPER_1(fildl_ST0, void, s32) | |
116 | +DEF_HELPER_1(fildll_ST0, void, s64) | |
117 | +DEF_HELPER_0(fsts_ST0, i32) | |
118 | +DEF_HELPER_0(fstl_ST0, i64) | |
119 | +DEF_HELPER_0(fist_ST0, s32) | |
120 | +DEF_HELPER_0(fistl_ST0, s32) | |
121 | +DEF_HELPER_0(fistll_ST0, s64) | |
122 | +DEF_HELPER_0(fistt_ST0, s32) | |
123 | +DEF_HELPER_0(fisttl_ST0, s32) | |
124 | +DEF_HELPER_0(fisttll_ST0, s64) | |
125 | +DEF_HELPER_1(fldt_ST0, void, tl) | |
126 | +DEF_HELPER_1(fstt_ST0, void, tl) | |
127 | +DEF_HELPER_0(fpush, void) | |
128 | +DEF_HELPER_0(fpop, void) | |
129 | +DEF_HELPER_0(fdecstp, void) | |
130 | +DEF_HELPER_0(fincstp, void) | |
131 | +DEF_HELPER_1(ffree_STN, void, int) | |
132 | +DEF_HELPER_0(fmov_ST0_FT0, void) | |
133 | +DEF_HELPER_1(fmov_FT0_STN, void, int) | |
134 | +DEF_HELPER_1(fmov_ST0_STN, void, int) | |
135 | +DEF_HELPER_1(fmov_STN_ST0, void, int) | |
136 | +DEF_HELPER_1(fxchg_ST0_STN, void, int) | |
137 | +DEF_HELPER_0(fcom_ST0_FT0, void) | |
138 | +DEF_HELPER_0(fucom_ST0_FT0, void) | |
139 | +DEF_HELPER_0(fcomi_ST0_FT0, void) | |
140 | +DEF_HELPER_0(fucomi_ST0_FT0, void) | |
141 | +DEF_HELPER_0(fadd_ST0_FT0, void) | |
142 | +DEF_HELPER_0(fmul_ST0_FT0, void) | |
143 | +DEF_HELPER_0(fsub_ST0_FT0, void) | |
144 | +DEF_HELPER_0(fsubr_ST0_FT0, void) | |
145 | +DEF_HELPER_0(fdiv_ST0_FT0, void) | |
146 | +DEF_HELPER_0(fdivr_ST0_FT0, void) | |
147 | +DEF_HELPER_1(fadd_STN_ST0, void, int) | |
148 | +DEF_HELPER_1(fmul_STN_ST0, void, int) | |
149 | +DEF_HELPER_1(fsub_STN_ST0, void, int) | |
150 | +DEF_HELPER_1(fsubr_STN_ST0, void, int) | |
151 | +DEF_HELPER_1(fdiv_STN_ST0, void, int) | |
152 | +DEF_HELPER_1(fdivr_STN_ST0, void, int) | |
153 | +DEF_HELPER_0(fchs_ST0, void) | |
154 | +DEF_HELPER_0(fabs_ST0, void) | |
155 | +DEF_HELPER_0(fxam_ST0, void) | |
156 | +DEF_HELPER_0(fld1_ST0, void) | |
157 | +DEF_HELPER_0(fldl2t_ST0, void) | |
158 | +DEF_HELPER_0(fldl2e_ST0, void) | |
159 | +DEF_HELPER_0(fldpi_ST0, void) | |
160 | +DEF_HELPER_0(fldlg2_ST0, void) | |
161 | +DEF_HELPER_0(fldln2_ST0, void) | |
162 | +DEF_HELPER_0(fldz_ST0, void) | |
163 | +DEF_HELPER_0(fldz_FT0, void) | |
164 | +DEF_HELPER_0(fnstsw, i32) | |
165 | +DEF_HELPER_0(fnstcw, i32) | |
166 | +DEF_HELPER_1(fldcw, void, i32) | |
167 | +DEF_HELPER_0(fclex, void) | |
168 | +DEF_HELPER_0(fwait, void) | |
169 | +DEF_HELPER_0(fninit, void) | |
170 | +DEF_HELPER_1(fbld_ST0, void, tl) | |
171 | +DEF_HELPER_1(fbst_ST0, void, tl) | |
172 | +DEF_HELPER_0(f2xm1, void) | |
173 | +DEF_HELPER_0(fyl2x, void) | |
174 | +DEF_HELPER_0(fptan, void) | |
175 | +DEF_HELPER_0(fpatan, void) | |
176 | +DEF_HELPER_0(fxtract, void) | |
177 | +DEF_HELPER_0(fprem1, void) | |
178 | +DEF_HELPER_0(fprem, void) | |
179 | +DEF_HELPER_0(fyl2xp1, void) | |
180 | +DEF_HELPER_0(fsqrt, void) | |
181 | +DEF_HELPER_0(fsincos, void) | |
182 | +DEF_HELPER_0(frndint, void) | |
183 | +DEF_HELPER_0(fscale, void) | |
184 | +DEF_HELPER_0(fsin, void) | |
185 | +DEF_HELPER_0(fcos, void) | |
186 | +DEF_HELPER_2(fstenv, void, tl, int) | |
187 | +DEF_HELPER_2(fldenv, void, tl, int) | |
188 | +DEF_HELPER_2(fsave, void, tl, int) | |
189 | +DEF_HELPER_2(frstor, void, tl, int) | |
190 | +DEF_HELPER_2(fxsave, void, tl, int) | |
191 | +DEF_HELPER_2(fxrstor, void, tl, int) | |
192 | +DEF_HELPER_1(bsf, tl, tl) | |
193 | +DEF_HELPER_1(bsr, tl, tl) | |
197 | 194 | |
198 | 195 | /* MMX/SSE */ |
199 | 196 | |
200 | -DEF_HELPER(void, helper_enter_mmx, (void)) | |
201 | -DEF_HELPER(void, helper_emms, (void)) | |
202 | -DEF_HELPER(void, helper_movq, (uint64_t *d, uint64_t *s)) | |
197 | +DEF_HELPER_0(enter_mmx, void) | |
198 | +DEF_HELPER_0(emms, void) | |
199 | +DEF_HELPER_2(movq, void, ptr, ptr) | |
203 | 200 | |
204 | 201 | #define SHIFT 0 |
205 | 202 | #include "ops_sse_header.h" |
206 | 203 | #define SHIFT 1 |
207 | 204 | #include "ops_sse_header.h" |
208 | 205 | |
209 | -DEF_HELPER(target_ulong, helper_rclb, (target_ulong t0, target_ulong t1)) | |
210 | -DEF_HELPER(target_ulong, helper_rclw, (target_ulong t0, target_ulong t1)) | |
211 | -DEF_HELPER(target_ulong, helper_rcll, (target_ulong t0, target_ulong t1)) | |
212 | -DEF_HELPER(target_ulong, helper_rcrb, (target_ulong t0, target_ulong t1)) | |
213 | -DEF_HELPER(target_ulong, helper_rcrw, (target_ulong t0, target_ulong t1)) | |
214 | -DEF_HELPER(target_ulong, helper_rcrl, (target_ulong t0, target_ulong t1)) | |
206 | +DEF_HELPER_2(rclb, tl, tl, tl) | |
207 | +DEF_HELPER_2(rclw, tl, tl, tl) | |
208 | +DEF_HELPER_2(rcll, tl, tl, tl) | |
209 | +DEF_HELPER_2(rcrb, tl, tl, tl) | |
210 | +DEF_HELPER_2(rcrw, tl, tl, tl) | |
211 | +DEF_HELPER_2(rcrl, tl, tl, tl) | |
215 | 212 | #ifdef TARGET_X86_64 |
216 | -DEF_HELPER(target_ulong, helper_rclq, (target_ulong t0, target_ulong t1)) | |
217 | -DEF_HELPER(target_ulong, helper_rcrq, (target_ulong t0, target_ulong t1)) | |
213 | +DEF_HELPER_2(rclq, tl, tl, tl) | |
214 | +DEF_HELPER_2(rcrq, tl, tl, tl) | |
218 | 215 | #endif |
219 | 216 | |
220 | -#undef DEF_HELPER | |
217 | +#include "def-helper.h" | ... | ... |
target-i386/helper_template.h
... | ... | @@ -280,7 +280,7 @@ target_ulong glue(helper_rcl, SUFFIX)(target_ulong t0, target_ulong t1) |
280 | 280 | count = rclb_table[count]; |
281 | 281 | #endif |
282 | 282 | if (count) { |
283 | - eflags = cc_table[CC_OP].compute_all(); | |
283 | + eflags = helper_cc_compute_all(CC_OP); | |
284 | 284 | t0 &= DATA_MASK; |
285 | 285 | src = t0; |
286 | 286 | res = (t0 << count) | ((target_ulong)(eflags & CC_C) << (count - 1)); |
... | ... | @@ -309,7 +309,7 @@ target_ulong glue(helper_rcr, SUFFIX)(target_ulong t0, target_ulong t1) |
309 | 309 | count = rclb_table[count]; |
310 | 310 | #endif |
311 | 311 | if (count) { |
312 | - eflags = cc_table[CC_OP].compute_all(); | |
312 | + eflags = helper_cc_compute_all(CC_OP); | |
313 | 313 | t0 &= DATA_MASK; |
314 | 314 | src = t0; |
315 | 315 | res = (t0 >> count) | ((target_ulong)(eflags & CC_C) << (DATA_BITS - count)); | ... | ... |