gwj / at91sam9263 · Commits

Commit a748ab6d9a443e741c52ccd38c4e00e2b32590c4

Authored by aurel32
1 parent f2fde45a

target-ppc: modify hw/ppc_oldword.c to use qemu_ram_alloc() 

This patch uses qemu_ram_alloc() to allocate RAM, VGA RAM and VGA BIOS.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Laurent Vivier <Laurent@lvivier.info>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6114 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 12 additions and 9 deletions
hw/ppc_oldworld.c
  View file @a748ab6
@@ -34,6 +34,7 @@ @@ -34,6 +34,7 @@
34 #include "boards.h" 34 #include "boards.h"
35 35
36 #define MAX_IDE_BUS 2 36 #define MAX_IDE_BUS 2
  37 +#define VGA_BIOS_SIZE 65536
37 38
38 /* temporary frame buffer OSI calls for the video.x driver. The right 39 /* temporary frame buffer OSI calls for the video.x driver. The right
39 solution is to modify the driver to use VGA PCI I/Os */ 40 solution is to modify the driver to use VGA PCI I/Os */
@@ -116,7 +117,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size, @@ -116,7 +117,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
116 nvram_t nvram; 117 nvram_t nvram;
117 m48t59_t *m48t59; 118 m48t59_t *m48t59;
118 int linux_boot, i; 119 int linux_boot, i;
119 - unsigned long bios_offset, vga_bios_offset; 120 + ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset;
120 uint32_t kernel_base, kernel_size, initrd_base, initrd_size; 121 uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
121 PCIBus *pci_bus; 122 PCIBus *pci_bus;
122 MacIONVRAMState *nvr; 123 MacIONVRAMState *nvr;
@@ -154,10 +155,14 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size, @@ -154,10 +155,14 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
154 } 155 }
155 156
156 /* allocate RAM */ 157 /* allocate RAM */
157 - cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); 158 + ram_offset = qemu_ram_alloc(ram_size);
  159 + cpu_register_physical_memory(0, ram_size, ram_offset);
  160 +
  161 + /* allocate VGA RAM */
  162 + vga_ram_offset = qemu_ram_alloc(vga_ram_size);
158 163
159 /* allocate and load BIOS */ 164 /* allocate and load BIOS */
160 - bios_offset = ram_size + vga_ram_size; 165 + bios_offset = qemu_ram_alloc(BIOS_SIZE);
161 if (bios_name == NULL) 166 if (bios_name == NULL)
162 bios_name = BIOS_FILENAME; 167 bios_name = BIOS_FILENAME;
163 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); 168 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
@@ -166,7 +171,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size, @@ -166,7 +171,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
166 cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf); 171 cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
167 exit(1); 172 exit(1);
168 } 173 }
169 - bios_size = (bios_size + 0xfff) & ~0xfff;  
170 if (bios_size > 0x00080000) { 174 if (bios_size > 0x00080000) {
171 /* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */ 175 /* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
172 cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n"); 176 cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
@@ -175,7 +179,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size, @@ -175,7 +179,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
175 bios_size, bios_offset | IO_MEM_ROM); 179 bios_size, bios_offset | IO_MEM_ROM);
176 180
177 /* allocate and load VGA BIOS */ 181 /* allocate and load VGA BIOS */
178 - vga_bios_offset = bios_offset + bios_size; 182 + vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
179 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); 183 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
180 vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8); 184 vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
181 if (vga_bios_size < 0) { 185 if (vga_bios_size < 0) {
@@ -193,7 +197,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size, @@ -193,7 +197,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
193 vga_bios_size); 197 vga_bios_size);
194 vga_bios_size += 8; 198 vga_bios_size += 8;
195 } 199 }
196 - vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;  
197 200
198 if (linux_boot) { 201 if (linux_boot) {
199 kernel_base = KERNEL_LOAD_ADDR; 202 kernel_base = KERNEL_LOAD_ADDR;
@@ -278,8 +281,8 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size, @@ -278,8 +281,8 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
278 } 281 }
279 pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs); 282 pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
280 pci_bus = pci_grackle_init(0xfec00000, pic); 283 pci_bus = pci_grackle_init(0xfec00000, pic);
281 - pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,  
282 - ram_size, vga_ram_size, 284 + pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset,
  285 + vga_ram_offset, vga_ram_size,
283 vga_bios_offset, vga_bios_size); 286 vga_bios_offset, vga_bios_size);
284 287
285 /* XXX: suppress that */ 288 /* XXX: suppress that */
@@ -369,6 +372,6 @@ QEMUMachine heathrow_machine = { @@ -369,6 +372,6 @@ QEMUMachine heathrow_machine = {
369 .name = "g3bw", 372 .name = "g3bw",
370 .desc = "Heathrow based PowerMAC", 373 .desc = "Heathrow based PowerMAC",
371 .init = ppc_heathrow_init, 374 .init = ppc_heathrow_init,
372 - .ram_require = BIOS_SIZE + VGA_RAM_SIZE, 375 + .ram_require = BIOS_SIZE + VGA_BIOS_SIZE + VGA_RAM_SIZE,
373 .max_cpus = MAX_CPUS, 376 .max_cpus = MAX_CPUS,
374 }; 377 };