gwj / at91sam9263 · Commits

Commit a68156d016383c2f2fb183080b3f75ce0d32abd1

Authored by blueswir1
1 parent eee0b836

Constification 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2711 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 7 additions and 7 deletions
target-sparc/translate.c
  View file @a68156d
... ... @@ -108,7 +108,7 @@ static int sign_extend(int x, int len)
108 108  
109 109 static void disas_sparc_insn(DisasContext * dc);
110 110  
111   -static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
  111 +static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {
112 112 {
113 113 gen_op_movl_g0_T0,
114 114 gen_op_movl_g1_T0,
... ... @@ -179,7 +179,7 @@ static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
179 179 }
180 180 };
181 181  
182   -static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
  182 +static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {
183 183 {
184 184 gen_op_movl_T0_g0,
185 185 gen_op_movl_T0_g1,
... ... @@ -284,7 +284,7 @@ static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
284 284 }
285 285 };
286 286  
287   -static GenOpFunc1 *gen_op_movl_TN_im[3] = {
  287 +static GenOpFunc1 * const gen_op_movl_TN_im[3] = {
288 288 gen_op_movl_T0_im,
289 289 gen_op_movl_T1_im,
290 290 gen_op_movl_T2_im
... ... @@ -299,7 +299,7 @@ static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
299 299  
300 300 #ifdef TARGET_SPARC64
301 301 #define GEN32(func, NAME) \
302   -static GenOpFunc *NAME ## _table [64] = { \
  302 +static GenOpFunc * const NAME ## _table [64] = { \
303 303 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
304 304 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
305 305 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
... ... @@ -319,7 +319,7 @@ static inline void func(int n) \
319 319 }
320 320 #else
321 321 #define GEN32(func, NAME) \
322   -static GenOpFunc *NAME ## _table [32] = { \
  322 +static GenOpFunc *const NAME ## _table [32] = { \
323 323 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
324 324 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
325 325 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
... ... @@ -380,7 +380,7 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
380 380 #else
381 381 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
382 382 #define OP_LD_TABLE(width) \
383   - static GenOpFunc *gen_op_##width[] = { \
  383 + static GenOpFunc * const gen_op_##width[] = { \
384 384 &gen_op_##width##_user, \
385 385 &gen_op_##width##_kernel, \
386 386 }; \
... ... @@ -414,7 +414,7 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
414 414 #else
415 415 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
416 416 #define OP_LD_TABLE(width) \
417   -static GenOpFunc *gen_op_##width[] = { \
  417 +static GenOpFunc * const gen_op_##width[] = { \
418 418 &gen_op_##width##_user, \
419 419 &gen_op_##width##_kernel, \
420 420 }; \
... ...