Commit a63bdb31026648fef5d4ffb3caafc973c8ced53c
1 parent
a5580466
PL031 qdev conversion
Signed-off-by: Paul Brook <paul@codesourcery.com>
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5 changed files
with
16 additions
and
14 deletions
hw/integratorcp.c
... | ... | @@ -481,7 +481,7 @@ static void integratorcp_init(ram_addr_t ram_size, |
481 | 481 | cpu_pic[ARM_PIC_CPU_FIQ]); |
482 | 482 | icp_pic_init(0xca000000, pic[26], NULL); |
483 | 483 | icp_pit_init(0x13000000, pic, 5); |
484 | - pl031_init(0x15000000, pic[8]); | |
484 | + sysbus_create_simple("pl031", 0x15000000, pic[8]); | |
485 | 485 | sysbus_create_simple("pl011", 0x16000000, pic[1]); |
486 | 486 | sysbus_create_simple("pl011", 0x17000000, pic[2]); |
487 | 487 | icp_control_init(0xcb000000); | ... | ... |
hw/pl031.c
... | ... | @@ -9,8 +9,7 @@ |
9 | 9 | * |
10 | 10 | */ |
11 | 11 | |
12 | -#include "hw.h" | |
13 | -#include "primecell.h" | |
12 | +#include "sysbus.h" | |
14 | 13 | #include "qemu-timer.h" |
15 | 14 | |
16 | 15 | //#define DEBUG_PL031 |
... | ... | @@ -32,6 +31,7 @@ do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0) |
32 | 31 | #define RTC_ICR 0x1c /* Interrupt clear register */ |
33 | 32 | |
34 | 33 | typedef struct { |
34 | + SysBusDevice busdev; | |
35 | 35 | QEMUTimer *timer; |
36 | 36 | qemu_irq irq; |
37 | 37 | |
... | ... | @@ -183,25 +183,30 @@ static CPUReadMemoryFunc * pl031_readfn[] = { |
183 | 183 | pl031_read |
184 | 184 | }; |
185 | 185 | |
186 | -void pl031_init(uint32_t base, qemu_irq irq) | |
186 | +static void pl031_init(SysBusDevice *dev) | |
187 | 187 | { |
188 | 188 | int iomemtype; |
189 | - pl031_state *s; | |
189 | + pl031_state *s = FROM_SYSBUS(pl031_state, dev); | |
190 | 190 | struct tm tm; |
191 | 191 | |
192 | - s = qemu_mallocz(sizeof(pl031_state)); | |
193 | - | |
194 | 192 | iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s); |
195 | 193 | if (iomemtype == -1) { |
196 | 194 | hw_error("pl031_init: Can't register I/O memory\n"); |
197 | 195 | } |
198 | 196 | |
199 | - cpu_register_physical_memory(base, 0x00001000, iomemtype); | |
197 | + sysbus_init_mmio(dev, 0x1000, iomemtype); | |
200 | 198 | |
201 | - s->irq = irq; | |
199 | + sysbus_init_irq(dev, &s->irq); | |
202 | 200 | /* ??? We assume vm_clock is zero at this point. */ |
203 | 201 | qemu_get_timedate(&tm, 0); |
204 | 202 | s->tick_offset = mktimegm(&tm); |
205 | 203 | |
206 | 204 | s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s); |
207 | 205 | } |
206 | + | |
207 | +static void pl031_register_devices(void) | |
208 | +{ | |
209 | + sysbus_register_dev("pl031", sizeof(pl031_state), pl031_init); | |
210 | +} | |
211 | + | |
212 | +device_init(pl031_register_devices) | ... | ... |
hw/primecell.h
... | ... | @@ -5,9 +5,6 @@ |
5 | 5 | /* Also includes some devices that are currently only used by the |
6 | 6 | ARM boards. */ |
7 | 7 | |
8 | -/* pl031.c */ | |
9 | -void pl031_init(uint32_t base, qemu_irq irq); | |
10 | - | |
11 | 8 | /* pl022.c */ |
12 | 9 | typedef int (*ssi_xfer_cb)(void *, int); |
13 | 10 | void pl022_init(uint32_t base, qemu_irq irq, ssi_xfer_cb xfer_cb, | ... | ... |
hw/realview.c
... | ... | @@ -104,7 +104,7 @@ static void realview_init(ram_addr_t ram_size, |
104 | 104 | } |
105 | 105 | pl181_init(0x10005000, drives_table[index].bdrv, pic[17], pic[18]); |
106 | 106 | |
107 | - pl031_init(0x10017000, pic[10]); | |
107 | + sysbus_create_simple("pl031", 0x10017000, pic[10]); | |
108 | 108 | |
109 | 109 | pci_bus = pci_vpb_init(pic, 48, 1); |
110 | 110 | if (usb_enabled) { | ... | ... |
hw/versatilepb.c
... | ... | @@ -237,7 +237,7 @@ static void versatile_init(ram_addr_t ram_size, |
237 | 237 | #endif |
238 | 238 | |
239 | 239 | /* Add PL031 Real Time Clock. */ |
240 | - pl031_init(0x101e8000,pic[10]); | |
240 | + sysbus_create_simple("pl031", 0x101e8000, pic[10]); | |
241 | 241 | |
242 | 242 | /* Memory map for Versatile/PB: */ |
243 | 243 | /* 0x10000000 System registers. */ | ... | ... |