gwj / at91sam9263 · Commits

Commit a5a52cf24604c6ae1a1df898cc252f60583f172a

Authored by blueswir1
1 parent e19e4efe

Fix MMU registers, add more E-cache ASIs 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4881 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 64 additions and 10 deletions
target-sparc/op_helper.c
  View file @a5a52cf
@@ -1649,19 +1649,43 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) @@ -1649,19 +1649,43 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1649 } 1649 }
1650 case 0x51: // I-MMU 8k TSB pointer 1650 case 0x51: // I-MMU 8k TSB pointer
1651 case 0x52: // I-MMU 64k TSB pointer 1651 case 0x52: // I-MMU 64k TSB pointer
1652 - case 0x55: // I-MMU data access  
1653 // XXX 1652 // XXX
1654 break; 1653 break;
  1654 + case 0x55: // I-MMU data access
  1655 + {
  1656 + int reg = (addr >> 3) & 0x3f;
  1657 +
  1658 + ret = env->itlb_tte[reg];
  1659 + break;
  1660 + }
1655 case 0x56: // I-MMU tag read 1661 case 0x56: // I-MMU tag read
1656 { 1662 {
1657 unsigned int i; 1663 unsigned int i;
1658 1664
1659 for (i = 0; i < 64; i++) { 1665 for (i = 0; i < 64; i++) {
1660 // Valid, ctx match, vaddr match 1666 // Valid, ctx match, vaddr match
1661 - if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&  
1662 - env->itlb_tag[i] == addr) {  
1663 - ret = env->itlb_tag[i];  
1664 - break; 1667 + if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
  1668 + uint64_t mask;
  1669 +
  1670 + switch ((env->itlb_tte[i] >> 61) & 3) {
  1671 + default:
  1672 + case 0x0:
  1673 + mask = 0xffffffffffffffff;
  1674 + break;
  1675 + case 0x1:
  1676 + mask = 0xffffffffffff0fff;
  1677 + break;
  1678 + case 0x2:
  1679 + mask = 0xfffffffffff80fff;
  1680 + break;
  1681 + case 0x3:
  1682 + mask = 0xffffffffffc00fff;
  1683 + break;
  1684 + }
  1685 + if ((env->itlb_tag[i] & mask) == (addr & mask)) {
  1686 + ret = env->itlb_tte[i];
  1687 + break;
  1688 + }
1665 } 1689 }
1666 } 1690 }
1667 break; 1691 break;
@@ -1673,22 +1697,50 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) @@ -1673,22 +1697,50 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1673 ret = env->dmmuregs[reg]; 1697 ret = env->dmmuregs[reg];
1674 break; 1698 break;
1675 } 1699 }
  1700 + case 0x5d: // D-MMU data access
  1701 + {
  1702 + int reg = (addr >> 3) & 0x3f;
  1703 +
  1704 + ret = env->dtlb_tte[reg];
  1705 + break;
  1706 + }
1676 case 0x5e: // D-MMU tag read 1707 case 0x5e: // D-MMU tag read
1677 { 1708 {
1678 unsigned int i; 1709 unsigned int i;
1679 1710
1680 for (i = 0; i < 64; i++) { 1711 for (i = 0; i < 64; i++) {
1681 // Valid, ctx match, vaddr match 1712 // Valid, ctx match, vaddr match
1682 - if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&  
1683 - env->dtlb_tag[i] == addr) {  
1684 - ret = env->dtlb_tag[i];  
1685 - break; 1713 + if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
  1714 + uint64_t mask;
  1715 +
  1716 + switch ((env->dtlb_tte[i] >> 61) & 3) {
  1717 + default:
  1718 + case 0x0:
  1719 + mask = 0xffffffffffffffff;
  1720 + break;
  1721 + case 0x1:
  1722 + mask = 0xffffffffffff0fff;
  1723 + break;
  1724 + case 0x2:
  1725 + mask = 0xfffffffffff80fff;
  1726 + break;
  1727 + case 0x3:
  1728 + mask = 0xffffffffffc00fff;
  1729 + break;
  1730 + }
  1731 + if ((env->dtlb_tag[i] & mask) == (addr & mask)) {
  1732 + ret = env->dtlb_tte[i];
  1733 + break;
  1734 + }
1686 } 1735 }
1687 } 1736 }
1688 break; 1737 break;
1689 } 1738 }
1690 case 0x46: // D-cache data 1739 case 0x46: // D-cache data
1691 case 0x47: // D-cache tag access 1740 case 0x47: // D-cache tag access
  1741 + case 0x4b: // E-cache error enable
  1742 + case 0x4c: // E-cache asynchronous fault status
  1743 + case 0x4d: // E-cache asynchronous fault address
1692 case 0x4e: // E-cache tag data 1744 case 0x4e: // E-cache tag data
1693 case 0x66: // I-cache instruction access 1745 case 0x66: // I-cache instruction access
1694 case 0x67: // I-cache tag access 1746 case 0x67: // I-cache tag access
@@ -1700,7 +1752,6 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) @@ -1700,7 +1752,6 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1700 case 0x59: // D-MMU 8k TSB pointer 1752 case 0x59: // D-MMU 8k TSB pointer
1701 case 0x5a: // D-MMU 64k TSB pointer 1753 case 0x5a: // D-MMU 64k TSB pointer
1702 case 0x5b: // D-MMU data pointer 1754 case 0x5b: // D-MMU data pointer
1703 - case 0x5d: // D-MMU data access  
1704 case 0x48: // Interrupt dispatch, RO 1755 case 0x48: // Interrupt dispatch, RO
1705 case 0x49: // Interrupt data receive 1756 case 0x49: // Interrupt data receive
1706 case 0x7f: // Incoming interrupt vector, RO 1757 case 0x7f: // Incoming interrupt vector, RO
@@ -2052,6 +2103,9 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) @@ -2052,6 +2103,9 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
2052 return; 2103 return;
2053 case 0x46: // D-cache data 2104 case 0x46: // D-cache data
2054 case 0x47: // D-cache tag access 2105 case 0x47: // D-cache tag access
  2106 + case 0x4b: // E-cache error enable
  2107 + case 0x4c: // E-cache asynchronous fault status
  2108 + case 0x4d: // E-cache asynchronous fault address
2055 case 0x4e: // E-cache tag data 2109 case 0x4e: // E-cache tag data
2056 case 0x66: // I-cache instruction access 2110 case 0x66: // I-cache instruction access
2057 case 0x67: // I-cache tag access 2111 case 0x67: // I-cache tag access