gwj / at91sam9263 · Commits

Commit a4a771c055ea50f255f0d9a555c8628587afbea3

Authored by balrog
1 parent db8d9902

sh4: mmio based CF support on r2d board (Takashi YOSHII). 

 This patch adds emulation for a CompactFlash on sh4/r2d board.
 The device is CF, but wired to be worked as True-IDE mode, and connected
 directly to SH bus. So, this code is to support generally mmio based
 IDEs which are supported by "pata_platform" driver in linux kernel.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5924 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 102 additions and 0 deletions
Makefile.target
  View file @a4a771c
... ... @@ -711,6 +711,7 @@ endif
711 711 ifeq ($(TARGET_BASE_ARCH), sh4)
712 712 OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
713 713 OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sm501.o serial.o
  714 +OBJS+= ide.o
714 715 endif
715 716 ifeq ($(TARGET_BASE_ARCH), m68k)
716 717 OBJS+= an5206.o mcf5206.o ptimer.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
... ...
hw/ide.c
  View file @a4a771c
... ... @@ -3414,6 +3414,98 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq)
3414 3414 }
3415 3415  
3416 3416 /***********************************************************/
  3417 +/* MMIO based ide port
  3418 + * This emulates IDE device connected directly to the CPU bus without
  3419 + * dedicated ide controller, which is often seen on embedded boards.
  3420 + */
  3421 +
  3422 +typedef struct {
  3423 + void *dev;
  3424 + int shift;
  3425 +} MMIOState;
  3426 +
  3427 +static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
  3428 +{
  3429 + MMIOState *s = (MMIOState*)opaque;
  3430 + IDEState *ide = (IDEState*)s->dev;
  3431 + addr >>= s->shift;
  3432 + if (addr & 7)
  3433 + return ide_ioport_read(ide, addr);
  3434 + else
  3435 + return ide_data_readw(ide, 0);
  3436 +}
  3437 +
  3438 +static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
  3439 + uint32_t val)
  3440 +{
  3441 + MMIOState *s = (MMIOState*)opaque;
  3442 + IDEState *ide = (IDEState*)s->dev;
  3443 + addr >>= s->shift;
  3444 + if (addr & 7)
  3445 + ide_ioport_write(ide, addr, val);
  3446 + else
  3447 + ide_data_writew(ide, 0, val);
  3448 +}
  3449 +
  3450 +static CPUReadMemoryFunc *mmio_ide_reads[] = {
  3451 + mmio_ide_read,
  3452 + mmio_ide_read,
  3453 + mmio_ide_read,
  3454 +};
  3455 +
  3456 +static CPUWriteMemoryFunc *mmio_ide_writes[] = {
  3457 + mmio_ide_write,
  3458 + mmio_ide_write,
  3459 + mmio_ide_write,
  3460 +};
  3461 +
  3462 +static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
  3463 +{
  3464 + MMIOState *s= (MMIOState*)opaque;
  3465 + IDEState *ide = (IDEState*)s->dev;
  3466 + return ide_status_read(ide, 0);
  3467 +}
  3468 +
  3469 +static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
  3470 + uint32_t val)
  3471 +{
  3472 + MMIOState *s = (MMIOState*)opaque;
  3473 + IDEState *ide = (IDEState*)s->dev;
  3474 + ide_cmd_write(ide, 0, val);
  3475 +}
  3476 +
  3477 +static CPUReadMemoryFunc *mmio_ide_status[] = {
  3478 + mmio_ide_status_read,
  3479 + mmio_ide_status_read,
  3480 + mmio_ide_status_read,
  3481 +};
  3482 +
  3483 +static CPUWriteMemoryFunc *mmio_ide_cmd[] = {
  3484 + mmio_ide_cmd_write,
  3485 + mmio_ide_cmd_write,
  3486 + mmio_ide_cmd_write,
  3487 +};
  3488 +
  3489 +void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
  3490 + qemu_irq irq, int shift,
  3491 + BlockDriverState *hd0, BlockDriverState *hd1)
  3492 +{
  3493 + MMIOState *s = qemu_mallocz(sizeof(MMIOState));
  3494 + IDEState *ide = qemu_mallocz(sizeof(IDEState) * 2);
  3495 + int mem1, mem2;
  3496 +
  3497 + ide_init2(ide, hd0, hd1, irq);
  3498 +
  3499 + s->dev = ide;
  3500 + s->shift = shift;
  3501 +
  3502 + mem1 = cpu_register_io_memory(0, mmio_ide_reads, mmio_ide_writes, s);
  3503 + mem2 = cpu_register_io_memory(0, mmio_ide_status, mmio_ide_cmd, s);
  3504 + cpu_register_physical_memory(membase, 16 << shift, mem1);
  3505 + cpu_register_physical_memory(membase2, 2 << shift, mem2);
  3506 +}
  3507 +
  3508 +/***********************************************************/
3417 3509 /* CF-ATA Microdrive */
3418 3510  
3419 3511 #define METADATA_SIZE 0x20
... ...
hw/r2d.c
  View file @a4a771c
... ... @@ -149,6 +149,11 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
149 149 sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE);
150 150 sm501_init(ds, 0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
151 151 serial_hds[2]);
  152 +
  153 + /* onboard CF (True IDE mode, Master only). */
  154 + mmio_ide_init(0x14001000, 0x1400080c, NULL, 1,
  155 + drives_table[drive_get_index(IF_IDE, 0, 0)].bdrv, NULL);
  156 +
152 157 /* Todo: register on board registers */
153 158 {
154 159 int kernel_size;
... ...
... ... @@ -45,4 +45,8 @@ void sh_serial_init (target_phys_addr_t base, int feat,
45 45 /* tc58128.c */
46 46 int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2);
47 47  
  48 +/* ide.c */
  49 +void mmio_ide_init(target_phys_addr_t membase, target_phys_addr_t membase2,
  50 + qemu_irq irq, int shift,
  51 + BlockDriverState *hd0, BlockDriverState *hd1);
48 52 #endif
... ...