gwj / at91sam9263 · Commits

Commit a49ea279c4fcda7e6558bfe5b32a8d9aff0dd05b

Authored by pbrook
1 parent fe1479c3

Implement ARMv7 cp15 cache ID registers. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6105 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 28 additions and 7 deletions
target-arm/cpu.h
  View file @a49ea27
... ... @@ -100,6 +100,9 @@ typedef struct CPUARMState {
100 100 struct {
101 101 uint32_t c0_cpuid;
102 102 uint32_t c0_cachetype;
  103 + uint32_t c0_ccsid[16]; /* Cache size. */
  104 + uint32_t c0_clid; /* Cache level. */
  105 + uint32_t c0_cssel; /* Cache size selection. */
103 106 uint32_t c0_c1[8]; /* Feature registers. */
104 107 uint32_t c0_c2[8]; /* Instruction set registers. */
105 108 uint32_t c1_sys; /* System control register. */
... ...
target-arm/helper.c
  View file @a49ea27
... ... @@ -94,7 +94,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
94 94 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
95 95 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
96 96 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
97   - env->cp15.c0_cachetype = 0x1dd20d2;
  97 + env->cp15.c0_cachetype = 0x82048004;
  98 + env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
  99 + env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
  100 + env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
  101 + env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
98 102 break;
99 103 case ARM_CPUID_CORTEXM3:
100 104 set_feature(env, ARM_FEATURE_V6);
... ... @@ -1321,15 +1325,16 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
1321 1325 crm = insn & 0xf;
1322 1326 switch ((insn >> 16) & 0xf) {
1323 1327 case 0:
1324   - if (((insn >> 21) & 7) == 2) {
1325   - /* ??? Select cache level. Ignore. */
1326   - return;
1327   - }
1328 1328 /* ID codes. */
1329 1329 if (arm_feature(env, ARM_FEATURE_XSCALE))
1330 1330 break;
1331 1331 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1332 1332 break;
  1333 + if (arm_feature(env, ARM_FEATURE_V7)
  1334 + && op1 == 2 && crm == 0 && op2 == 0) {
  1335 + env->cp15.c0_cssel = val & 0xf;
  1336 + break;
  1337 + }
1333 1338 goto bad_reg;
1334 1339 case 1: /* System configuration. */
1335 1340 if (arm_feature(env, ARM_FEATURE_OMAPCP))
... ... @@ -1648,9 +1653,22 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
1648 1653 goto bad_reg;
1649 1654 if (crm != 0)
1650 1655 goto bad_reg;
1651   - if (arm_feature(env, ARM_FEATURE_XSCALE))
  1656 + if (!arm_feature(env, ARM_FEATURE_V7))
  1657 + return 0;
  1658 +
  1659 + switch (op2) {
  1660 + case 0:
  1661 + return env->cp15.c0_ccsid[env->cp15.c0_cssel];
  1662 + case 1:
  1663 + return env->cp15.c0_clid;
  1664 + case 7:
  1665 + return 0;
  1666 + }
  1667 + goto bad_reg;
  1668 + case 2:
  1669 + if (op2 != 0 || crm != 0)
1652 1670 goto bad_reg;
1653   - return 0;
  1671 + return env->cp15.c0_cssel;
1654 1672 default:
1655 1673 goto bad_reg;
1656 1674 }
... ...