gwj / at91sam9263 · Commits

Commit a46256129e80d993d23ed9d95566c79bcfa65e2d

Authored by aurel32
1 parent 3a8a44c4

SH4: convert simple compare instructions to TCG 

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5108 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 53 additions and 87 deletions
target-sh4/op.c
  View file @a462561
... ... @@ -37,12 +37,6 @@ static inline void cond_t(int cond)
37 37 clr_t();
38 38 }
39 39  
40   -void OPPROTO op_cmp_eq_imm_T0(void)
41   -{
42   - cond_t((int32_t) T0 == (int32_t) PARAM1);
43   - RETURN();
44   -}
45   -
46 40 void OPPROTO op_bf_s(void)
47 41 {
48 42 env->delayed_pc = PARAM1;
... ... @@ -144,36 +138,6 @@ void OPPROTO op_addv_T0_T1(void)
144 138 RETURN();
145 139 }
146 140  
147   -void OPPROTO op_cmp_eq_T0_T1(void)
148   -{
149   - cond_t(T1 == T0);
150   - RETURN();
151   -}
152   -
153   -void OPPROTO op_cmp_ge_T0_T1(void)
154   -{
155   - cond_t((int32_t) T1 >= (int32_t) T0);
156   - RETURN();
157   -}
158   -
159   -void OPPROTO op_cmp_gt_T0_T1(void)
160   -{
161   - cond_t((int32_t) T1 > (int32_t) T0);
162   - RETURN();
163   -}
164   -
165   -void OPPROTO op_cmp_hi_T0_T1(void)
166   -{
167   - cond_t((uint32_t) T1 > (uint32_t) T0);
168   - RETURN();
169   -}
170   -
171   -void OPPROTO op_cmp_hs_T0_T1(void)
172   -{
173   - cond_t((uint32_t) T1 >= (uint32_t) T0);
174   - RETURN();
175   -}
176   -
177 141 void OPPROTO op_cmp_str_T0_T1(void)
178 142 {
179 143 cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) ||
... ... @@ -183,12 +147,6 @@ void OPPROTO op_cmp_str_T0_T1(void)
183 147 RETURN();
184 148 }
185 149  
186   -void OPPROTO op_tst_T0_T1(void)
187   -{
188   - cond_t((T1 & T0) == 0);
189   - RETURN();
190   -}
191   -
192 150 void OPPROTO op_div0s_T0_T1(void)
193 151 {
194 152 if (T1 & 0x80000000)
... ... @@ -299,18 +257,6 @@ void OPPROTO op_trapa(void)
299 257 RETURN();
300 258 }
301 259  
302   -void OPPROTO op_cmp_pl_T0(void)
303   -{
304   - cond_t((int32_t) T0 > 0);
305   - RETURN();
306   -}
307   -
308   -void OPPROTO op_cmp_pz_T0(void)
309   -{
310   - cond_t((int32_t) T0 >= 0);
311   - RETURN();
312   -}
313   -
314 260 void OPPROTO op_jmp_T0(void)
315 261 {
316 262 env->delayed_pc = T0;
... ... @@ -610,18 +556,6 @@ void OPPROTO op_fmov_T0_frN(void)
610 556 RETURN();
611 557 }
612 558  
613   -void OPPROTO op_dt_rN(void)
614   -{
615   - cond_t((--env->gregs[PARAM1]) == 0);
616   - RETURN();
617   -}
618   -
619   -void OPPROTO op_tst_imm_rN(void)
620   -{
621   - cond_t((env->gregs[PARAM2] & PARAM1) == 0);
622   - RETURN();
623   -}
624   -
625 559 void OPPROTO op_movl_fpul_FT0(void)
626 560 {
627 561 FT0 = *(float32 *)&env->fpul;
... ... @@ -656,12 +590,6 @@ void OPPROTO op_movl_delayed_pc_PC(void)
656 590 RETURN();
657 591 }
658 592  
659   -void OPPROTO op_tst_imm_T0(void)
660   -{
661   - cond_t((T0 & PARAM1) == 0);
662   - RETURN();
663   -}
664   -
665 593 void OPPROTO op_raise_illegal_instruction(void)
666 594 {
667 595 env->exception_index = 0x180;
... ...
target-sh4/translate.c
  View file @a462561
... ... @@ -283,6 +283,40 @@ static void gen_delayed_conditional_jump(DisasContext * ctx)
283 283 gen_jump(ctx);
284 284 }
285 285  
  286 +static inline void gen_set_t(void)
  287 +{
  288 + tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
  289 +}
  290 +
  291 +static inline void gen_clr_t(void)
  292 +{
  293 + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
  294 +}
  295 +
  296 +static inline void gen_cmp(int cond, TCGv t0, TCGv t1)
  297 +{
  298 + int label1 = gen_new_label();
  299 + int label2 = gen_new_label();
  300 + tcg_gen_brcond_i32(cond, t1, t0, label1);
  301 + gen_clr_t();
  302 + tcg_gen_br(label2);
  303 + gen_set_label(label1);
  304 + gen_set_t();
  305 + gen_set_label(label2);
  306 +}
  307 +
  308 +static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm)
  309 +{
  310 + int label1 = gen_new_label();
  311 + int label2 = gen_new_label();
  312 + tcg_gen_brcondi_i32(cond, t0, imm, label1);
  313 + gen_clr_t();
  314 + tcg_gen_br(label2);
  315 + gen_set_label(label1);
  316 + gen_set_t();
  317 + gen_set_label(label2);
  318 +}
  319 +
286 320 #define B3_0 (ctx->opcode & 0xf)
287 321 #define B6_4 ((ctx->opcode >> 4) & 0x7)
288 322 #define B7_4 ((ctx->opcode >> 4) & 0xf)
... ... @@ -331,7 +365,7 @@ void _decode_opc(DisasContext * ctx)
331 365 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);
332 366 return;
333 367 case 0x0008: /* clrt */
334   - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
  368 + gen_clr_t();
335 369 return;
336 370 case 0x0038: /* ldtlb */
337 371 #if defined(CONFIG_USER_ONLY)
... ... @@ -349,7 +383,7 @@ void _decode_opc(DisasContext * ctx)
349 383 tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);
350 384 return;
351 385 case 0x0018: /* sett */
352   - tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
  386 + gen_set_t();
353 387 return;
354 388 case 0xfbfd: /* frchg */
355 389 gen_op_frchg();
... ... @@ -582,27 +616,27 @@ void _decode_opc(DisasContext * ctx)
582 616 case 0x3000: /* cmp/eq Rm,Rn */
583 617 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
584 618 tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
585   - gen_op_cmp_eq_T0_T1();
  619 + gen_cmp(TCG_COND_EQ, cpu_T[0], cpu_T[1]);
586 620 return;
587 621 case 0x3003: /* cmp/ge Rm,Rn */
588 622 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
589 623 tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
590   - gen_op_cmp_ge_T0_T1();
  624 + gen_cmp(TCG_COND_GE, cpu_T[0], cpu_T[1]);
591 625 return;
592 626 case 0x3007: /* cmp/gt Rm,Rn */
593 627 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
594 628 tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
595   - gen_op_cmp_gt_T0_T1();
  629 + gen_cmp(TCG_COND_GT, cpu_T[0], cpu_T[1]);
596 630 return;
597 631 case 0x3006: /* cmp/hi Rm,Rn */
598 632 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
599 633 tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
600   - gen_op_cmp_hi_T0_T1();
  634 + gen_cmp(TCG_COND_GTU, cpu_T[0], cpu_T[1]);
601 635 return;
602 636 case 0x3002: /* cmp/hs Rm,Rn */
603 637 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
604 638 tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
605   - gen_op_cmp_hs_T0_T1();
  639 + gen_cmp(TCG_COND_GEU, cpu_T[0], cpu_T[1]);
606 640 return;
607 641 case 0x200c: /* cmp/str Rm,Rn */
608 642 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
... ... @@ -737,7 +771,8 @@ void _decode_opc(DisasContext * ctx)
737 771 case 0x2008: /* tst Rm,Rn */
738 772 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
739 773 tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
740   - gen_op_tst_T0_T1();
  774 + tcg_gen_and_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
  775 + gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0);
741 776 return;
742 777 case 0x200a: /* xor Rm,Rn */
743 778 tcg_gen_xor_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]);
... ... @@ -911,7 +946,7 @@ void _decode_opc(DisasContext * ctx)
911 946 return;
912 947 case 0x8800: /* cmp/eq #imm,R0 */
913 948 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
914   - gen_op_cmp_eq_imm_T0(B7_0s);
  949 + gen_cmp_imm(TCG_COND_EQ, cpu_T[0], B7_0s);
915 950 return;
916 951 case 0xc400: /* mov.b @(disp,GBR),R0 */
917 952 gen_op_stc_gbr_T0();
... ... @@ -997,13 +1032,15 @@ void _decode_opc(DisasContext * ctx)
997 1032 ctx->bstate = BS_BRANCH;
998 1033 return;
999 1034 case 0xc800: /* tst #imm,R0 */
1000   - gen_op_tst_imm_rN(B7_0, REG(0));
  1035 + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(0)], B7_0);
  1036 + gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0);
1001 1037 return;
1002 1038 case 0xcc00: /* tst.b #imm,@(R0,GBR) */
1003 1039 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
1004 1040 tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
1005 1041 gen_op_ldub_T0_T0(ctx);
1006   - gen_op_tst_imm_T0(B7_0);
  1042 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0);
  1043 + gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0);
1007 1044 return;
1008 1045 case 0xca00: /* xor #imm,R0 */
1009 1046 tcg_gen_xori_i32(cpu_gregs[REG(0)], cpu_gregs[REG(0)], B7_0);
... ... @@ -1058,14 +1095,15 @@ void _decode_opc(DisasContext * ctx)
1058 1095 return;
1059 1096 case 0x4015: /* cmp/pl Rn */
1060 1097 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1061   - gen_op_cmp_pl_T0();
  1098 + gen_cmp_imm(TCG_COND_GT, cpu_T[0], 0);
1062 1099 return;
1063 1100 case 0x4011: /* cmp/pz Rn */
1064 1101 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1065   - gen_op_cmp_pz_T0();
  1102 + gen_cmp_imm(TCG_COND_GE, cpu_T[0], 0);
1066 1103 return;
1067 1104 case 0x4010: /* dt Rn */
1068   - gen_op_dt_rN(REG(B11_8));
  1105 + tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
  1106 + gen_cmp_imm(TCG_COND_EQ, cpu_gregs[REG(B11_8)], 0);
1069 1107 return;
1070 1108 case 0x402b: /* jmp @Rn */
1071 1109 CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
... ... @@ -1187,7 +1225,7 @@ void _decode_opc(DisasContext * ctx)
1187 1225 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1188 1226 tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
1189 1227 gen_op_ldub_T0_T0(ctx);
1190   - gen_op_cmp_eq_imm_T0(0);
  1228 + gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0);
1191 1229 tcg_gen_ori_i32(cpu_T[0], cpu_T[0], 0x80);
1192 1230 gen_op_stb_T0_T1(ctx);
1193 1231 return;
... ...