gwj / at91sam9263 · Commits

Commit a45db6c6fd587be85118038be3722c1dadeedfe4

Authored by aurel32
1 parent 2701dfd2

arm: Fix gic_irq_state.level bitfield type 

Found while cleaning up compiler warnings: GIC_*_LEVEL macros strongly
suggest that gic_irq_state.level is intended to be per-CPU and not just
a single, global bit. I'm unable to test the effect, but it seems to be
the most reasonable fix for the apparent brokenness.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6765 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 1 additions and 1 deletions
hw/arm_gic.c
  View file @a45db6c
... ... @@ -39,7 +39,7 @@ typedef struct gic_irq_state
39 39 unsigned enabled:1;
40 40 unsigned pending:NCPU;
41 41 unsigned active:NCPU;
42   - unsigned level:1;
  42 + unsigned level:NCPU;
43 43 unsigned model:1; /* 0 = N:N, 1 = 1:N */
44 44 unsigned trigger:1; /* nonzero = edge triggered. */
45 45 } gic_irq_state;
... ...