gwj / at91sam9263 · Commits

Commit a41bc9af8fc6fe89a7539f1c00e743f69643d744

Authored by bellard
1 parent 3bfd9da1

explicited S3 specific code - added more debug code 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@497 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 43 additions and 3 deletions
hw/vga.c
  View file @a41bc9a
... ... @@ -50,6 +50,10 @@
50 50  
51 51 //#define DEBUG_VGA
52 52 //#define DEBUG_VGA_MEM
  53 +//#define DEBUG_VGA_REG
  54 +
  55 +//#define DEBUG_S3
  56 +#define CONFIG_S3VGA
53 57  
54 58 #define MSR_COLOR_EMULATION 0x01
55 59 #define MSR_PAGE_SELECT 0x20
... ... @@ -252,6 +256,9 @@ static uint32_t vga_ioport_read(CPUX86State *env, uint32_t addr)
252 256 break;
253 257 case 0x3c5:
254 258 val = s->sr[s->sr_index];
  259 +#ifdef DEBUG_VGA_REG
  260 + printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
  261 +#endif
255 262 break;
256 263 case 0x3c7:
257 264 val = s->dac_state;
... ... @@ -274,6 +281,9 @@ static uint32_t vga_ioport_read(CPUX86State *env, uint32_t addr)
274 281 break;
275 282 case 0x3cf:
276 283 val = s->gr[s->gr_index];
  284 +#ifdef DEBUG_VGA_REG
  285 + printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
  286 +#endif
277 287 break;
278 288 case 0x3b4:
279 289 case 0x3d4:
... ... @@ -282,6 +292,14 @@ static uint32_t vga_ioport_read(CPUX86State *env, uint32_t addr)
282 292 case 0x3b5:
283 293 case 0x3d5:
284 294 val = s->cr[s->cr_index];
  295 +#ifdef DEBUG_VGA_REG
  296 + printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
  297 +#endif
  298 +#ifdef DEBUG_S3
  299 + if (s->cr_index >= 0x20)
  300 + printf("S3: CR read index=0x%x val=0x%x\n",
  301 + s->cr_index, val);
  302 +#endif
285 303 break;
286 304 case 0x3ba:
287 305 case 0x3da:
... ... @@ -354,6 +372,9 @@ static void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
354 372 s->sr_index = val & 7;
355 373 break;
356 374 case 0x3c5:
  375 +#ifdef DEBUG_VGA_REG
  376 + printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
  377 +#endif
357 378 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
358 379 break;
359 380 case 0x3c7:
... ... @@ -378,6 +399,9 @@ static void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
378 399 s->gr_index = val & 0x0f;
379 400 break;
380 401 case 0x3cf:
  402 +#ifdef DEBUG_VGA_REG
  403 + printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
  404 +#endif
381 405 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
382 406 break;
383 407 case 0x3b4:
... ... @@ -386,6 +410,9 @@ static void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
386 410 break;
387 411 case 0x3b5:
388 412 case 0x3d5:
  413 +#ifdef DEBUG_VGA_REG
  414 + printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
  415 +#endif
389 416 /* handle CR0-7 protection */
390 417 if ((s->cr[11] & 0x80) && s->cr_index <= 7) {
391 418 /* can always write bit 4 of CR7 */
... ... @@ -403,6 +430,7 @@ static void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
403 430 s->cr[s->cr_index] = val;
404 431 break;
405 432  
  433 +#ifdef CONFIG_S3VGA
406 434 /* S3 registers */
407 435 case 0x2d:
408 436 case 0x2e:
... ... @@ -422,10 +450,16 @@ static void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
422 450 v = val & 3;
423 451 s->cr[0x69] = (s->cr[69] & ~0x0c) | (v << 2);
424 452 break;
  453 +#endif
425 454 default:
426 455 s->cr[s->cr_index] = val;
427 456 break;
428 457 }
  458 +#ifdef DEBUG_S3
  459 + if (s->cr_index >= 0x20)
  460 + printf("S3: CR write index=0x%x val=0x%x\n",
  461 + s->cr_index, val);
  462 +#endif
429 463 break;
430 464 case 0x3ba:
431 465 case 0x3da:
... ... @@ -507,7 +541,6 @@ static uint32_t vga_mem_readl(uint32_t addr)
507 541 return v;
508 542 }
509 543  
510   -
511 544 /* called for accesses between 0xa0000 and 0xc0000 */
512 545 void vga_mem_writeb(uint32_t addr, uint32_t val)
513 546 {
... ... @@ -588,7 +621,7 @@ void vga_mem_writeb(uint32_t addr, uint32_t val)
588 621 case 3:
589 622 /* rotate */
590 623 b = s->gr[3] & 7;
591   - val = ((val >> b) | (val << (8 - b)));
  624 + val = (val >> b) | (val << (8 - b));
592 625  
593 626 bit_mask = s->gr[8] & val;
594 627 val = mask16[s->gr[0]];
... ... @@ -787,15 +820,20 @@ static int update_basic_params(VGAState *s)
787 820  
788 821 full_update = 0;
789 822 /* compute line_offset in bytes */
  823 + line_offset = s->cr[0x13];
  824 +#ifdef CONFIG_S3VGA
790 825 v = (s->cr[0x51] >> 4) & 3; /* S3 extension */
791 826 if (v == 0)
792 827 v = (s->cr[0x43] >> 2) & 1; /* S3 extension */
793   - line_offset = s->cr[0x13] | (v << 8);
  828 + line_offset |= (v << 8);
  829 +#endif
794 830 line_offset <<= 3;
795 831  
796 832 /* starting address */
797 833 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
  834 +#ifdef CONFIG_S3VGA
798 835 start_addr |= (s->cr[0x69] & 0x1f) << 16; /* S3 extension */
  836 +#endif
799 837  
800 838 /* line compare */
801 839 line_compare = s->cr[0x18] |
... ... @@ -1290,11 +1328,13 @@ void vga_update_display(void)
1290 1328 void vga_reset(VGAState *s)
1291 1329 {
1292 1330 memset(s, 0, sizeof(VGAState));
  1331 +#ifdef CONFIG_S3VGA
1293 1332 /* chip ID for 8c968 */
1294 1333 s->cr[0x2d] = 0x88;
1295 1334 s->cr[0x2e] = 0xb0;
1296 1335 s->cr[0x2f] = 0x01; /* XXX: check revision code */
1297 1336 s->cr[0x30] = 0xe1;
  1337 +#endif
1298 1338 s->graphic_mode = -1; /* force full update */
1299 1339 }
1300 1340  
... ...