Commit a41b2ff2ddd0ba05ac2ca1bb657603b1d09dc9bc
1 parent
d861b05e
Allow selection of emulated network card.
rtl8139 emulation. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1745 c046a42c-6fe2-441c-8c8c-71466251a162
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2983 additions
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25 deletions
Makefile.target
@@ -307,26 +307,29 @@ endif | @@ -307,26 +307,29 @@ endif | ||
307 | # USB layer | 307 | # USB layer |
308 | VL_OBJS+= usb.o usb-uhci.o usb-linux.o usb-hid.o | 308 | VL_OBJS+= usb.o usb-uhci.o usb-linux.o usb-hid.o |
309 | 309 | ||
310 | +# PCI network cards | ||
311 | +VL_OBJS+= ne2000.o rtl8139.o | ||
312 | + | ||
310 | ifeq ($(TARGET_BASE_ARCH), i386) | 313 | ifeq ($(TARGET_BASE_ARCH), i386) |
311 | # Hardware support | 314 | # Hardware support |
312 | -VL_OBJS+= ide.o ne2000.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o $(AUDIODRV) | 315 | +VL_OBJS+= ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o $(AUDIODRV) |
313 | VL_OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pc.o | 316 | VL_OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pc.o |
314 | VL_OBJS+= cirrus_vga.o mixeng.o apic.o parallel.o | 317 | VL_OBJS+= cirrus_vga.o mixeng.o apic.o parallel.o |
315 | DEFINES += -DHAS_AUDIO | 318 | DEFINES += -DHAS_AUDIO |
316 | endif | 319 | endif |
317 | ifeq ($(TARGET_BASE_ARCH), ppc) | 320 | ifeq ($(TARGET_BASE_ARCH), ppc) |
318 | -VL_OBJS+= ppc.o ide.o ne2000.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o $(AUDIODRV) | 321 | +VL_OBJS+= ppc.o ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o $(AUDIODRV) |
319 | VL_OBJS+= mc146818rtc.o serial.o i8259.o i8254.o fdc.o m48t59.o | 322 | VL_OBJS+= mc146818rtc.o serial.o i8259.o i8254.o fdc.o m48t59.o |
320 | VL_OBJS+= ppc_prep.o ppc_chrp.o cuda.o adb.o openpic.o heathrow_pic.o mixeng.o | 323 | VL_OBJS+= ppc_prep.o ppc_chrp.o cuda.o adb.o openpic.o heathrow_pic.o mixeng.o |
321 | DEFINES += -DHAS_AUDIO | 324 | DEFINES += -DHAS_AUDIO |
322 | endif | 325 | endif |
323 | ifeq ($(TARGET_ARCH), mips) | 326 | ifeq ($(TARGET_ARCH), mips) |
324 | -VL_OBJS+= mips_r4k.o dma.o vga.o serial.o ne2000.o i8254.o i8259.o | 327 | +VL_OBJS+= mips_r4k.o dma.o vga.o serial.o i8254.o i8259.o |
325 | #VL_OBJS+= #ide.o pckbd.o fdc.o m48t59.o | 328 | #VL_OBJS+= #ide.o pckbd.o fdc.o m48t59.o |
326 | endif | 329 | endif |
327 | ifeq ($(TARGET_BASE_ARCH), sparc) | 330 | ifeq ($(TARGET_BASE_ARCH), sparc) |
328 | ifeq ($(TARGET_ARCH), sparc64) | 331 | ifeq ($(TARGET_ARCH), sparc64) |
329 | -VL_OBJS+= sun4u.o ide.o ne2000.o pckbd.o ps2.o vga.o | 332 | +VL_OBJS+= sun4u.o ide.o pckbd.o ps2.o vga.o |
330 | VL_OBJS+= fdc.o mc146818rtc.o serial.o m48t59.o | 333 | VL_OBJS+= fdc.o mc146818rtc.o serial.o m48t59.o |
331 | VL_OBJS+= cirrus_vga.o parallel.o | 334 | VL_OBJS+= cirrus_vga.o parallel.o |
332 | VL_OBJS+= magic-load.o | 335 | VL_OBJS+= magic-load.o |
hw/integratorcp.c
@@ -1195,8 +1195,15 @@ static void integratorcp_init(int ram_size, int vga_ram_size, int boot_device, | @@ -1195,8 +1195,15 @@ static void integratorcp_init(int ram_size, int vga_ram_size, int boot_device, | ||
1195 | icp_control_init(0xcb000000); | 1195 | icp_control_init(0xcb000000); |
1196 | icp_kmi_init(0x18000000, pic, 3, 0); | 1196 | icp_kmi_init(0x18000000, pic, 3, 0); |
1197 | icp_kmi_init(0x19000000, pic, 4, 1); | 1197 | icp_kmi_init(0x19000000, pic, 4, 1); |
1198 | - if (nd_table[0].vlan) | ||
1199 | - smc91c111_init(&nd_table[0], 0xc8000000, pic, 27); | 1198 | + if (nd_table[0].vlan) { |
1199 | + if (nd_table[0].model == NULL | ||
1200 | + || strcmp(nd_table[0].model, "smc91c111") == 0) { | ||
1201 | + smc91c111_init(&nd_table[0], 0xc8000000, pic, 27); | ||
1202 | + } else { | ||
1203 | + fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | ||
1204 | + exit (1); | ||
1205 | + } | ||
1206 | + } | ||
1200 | 1207 | ||
1201 | /* Load the kernel. */ | 1208 | /* Load the kernel. */ |
1202 | if (!kernel_filename) { | 1209 | if (!kernel_filename) { |
hw/mips_r4k.c
@@ -272,8 +272,15 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, | @@ -272,8 +272,15 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, | ||
272 | vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size, | 272 | vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size, |
273 | vga_ram_size, 0, 0); | 273 | vga_ram_size, 0, 0); |
274 | 274 | ||
275 | - if (nd_table[0].vlan) | ||
276 | - isa_ne2000_init(0x300, 9, &nd_table[0]); | 275 | + if (nd_table[0].vlan) { |
276 | + if (nd_table[0].model == NULL | ||
277 | + || strcmp(nd_table[0].model, "ne2k_isa") == 0) { | ||
278 | + isa_ne2000_init(0x300, 9, &nd_table[0]); | ||
279 | + } else { | ||
280 | + fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | ||
281 | + exit (1); | ||
282 | + } | ||
283 | + } | ||
277 | } | 284 | } |
278 | 285 | ||
279 | QEMUMachine mips_machine = { | 286 | QEMUMachine mips_machine = { |
hw/pc.c
@@ -606,6 +606,16 @@ static void audio_init (PCIBus *pci_bus) | @@ -606,6 +606,16 @@ static void audio_init (PCIBus *pci_bus) | ||
606 | } | 606 | } |
607 | #endif | 607 | #endif |
608 | 608 | ||
609 | +static void pc_init_ne2k_isa(NICInfo *nd) | ||
610 | +{ | ||
611 | + static int nb_ne2k = 0; | ||
612 | + | ||
613 | + if (nb_ne2k == NE2000_NB_MAX) | ||
614 | + return; | ||
615 | + isa_ne2000_init(ne2000_io[nb_ne2k], ne2000_irq[nb_ne2k], nd); | ||
616 | + nb_ne2k++; | ||
617 | +} | ||
618 | + | ||
609 | /* PC hardware initialisation */ | 619 | /* PC hardware initialisation */ |
610 | static void pc_init1(int ram_size, int vga_ram_size, int boot_device, | 620 | static void pc_init1(int ram_size, int vga_ram_size, int boot_device, |
611 | DisplayState *ds, const char **fd_filename, int snapshot, | 621 | DisplayState *ds, const char **fd_filename, int snapshot, |
@@ -614,11 +624,12 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device, | @@ -614,11 +624,12 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device, | ||
614 | int pci_enabled) | 624 | int pci_enabled) |
615 | { | 625 | { |
616 | char buf[1024]; | 626 | char buf[1024]; |
617 | - int ret, linux_boot, initrd_size, i, nb_nics1; | 627 | + int ret, linux_boot, initrd_size, i; |
618 | unsigned long bios_offset, vga_bios_offset; | 628 | unsigned long bios_offset, vga_bios_offset; |
619 | int bios_size, isa_bios_size; | 629 | int bios_size, isa_bios_size; |
620 | PCIBus *pci_bus; | 630 | PCIBus *pci_bus; |
621 | CPUState *env; | 631 | CPUState *env; |
632 | + NICInfo *nd; | ||
622 | 633 | ||
623 | linux_boot = (kernel_filename != NULL); | 634 | linux_boot = (kernel_filename != NULL); |
624 | 635 | ||
@@ -800,19 +811,28 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device, | @@ -800,19 +811,28 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device, | ||
800 | } | 811 | } |
801 | } | 812 | } |
802 | 813 | ||
803 | - if (pci_enabled) { | ||
804 | - for(i = 0; i < nb_nics; i++) { | ||
805 | - pci_ne2000_init(pci_bus, &nd_table[i]); | 814 | + for(i = 0; i < nb_nics; i++) { |
815 | + nd = &nd_table[i]; | ||
816 | + if (!nd->model) { | ||
817 | + if (pci_enabled) { | ||
818 | + nd->model = "ne2k_pci"; | ||
819 | + } else { | ||
820 | + nd->model = "ne2k_isa"; | ||
821 | + } | ||
806 | } | 822 | } |
807 | - pci_piix3_ide_init(pci_bus, bs_table); | ||
808 | - } else { | ||
809 | - nb_nics1 = nb_nics; | ||
810 | - if (nb_nics1 > NE2000_NB_MAX) | ||
811 | - nb_nics1 = NE2000_NB_MAX; | ||
812 | - for(i = 0; i < nb_nics1; i++) { | ||
813 | - isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); | 823 | + if (strcmp(nd->model, "ne2k_isa") == 0) { |
824 | + pc_init_ne2k_isa(nd); | ||
825 | + } else if (pci_enabled) { | ||
826 | + pci_nic_init(pci_bus, nd); | ||
827 | + } else { | ||
828 | + fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); | ||
829 | + exit(1); | ||
814 | } | 830 | } |
831 | + } | ||
815 | 832 | ||
833 | + if (pci_enabled) { | ||
834 | + pci_piix3_ide_init(pci_bus, bs_table); | ||
835 | + } else { | ||
816 | for(i = 0; i < 2; i++) { | 836 | for(i = 0; i < 2; i++) { |
817 | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], | 837 | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
818 | bs_table[2 * i], bs_table[2 * i + 1]); | 838 | bs_table[2 * i], bs_table[2 * i + 1]); |
hw/pci.c
@@ -1837,3 +1837,17 @@ void pci_bios_init(void) | @@ -1837,3 +1837,17 @@ void pci_bios_init(void) | ||
1837 | } | 1837 | } |
1838 | } | 1838 | } |
1839 | } | 1839 | } |
1840 | + | ||
1841 | +/* Initialize a PCI NIC. */ | ||
1842 | +void pci_nic_init(PCIBus *bus, NICInfo *nd) | ||
1843 | +{ | ||
1844 | + if (strcmp(nd->model, "ne2k_pci") == 0) { | ||
1845 | + pci_ne2000_init(bus, nd); | ||
1846 | + } else if (strcmp(nd->model, "rtl8139") == 0) { | ||
1847 | + pci_rtl8139_init(bus, nd); | ||
1848 | + } else { | ||
1849 | + fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); | ||
1850 | + exit (1); | ||
1851 | + } | ||
1852 | +} | ||
1853 | + |
hw/ppc_chrp.c
@@ -436,7 +436,9 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device, | @@ -436,7 +436,9 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device, | ||
436 | serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); | 436 | serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); |
437 | 437 | ||
438 | for(i = 0; i < nb_nics; i++) { | 438 | for(i = 0; i < nb_nics; i++) { |
439 | - pci_ne2000_init(pci_bus, &nd_table[i]); | 439 | + if (!nd_table[i].model) |
440 | + nd_table[i].model = "ne2k_pci"; | ||
441 | + pci_nic_init(pci_bus, &nd_table[i]); | ||
440 | } | 442 | } |
441 | 443 | ||
442 | pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); | 444 | pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); |
hw/ppc_prep.c
@@ -624,7 +624,13 @@ static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, | @@ -624,7 +624,13 @@ static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, | ||
624 | if (nb_nics1 > NE2000_NB_MAX) | 624 | if (nb_nics1 > NE2000_NB_MAX) |
625 | nb_nics1 = NE2000_NB_MAX; | 625 | nb_nics1 = NE2000_NB_MAX; |
626 | for(i = 0; i < nb_nics1; i++) { | 626 | for(i = 0; i < nb_nics1; i++) { |
627 | - isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); | 627 | + if (nd_table[0].model == NULL |
628 | + || strcmp(nd_table[0].model, "ne2k_isa") == 0) { | ||
629 | + isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); | ||
630 | + } else { | ||
631 | + fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | ||
632 | + exit (1); | ||
633 | + } | ||
628 | } | 634 | } |
629 | 635 | ||
630 | for(i = 0; i < 2; i++) { | 636 | for(i = 0; i < 2; i++) { |
hw/rtl8139.c
0 โ 100644
1 | +/** | ||
2 | + * QEMU RTL8139 emulation | ||
3 | + * | ||
4 | + * Copyright (c) 2006 Igor Kovalenko | ||
5 | + * | ||
6 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
7 | + * of this software and associated documentation files (the "Software"), to deal | ||
8 | + * in the Software without restriction, including without limitation the rights | ||
9 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
10 | + * copies of the Software, and to permit persons to whom the Software is | ||
11 | + * furnished to do so, subject to the following conditions: | ||
12 | + * | ||
13 | + * The above copyright notice and this permission notice shall be included in | ||
14 | + * all copies or substantial portions of the Software. | ||
15 | + * | ||
16 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
21 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
22 | + * THE SOFTWARE. | ||
23 | + | ||
24 | + * Modifications: | ||
25 | + * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver) | ||
26 | + * | ||
27 | + */ | ||
28 | + | ||
29 | +#include "vl.h" | ||
30 | + | ||
31 | + | ||
32 | +/* debug RTL8139 card */ | ||
33 | +//#define DEBUG_RTL8139 1 | ||
34 | + | ||
35 | +/* debug RTL8139 card C+ mode only */ | ||
36 | +//#define DEBUG_RTL8139CP 1 | ||
37 | + | ||
38 | +/* RTL8139 provides frame CRC with received packet, this feature seems to be | ||
39 | + ignored by most drivers, disabled by default */ | ||
40 | +//#define RTL8139_CALCULATE_RXCRC 1 | ||
41 | + | ||
42 | + | ||
43 | +#if defined(RTL8139_CALCULATE_RXCRC) | ||
44 | +/* For crc32 */ | ||
45 | +#include <zlib.h> | ||
46 | +#endif | ||
47 | + | ||
48 | +#define SET_MASKED(input, mask, curr) \ | ||
49 | + ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) | ||
50 | + | ||
51 | +/* arg % size for size which is a power of 2 */ | ||
52 | +#define MOD2(input, size) \ | ||
53 | + ( ( input ) & ( size - 1 ) ) | ||
54 | + | ||
55 | +/* Symbolic offsets to registers. */ | ||
56 | +enum RTL8139_registers { | ||
57 | + MAC0 = 0, /* Ethernet hardware address. */ | ||
58 | + MAR0 = 8, /* Multicast filter. */ | ||
59 | + TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */ | ||
60 | + TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ | ||
61 | + RxBuf = 0x30, | ||
62 | + ChipCmd = 0x37, | ||
63 | + RxBufPtr = 0x38, | ||
64 | + RxBufAddr = 0x3A, | ||
65 | + IntrMask = 0x3C, | ||
66 | + IntrStatus = 0x3E, | ||
67 | + TxConfig = 0x40, | ||
68 | + RxConfig = 0x44, | ||
69 | + Timer = 0x48, /* A general-purpose counter. */ | ||
70 | + RxMissed = 0x4C, /* 24 bits valid, write clears. */ | ||
71 | + Cfg9346 = 0x50, | ||
72 | + Config0 = 0x51, | ||
73 | + Config1 = 0x52, | ||
74 | + FlashReg = 0x54, | ||
75 | + MediaStatus = 0x58, | ||
76 | + Config3 = 0x59, | ||
77 | + Config4 = 0x5A, /* absent on RTL-8139A */ | ||
78 | + HltClk = 0x5B, | ||
79 | + MultiIntr = 0x5C, | ||
80 | + PCIRevisionID = 0x5E, | ||
81 | + TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ | ||
82 | + BasicModeCtrl = 0x62, | ||
83 | + BasicModeStatus = 0x64, | ||
84 | + NWayAdvert = 0x66, | ||
85 | + NWayLPAR = 0x68, | ||
86 | + NWayExpansion = 0x6A, | ||
87 | + /* Undocumented registers, but required for proper operation. */ | ||
88 | + FIFOTMS = 0x70, /* FIFO Control and test. */ | ||
89 | + CSCR = 0x74, /* Chip Status and Configuration Register. */ | ||
90 | + PARA78 = 0x78, | ||
91 | + PARA7c = 0x7c, /* Magic transceiver parameter register. */ | ||
92 | + Config5 = 0xD8, /* absent on RTL-8139A */ | ||
93 | + /* C+ mode */ | ||
94 | + TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ | ||
95 | + RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ | ||
96 | + CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ | ||
97 | + IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ | ||
98 | + RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ | ||
99 | + RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ | ||
100 | + TxThresh = 0xEC, /* Early Tx threshold */ | ||
101 | +}; | ||
102 | + | ||
103 | +enum ClearBitMasks { | ||
104 | + MultiIntrClear = 0xF000, | ||
105 | + ChipCmdClear = 0xE2, | ||
106 | + Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), | ||
107 | +}; | ||
108 | + | ||
109 | +enum ChipCmdBits { | ||
110 | + CmdReset = 0x10, | ||
111 | + CmdRxEnb = 0x08, | ||
112 | + CmdTxEnb = 0x04, | ||
113 | + RxBufEmpty = 0x01, | ||
114 | +}; | ||
115 | + | ||
116 | +/* C+ mode */ | ||
117 | +enum CplusCmdBits { | ||
118 | + CPlusRxEnb = 0x0002, | ||
119 | + CPlusTxEnb = 0x0001, | ||
120 | +}; | ||
121 | + | ||
122 | +/* Interrupt register bits, using my own meaningful names. */ | ||
123 | +enum IntrStatusBits { | ||
124 | + PCIErr = 0x8000, | ||
125 | + PCSTimeout = 0x4000, | ||
126 | + RxFIFOOver = 0x40, | ||
127 | + RxUnderrun = 0x20, | ||
128 | + RxOverflow = 0x10, | ||
129 | + TxErr = 0x08, | ||
130 | + TxOK = 0x04, | ||
131 | + RxErr = 0x02, | ||
132 | + RxOK = 0x01, | ||
133 | + | ||
134 | + RxAckBits = RxFIFOOver | RxOverflow | RxOK, | ||
135 | +}; | ||
136 | + | ||
137 | +enum TxStatusBits { | ||
138 | + TxHostOwns = 0x2000, | ||
139 | + TxUnderrun = 0x4000, | ||
140 | + TxStatOK = 0x8000, | ||
141 | + TxOutOfWindow = 0x20000000, | ||
142 | + TxAborted = 0x40000000, | ||
143 | + TxCarrierLost = 0x80000000, | ||
144 | +}; | ||
145 | +enum RxStatusBits { | ||
146 | + RxMulticast = 0x8000, | ||
147 | + RxPhysical = 0x4000, | ||
148 | + RxBroadcast = 0x2000, | ||
149 | + RxBadSymbol = 0x0020, | ||
150 | + RxRunt = 0x0010, | ||
151 | + RxTooLong = 0x0008, | ||
152 | + RxCRCErr = 0x0004, | ||
153 | + RxBadAlign = 0x0002, | ||
154 | + RxStatusOK = 0x0001, | ||
155 | +}; | ||
156 | + | ||
157 | +/* Bits in RxConfig. */ | ||
158 | +enum rx_mode_bits { | ||
159 | + AcceptErr = 0x20, | ||
160 | + AcceptRunt = 0x10, | ||
161 | + AcceptBroadcast = 0x08, | ||
162 | + AcceptMulticast = 0x04, | ||
163 | + AcceptMyPhys = 0x02, | ||
164 | + AcceptAllPhys = 0x01, | ||
165 | +}; | ||
166 | + | ||
167 | +/* Bits in TxConfig. */ | ||
168 | +enum tx_config_bits { | ||
169 | + | ||
170 | + /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ | ||
171 | + TxIFGShift = 24, | ||
172 | + TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ | ||
173 | + TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ | ||
174 | + TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ | ||
175 | + TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ | ||
176 | + | ||
177 | + TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ | ||
178 | + TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ | ||
179 | + TxClearAbt = (1 << 0), /* Clear abort (WO) */ | ||
180 | + TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ | ||
181 | + TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ | ||
182 | + | ||
183 | + TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ | ||
184 | +}; | ||
185 | + | ||
186 | + | ||
187 | +/* Transmit Status of All Descriptors (TSAD) Register */ | ||
188 | +enum TSAD_bits { | ||
189 | + TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 | ||
190 | + TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 | ||
191 | + TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 | ||
192 | + TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 | ||
193 | + TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 | ||
194 | + TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 | ||
195 | + TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 | ||
196 | + TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 | ||
197 | + TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 | ||
198 | + TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 | ||
199 | + TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 | ||
200 | + TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 | ||
201 | + TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 | ||
202 | + TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 | ||
203 | + TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 | ||
204 | + TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 | ||
205 | +}; | ||
206 | + | ||
207 | + | ||
208 | +/* Bits in Config1 */ | ||
209 | +enum Config1Bits { | ||
210 | + Cfg1_PM_Enable = 0x01, | ||
211 | + Cfg1_VPD_Enable = 0x02, | ||
212 | + Cfg1_PIO = 0x04, | ||
213 | + Cfg1_MMIO = 0x08, | ||
214 | + LWAKE = 0x10, /* not on 8139, 8139A */ | ||
215 | + Cfg1_Driver_Load = 0x20, | ||
216 | + Cfg1_LED0 = 0x40, | ||
217 | + Cfg1_LED1 = 0x80, | ||
218 | + SLEEP = (1 << 1), /* only on 8139, 8139A */ | ||
219 | + PWRDN = (1 << 0), /* only on 8139, 8139A */ | ||
220 | +}; | ||
221 | + | ||
222 | +/* Bits in Config3 */ | ||
223 | +enum Config3Bits { | ||
224 | + Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ | ||
225 | + Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ | ||
226 | + Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ | ||
227 | + Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ | ||
228 | + Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ | ||
229 | + Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ | ||
230 | + Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ | ||
231 | + Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ | ||
232 | +}; | ||
233 | + | ||
234 | +/* Bits in Config4 */ | ||
235 | +enum Config4Bits { | ||
236 | + LWPTN = (1 << 2), /* not on 8139, 8139A */ | ||
237 | +}; | ||
238 | + | ||
239 | +/* Bits in Config5 */ | ||
240 | +enum Config5Bits { | ||
241 | + Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ | ||
242 | + Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ | ||
243 | + Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ | ||
244 | + Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ | ||
245 | + Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ | ||
246 | + Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ | ||
247 | + Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ | ||
248 | +}; | ||
249 | + | ||
250 | +enum RxConfigBits { | ||
251 | + /* rx fifo threshold */ | ||
252 | + RxCfgFIFOShift = 13, | ||
253 | + RxCfgFIFONone = (7 << RxCfgFIFOShift), | ||
254 | + | ||
255 | + /* Max DMA burst */ | ||
256 | + RxCfgDMAShift = 8, | ||
257 | + RxCfgDMAUnlimited = (7 << RxCfgDMAShift), | ||
258 | + | ||
259 | + /* rx ring buffer length */ | ||
260 | + RxCfgRcv8K = 0, | ||
261 | + RxCfgRcv16K = (1 << 11), | ||
262 | + RxCfgRcv32K = (1 << 12), | ||
263 | + RxCfgRcv64K = (1 << 11) | (1 << 12), | ||
264 | + | ||
265 | + /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ | ||
266 | + RxNoWrap = (1 << 7), | ||
267 | +}; | ||
268 | + | ||
269 | +/* Twister tuning parameters from RealTek. | ||
270 | + Completely undocumented, but required to tune bad links on some boards. */ | ||
271 | +/* | ||
272 | +enum CSCRBits { | ||
273 | + CSCR_LinkOKBit = 0x0400, | ||
274 | + CSCR_LinkChangeBit = 0x0800, | ||
275 | + CSCR_LinkStatusBits = 0x0f000, | ||
276 | + CSCR_LinkDownOffCmd = 0x003c0, | ||
277 | + CSCR_LinkDownCmd = 0x0f3c0, | ||
278 | +*/ | ||
279 | +enum CSCRBits { | ||
280 | + CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ | ||
281 | + CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ | ||
282 | + CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ | ||
283 | + CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ | ||
284 | + CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ | ||
285 | + CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ | ||
286 | + CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ | ||
287 | + CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ | ||
288 | + CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ | ||
289 | +}; | ||
290 | + | ||
291 | +enum Cfg9346Bits { | ||
292 | + Cfg9346_Lock = 0x00, | ||
293 | + Cfg9346_Unlock = 0xC0, | ||
294 | +}; | ||
295 | + | ||
296 | +typedef enum { | ||
297 | + CH_8139 = 0, | ||
298 | + CH_8139_K, | ||
299 | + CH_8139A, | ||
300 | + CH_8139A_G, | ||
301 | + CH_8139B, | ||
302 | + CH_8130, | ||
303 | + CH_8139C, | ||
304 | + CH_8100, | ||
305 | + CH_8100B_8139D, | ||
306 | + CH_8101, | ||
307 | +} chip_t; | ||
308 | + | ||
309 | +enum chip_flags { | ||
310 | + HasHltClk = (1 << 0), | ||
311 | + HasLWake = (1 << 1), | ||
312 | +}; | ||
313 | + | ||
314 | +#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ | ||
315 | + (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) | ||
316 | +#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) | ||
317 | + | ||
318 | +/* Size is 64 * 16bit words */ | ||
319 | +#define EEPROM_9346_ADDR_BITS 6 | ||
320 | +#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) | ||
321 | +#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) | ||
322 | + | ||
323 | +enum Chip9346Operation | ||
324 | +{ | ||
325 | + Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ | ||
326 | + Chip9346_op_read = 0x80, /* 10 AAAAAA */ | ||
327 | + Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ | ||
328 | + Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ | ||
329 | + Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ | ||
330 | + Chip9346_op_write_all = 0x10, /* 00 01zzzz */ | ||
331 | + Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ | ||
332 | +}; | ||
333 | + | ||
334 | +enum Chip9346Mode | ||
335 | +{ | ||
336 | + Chip9346_none = 0, | ||
337 | + Chip9346_enter_command_mode, | ||
338 | + Chip9346_read_command, | ||
339 | + Chip9346_data_read, /* from output register */ | ||
340 | + Chip9346_data_write, /* to input register, then to contents at specified address */ | ||
341 | + Chip9346_data_write_all, /* to input register, then filling contents */ | ||
342 | +}; | ||
343 | + | ||
344 | +typedef struct EEprom9346 | ||
345 | +{ | ||
346 | + uint16_t contents[EEPROM_9346_SIZE]; | ||
347 | + int mode; | ||
348 | + uint32_t tick; | ||
349 | + uint8_t address; | ||
350 | + uint16_t input; | ||
351 | + uint16_t output; | ||
352 | + | ||
353 | + uint8_t eecs; | ||
354 | + uint8_t eesk; | ||
355 | + uint8_t eedi; | ||
356 | + uint8_t eedo; | ||
357 | +} EEprom9346; | ||
358 | + | ||
359 | +typedef struct RTL8139State { | ||
360 | + uint8_t phys[8]; /* mac address */ | ||
361 | + uint8_t mult[8]; /* multicast mask array */ | ||
362 | + | ||
363 | + uint32_t TxStatus[4]; /* TxStatus0 */ | ||
364 | + uint32_t TxAddr[4]; /* TxAddr0 */ | ||
365 | + uint32_t RxBuf; /* Receive buffer */ | ||
366 | + uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */ | ||
367 | + uint32_t RxBufPtr; | ||
368 | + uint32_t RxBufAddr; | ||
369 | + | ||
370 | + uint16_t IntrStatus; | ||
371 | + uint16_t IntrMask; | ||
372 | + | ||
373 | + uint32_t TxConfig; | ||
374 | + uint32_t RxConfig; | ||
375 | + uint32_t RxMissed; | ||
376 | + | ||
377 | + uint16_t CSCR; | ||
378 | + | ||
379 | + uint8_t Cfg9346; | ||
380 | + uint8_t Config0; | ||
381 | + uint8_t Config1; | ||
382 | + uint8_t Config3; | ||
383 | + uint8_t Config4; | ||
384 | + uint8_t Config5; | ||
385 | + | ||
386 | + uint8_t clock_enabled; | ||
387 | + uint8_t bChipCmdState; | ||
388 | + | ||
389 | + uint16_t MultiIntr; | ||
390 | + | ||
391 | + uint16_t BasicModeCtrl; | ||
392 | + uint16_t BasicModeStatus; | ||
393 | + uint16_t NWayAdvert; | ||
394 | + uint16_t NWayLPAR; | ||
395 | + uint16_t NWayExpansion; | ||
396 | + | ||
397 | + uint16_t CpCmd; | ||
398 | + uint8_t TxThresh; | ||
399 | + | ||
400 | + int irq; | ||
401 | + PCIDevice *pci_dev; | ||
402 | + VLANClientState *vc; | ||
403 | + uint8_t macaddr[6]; | ||
404 | + int rtl8139_mmio_io_addr; | ||
405 | + | ||
406 | + /* C ring mode */ | ||
407 | + uint32_t currTxDesc; | ||
408 | + | ||
409 | + /* C+ mode */ | ||
410 | + uint32_t currCPlusRxDesc; | ||
411 | + uint32_t currCPlusTxDesc; | ||
412 | + | ||
413 | + uint32_t RxRingAddrLO; | ||
414 | + uint32_t RxRingAddrHI; | ||
415 | + | ||
416 | + EEprom9346 eeprom; | ||
417 | + | ||
418 | +} RTL8139State; | ||
419 | + | ||
420 | +void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) | ||
421 | +{ | ||
422 | +#if defined(DEBUG_RTL8139) | ||
423 | + printf("RTL8139: eeprom command 0x%02x\n", command); | ||
424 | +#endif | ||
425 | + | ||
426 | + switch (command & Chip9346_op_mask) | ||
427 | + { | ||
428 | + case Chip9346_op_read: | ||
429 | + { | ||
430 | + eeprom->address = command & EEPROM_9346_ADDR_MASK; | ||
431 | + eeprom->output = eeprom->contents[eeprom->address]; | ||
432 | + eeprom->eedo = 0; | ||
433 | + eeprom->tick = 0; | ||
434 | + eeprom->mode = Chip9346_data_read; | ||
435 | +#if defined(DEBUG_RTL8139) | ||
436 | + printf("RTL8139: eeprom read from address 0x%02x data=0x%04x\n", | ||
437 | + eeprom->address, eeprom->output); | ||
438 | +#endif | ||
439 | + } | ||
440 | + break; | ||
441 | + | ||
442 | + case Chip9346_op_write: | ||
443 | + { | ||
444 | + eeprom->address = command & EEPROM_9346_ADDR_MASK; | ||
445 | + eeprom->input = 0; | ||
446 | + eeprom->tick = 0; | ||
447 | + eeprom->mode = Chip9346_none; /* Chip9346_data_write */ | ||
448 | +#if defined(DEBUG_RTL8139) | ||
449 | + printf("RTL8139: eeprom begin write to address 0x%02x\n", | ||
450 | + eeprom->address); | ||
451 | +#endif | ||
452 | + } | ||
453 | + break; | ||
454 | + default: | ||
455 | + eeprom->mode = Chip9346_none; | ||
456 | + switch (command & Chip9346_op_ext_mask) | ||
457 | + { | ||
458 | + case Chip9346_op_write_enable: | ||
459 | +#if defined(DEBUG_RTL8139) | ||
460 | + printf("RTL8139: eeprom write enabled\n"); | ||
461 | +#endif | ||
462 | + break; | ||
463 | + case Chip9346_op_write_all: | ||
464 | +#if defined(DEBUG_RTL8139) | ||
465 | + printf("RTL8139: eeprom begin write all\n"); | ||
466 | +#endif | ||
467 | + break; | ||
468 | + case Chip9346_op_write_disable: | ||
469 | +#if defined(DEBUG_RTL8139) | ||
470 | + printf("RTL8139: eeprom write disabled\n"); | ||
471 | +#endif | ||
472 | + break; | ||
473 | + } | ||
474 | + break; | ||
475 | + } | ||
476 | +} | ||
477 | + | ||
478 | +void prom9346_shift_clock(EEprom9346 *eeprom) | ||
479 | +{ | ||
480 | + int bit = eeprom->eedi?1:0; | ||
481 | + | ||
482 | + ++ eeprom->tick; | ||
483 | + | ||
484 | +#if defined(DEBUG_RTL8139) | ||
485 | + printf("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo); | ||
486 | +#endif | ||
487 | + | ||
488 | + switch (eeprom->mode) | ||
489 | + { | ||
490 | + case Chip9346_enter_command_mode: | ||
491 | + if (bit) | ||
492 | + { | ||
493 | + eeprom->mode = Chip9346_read_command; | ||
494 | + eeprom->tick = 0; | ||
495 | + eeprom->input = 0; | ||
496 | +#if defined(DEBUG_RTL8139) | ||
497 | + printf("eeprom: +++ synchronized, begin command read\n"); | ||
498 | +#endif | ||
499 | + } | ||
500 | + break; | ||
501 | + | ||
502 | + case Chip9346_read_command: | ||
503 | + eeprom->input = (eeprom->input << 1) | (bit & 1); | ||
504 | + if (eeprom->tick == 8) | ||
505 | + { | ||
506 | + prom9346_decode_command(eeprom, eeprom->input & 0xff); | ||
507 | + } | ||
508 | + break; | ||
509 | + | ||
510 | + case Chip9346_data_read: | ||
511 | + eeprom->eedo = (eeprom->output & 0x8000)?1:0; | ||
512 | + eeprom->output <<= 1; | ||
513 | + if (eeprom->tick == 16) | ||
514 | + { | ||
515 | + ++eeprom->address; | ||
516 | + eeprom->address &= EEPROM_9346_ADDR_MASK; | ||
517 | + eeprom->output = eeprom->contents[eeprom->address]; | ||
518 | + eeprom->tick = 0; | ||
519 | + | ||
520 | +#if defined(DEBUG_RTL8139) | ||
521 | + printf("eeprom: +++ read next address 0x%02x data=0x%04x\n", | ||
522 | + eeprom->address, eeprom->output); | ||
523 | +#endif | ||
524 | + } | ||
525 | + break; | ||
526 | + | ||
527 | + case Chip9346_data_write: | ||
528 | + eeprom->input = (eeprom->input << 1) | (bit & 1); | ||
529 | + if (eeprom->tick == 16) | ||
530 | + { | ||
531 | +#if defined(DEBUG_RTL8139) | ||
532 | + printf("RTL8139: eeprom write to address 0x%02x data=0x%04x\n", | ||
533 | + eeprom->address, eeprom->input); | ||
534 | +#endif | ||
535 | + eeprom->contents[eeprom->address] = eeprom->input; | ||
536 | + eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ | ||
537 | + eeprom->tick = 0; | ||
538 | + eeprom->input = 0; | ||
539 | + } | ||
540 | + break; | ||
541 | + | ||
542 | + case Chip9346_data_write_all: | ||
543 | + eeprom->input = (eeprom->input << 1) | (bit & 1); | ||
544 | + if (eeprom->tick == 16) | ||
545 | + { | ||
546 | + int i; | ||
547 | + for (i = 0; i < EEPROM_9346_SIZE; i++) | ||
548 | + { | ||
549 | + eeprom->contents[i] = eeprom->input; | ||
550 | + } | ||
551 | +#if defined(DEBUG_RTL8139) | ||
552 | + printf("RTL8139: eeprom filled with data=0x%04x\n", | ||
553 | + eeprom->input); | ||
554 | +#endif | ||
555 | + eeprom->mode = Chip9346_enter_command_mode; | ||
556 | + eeprom->tick = 0; | ||
557 | + eeprom->input = 0; | ||
558 | + } | ||
559 | + break; | ||
560 | + | ||
561 | + default: | ||
562 | + break; | ||
563 | + } | ||
564 | +} | ||
565 | + | ||
566 | +int prom9346_get_wire(RTL8139State *s) | ||
567 | +{ | ||
568 | + EEprom9346 *eeprom = &s->eeprom; | ||
569 | + if (!eeprom->eecs) | ||
570 | + return 0; | ||
571 | + | ||
572 | + return eeprom->eedo; | ||
573 | +} | ||
574 | + | ||
575 | +void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) | ||
576 | +{ | ||
577 | + EEprom9346 *eeprom = &s->eeprom; | ||
578 | + uint8_t old_eecs = eeprom->eecs; | ||
579 | + uint8_t old_eesk = eeprom->eesk; | ||
580 | + | ||
581 | + eeprom->eecs = eecs; | ||
582 | + eeprom->eesk = eesk; | ||
583 | + eeprom->eedi = eedi; | ||
584 | + | ||
585 | +#if defined(DEBUG_RTL8139) | ||
586 | + printf("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo); | ||
587 | +#endif | ||
588 | + | ||
589 | + if (!old_eecs && eecs) | ||
590 | + { | ||
591 | + /* Synchronize start */ | ||
592 | + eeprom->tick = 0; | ||
593 | + eeprom->input = 0; | ||
594 | + eeprom->output = 0; | ||
595 | + eeprom->mode = Chip9346_enter_command_mode; | ||
596 | + | ||
597 | +#if defined(DEBUG_RTL8139) | ||
598 | + printf("=== eeprom: begin access, enter command mode\n"); | ||
599 | +#endif | ||
600 | + | ||
601 | + } | ||
602 | + | ||
603 | + if (!eecs) | ||
604 | + { | ||
605 | +#if defined(DEBUG_RTL8139) | ||
606 | + printf("=== eeprom: end access\n"); | ||
607 | +#endif | ||
608 | + return; | ||
609 | + } | ||
610 | + | ||
611 | + if (!old_eesk && eesk) | ||
612 | + { | ||
613 | + /* SK front rules */ | ||
614 | + prom9346_shift_clock(eeprom); | ||
615 | + } | ||
616 | +} | ||
617 | + | ||
618 | +static void rtl8139_update_irq(RTL8139State *s) | ||
619 | +{ | ||
620 | + int isr; | ||
621 | + isr = (s->IntrStatus & s->IntrMask) & 0xffff; | ||
622 | +#if defined(DEBUG_RTL8139) | ||
623 | + printf("RTL8139: Set IRQ line %d to %d (%04x %04x)\n", | ||
624 | + s->irq, isr ? 1 : 0, s->IntrStatus, s->IntrMask); | ||
625 | +#endif | ||
626 | + if (s->irq == 16) { | ||
627 | + /* PCI irq */ | ||
628 | + pci_set_irq(s->pci_dev, 0, (isr != 0)); | ||
629 | + } else { | ||
630 | + /* ISA irq */ | ||
631 | + pic_set_irq(s->irq, (isr != 0)); | ||
632 | + } | ||
633 | +} | ||
634 | + | ||
635 | +#define POLYNOMIAL 0x04c11db6 | ||
636 | + | ||
637 | +/* From FreeBSD */ | ||
638 | +/* XXX: optimize */ | ||
639 | +static int compute_mcast_idx(const uint8_t *ep) | ||
640 | +{ | ||
641 | + uint32_t crc; | ||
642 | + int carry, i, j; | ||
643 | + uint8_t b; | ||
644 | + | ||
645 | + crc = 0xffffffff; | ||
646 | + for (i = 0; i < 6; i++) { | ||
647 | + b = *ep++; | ||
648 | + for (j = 0; j < 8; j++) { | ||
649 | + carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); | ||
650 | + crc <<= 1; | ||
651 | + b >>= 1; | ||
652 | + if (carry) | ||
653 | + crc = ((crc ^ POLYNOMIAL) | carry); | ||
654 | + } | ||
655 | + } | ||
656 | + return (crc >> 26); | ||
657 | +} | ||
658 | + | ||
659 | +static int rtl8139_RxWrap(RTL8139State *s) | ||
660 | +{ | ||
661 | + /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */ | ||
662 | + return (s->RxConfig & (1 << 7)); | ||
663 | +} | ||
664 | + | ||
665 | +static int rtl8139_receiver_enabled(RTL8139State *s) | ||
666 | +{ | ||
667 | + return s->bChipCmdState & CmdRxEnb; | ||
668 | +} | ||
669 | + | ||
670 | +static int rtl8139_transmitter_enabled(RTL8139State *s) | ||
671 | +{ | ||
672 | + return s->bChipCmdState & CmdTxEnb; | ||
673 | +} | ||
674 | + | ||
675 | +static int rtl8139_cp_receiver_enabled(RTL8139State *s) | ||
676 | +{ | ||
677 | + return s->CpCmd & CPlusRxEnb; | ||
678 | +} | ||
679 | + | ||
680 | +static int rtl8139_cp_transmitter_enabled(RTL8139State *s) | ||
681 | +{ | ||
682 | + return s->CpCmd & CPlusTxEnb; | ||
683 | +} | ||
684 | + | ||
685 | +static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) | ||
686 | +{ | ||
687 | + if (s->RxBufAddr + size > s->RxBufferSize) | ||
688 | + { | ||
689 | + int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize); | ||
690 | + | ||
691 | + /* write packet data */ | ||
692 | + if (wrapped && s->RxBufferSize < 65536 && !rtl8139_RxWrap(s)) | ||
693 | + { | ||
694 | + #if defined(DEBUG_RTL8139) | ||
695 | + printf(">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped); | ||
696 | + #endif | ||
697 | + | ||
698 | + if (size > wrapped) | ||
699 | + { | ||
700 | + cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, | ||
701 | + buf, size-wrapped ); | ||
702 | + } | ||
703 | + | ||
704 | + /* reset buffer pointer */ | ||
705 | + s->RxBufAddr = 0; | ||
706 | + | ||
707 | + cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, | ||
708 | + buf + (size-wrapped), wrapped ); | ||
709 | + | ||
710 | + s->RxBufAddr = wrapped; | ||
711 | + | ||
712 | + return; | ||
713 | + } | ||
714 | + } | ||
715 | + | ||
716 | + /* non-wrapping path or overwrapping enabled */ | ||
717 | + cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size ); | ||
718 | + | ||
719 | + s->RxBufAddr += size; | ||
720 | +} | ||
721 | + | ||
722 | +#define MIN_BUF_SIZE 60 | ||
723 | +static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high) | ||
724 | +{ | ||
725 | +#if TARGET_PHYS_ADDR_BITS > 32 | ||
726 | + return low | ((target_phys_addr_t)high << 32); | ||
727 | +#else | ||
728 | + return low; | ||
729 | +#endif | ||
730 | +} | ||
731 | + | ||
732 | +static int rtl8139_can_receive(void *opaque) | ||
733 | +{ | ||
734 | + RTL8139State *s = opaque; | ||
735 | + int avail; | ||
736 | + | ||
737 | + /* Recieve (drop) packets if card is disabled. */ | ||
738 | + if (!s->clock_enabled) | ||
739 | + return 1; | ||
740 | + if (!rtl8139_receiver_enabled(s)) | ||
741 | + return 1; | ||
742 | + | ||
743 | + if (rtl8139_cp_receiver_enabled(s)) { | ||
744 | + /* ??? Flow control not implemented in c+ mode. | ||
745 | + This is a hack to work around slirp deficiencies anyway. */ | ||
746 | + return 1; | ||
747 | + } else { | ||
748 | + avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, | ||
749 | + s->RxBufferSize); | ||
750 | + return (avail == 0 || avail >= 1514); | ||
751 | + } | ||
752 | +} | ||
753 | + | ||
754 | +static void rtl8139_receive(void *opaque, const uint8_t *buf, int size) | ||
755 | +{ | ||
756 | + RTL8139State *s = opaque; | ||
757 | + | ||
758 | + uint32_t packet_header = 0; | ||
759 | + | ||
760 | + uint8_t buf1[60]; | ||
761 | + static const uint8_t broadcast_macaddr[6] = | ||
762 | + { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | ||
763 | + | ||
764 | +#if defined(DEBUG_RTL8139) | ||
765 | + printf(">>> RTL8139: received len=%d\n", size); | ||
766 | +#endif | ||
767 | + | ||
768 | + /* test if board clock is stopped */ | ||
769 | + if (!s->clock_enabled) | ||
770 | + { | ||
771 | +#if defined(DEBUG_RTL8139) | ||
772 | + printf("RTL8139: stopped ==========================\n"); | ||
773 | +#endif | ||
774 | + return; | ||
775 | + } | ||
776 | + | ||
777 | + /* first check if receiver is enabled */ | ||
778 | + | ||
779 | + if (!rtl8139_receiver_enabled(s)) | ||
780 | + { | ||
781 | +#if defined(DEBUG_RTL8139) | ||
782 | + printf("RTL8139: receiver disabled ================\n"); | ||
783 | +#endif | ||
784 | + return; | ||
785 | + } | ||
786 | + | ||
787 | + /* XXX: check this */ | ||
788 | + if (s->RxConfig & AcceptAllPhys) { | ||
789 | + /* promiscuous: receive all */ | ||
790 | +#if defined(DEBUG_RTL8139) | ||
791 | + printf(">>> RTL8139: packet received in promiscuous mode\n"); | ||
792 | +#endif | ||
793 | + | ||
794 | + } else { | ||
795 | + if (!memcmp(buf, broadcast_macaddr, 6)) { | ||
796 | + /* broadcast address */ | ||
797 | + if (!(s->RxConfig & AcceptBroadcast)) | ||
798 | + { | ||
799 | +#if defined(DEBUG_RTL8139) | ||
800 | + printf(">>> RTL8139: broadcast packet rejected\n"); | ||
801 | +#endif | ||
802 | + return; | ||
803 | + } | ||
804 | + | ||
805 | + packet_header |= RxBroadcast; | ||
806 | + | ||
807 | +#if defined(DEBUG_RTL8139) | ||
808 | + printf(">>> RTL8139: broadcast packet received\n"); | ||
809 | +#endif | ||
810 | + } else if (buf[0] & 0x01) { | ||
811 | + /* multicast */ | ||
812 | + if (!(s->RxConfig & AcceptMulticast)) | ||
813 | + { | ||
814 | +#if defined(DEBUG_RTL8139) | ||
815 | + printf(">>> RTL8139: multicast packet rejected\n"); | ||
816 | +#endif | ||
817 | + return; | ||
818 | + } | ||
819 | + | ||
820 | + int mcast_idx = compute_mcast_idx(buf); | ||
821 | + | ||
822 | + if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) | ||
823 | + { | ||
824 | +#if defined(DEBUG_RTL8139) | ||
825 | + printf(">>> RTL8139: multicast address mismatch\n"); | ||
826 | +#endif | ||
827 | + return; | ||
828 | + } | ||
829 | + | ||
830 | + packet_header |= RxMulticast; | ||
831 | + | ||
832 | +#if defined(DEBUG_RTL8139) | ||
833 | + printf(">>> RTL8139: multicast packet received\n"); | ||
834 | +#endif | ||
835 | + } else if (s->phys[0] == buf[0] && | ||
836 | + s->phys[1] == buf[1] && | ||
837 | + s->phys[2] == buf[2] && | ||
838 | + s->phys[3] == buf[3] && | ||
839 | + s->phys[4] == buf[4] && | ||
840 | + s->phys[5] == buf[5]) { | ||
841 | + /* match */ | ||
842 | + if (!(s->RxConfig & AcceptMyPhys)) | ||
843 | + { | ||
844 | +#if defined(DEBUG_RTL8139) | ||
845 | + printf(">>> RTL8139: rejecting physical address matching packet\n"); | ||
846 | +#endif | ||
847 | + return; | ||
848 | + } | ||
849 | + | ||
850 | + packet_header |= RxPhysical; | ||
851 | + | ||
852 | +#if defined(DEBUG_RTL8139) | ||
853 | + printf(">>> RTL8139: physical address matching packet received\n"); | ||
854 | +#endif | ||
855 | + | ||
856 | + } else { | ||
857 | + | ||
858 | +#if defined(DEBUG_RTL8139) | ||
859 | + printf(">>> RTL8139: unknown packet\n"); | ||
860 | +#endif | ||
861 | + return; | ||
862 | + } | ||
863 | + } | ||
864 | + | ||
865 | + /* if too small buffer, then expand it */ | ||
866 | + if (size < MIN_BUF_SIZE) { | ||
867 | + memcpy(buf1, buf, size); | ||
868 | + memset(buf1 + size, 0, MIN_BUF_SIZE - size); | ||
869 | + buf = buf1; | ||
870 | + size = MIN_BUF_SIZE; | ||
871 | + } | ||
872 | + | ||
873 | + if (rtl8139_cp_receiver_enabled(s)) | ||
874 | + { | ||
875 | +#if defined(DEBUG_RTL8139) | ||
876 | + printf("RTL8139: in C+ Rx mode ================\n"); | ||
877 | +#endif | ||
878 | + | ||
879 | + /* begin C+ receiver mode */ | ||
880 | + | ||
881 | +/* w0 ownership flag */ | ||
882 | +#define CP_RX_OWN (1<<31) | ||
883 | +/* w0 end of ring flag */ | ||
884 | +#define CP_RX_EOR (1<<30) | ||
885 | +/* w0 bits 0...12 : buffer size */ | ||
886 | +#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) | ||
887 | +/* w1 tag available flag */ | ||
888 | +#define CP_RX_TAVA (1<<16) | ||
889 | +/* w1 bits 0...15 : VLAN tag */ | ||
890 | +#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) | ||
891 | +/* w2 low 32bit of Rx buffer ptr */ | ||
892 | +/* w3 high 32bit of Rx buffer ptr */ | ||
893 | + | ||
894 | + int descriptor = s->currCPlusRxDesc; | ||
895 | + target_phys_addr_t cplus_rx_ring_desc; | ||
896 | + | ||
897 | + cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); | ||
898 | + cplus_rx_ring_desc += 16 * descriptor; | ||
899 | + | ||
900 | +#ifdef DEBUG_RTL8139 | ||
901 | + printf("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = 0x%8lx\n", | ||
902 | + descriptor, s->RxRingAddrHI, s->RxRingAddrLO, cplus_rx_ring_desc); | ||
903 | +#endif | ||
904 | + | ||
905 | + uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; | ||
906 | + | ||
907 | + cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4); | ||
908 | + rxdw0 = le32_to_cpu(val); | ||
909 | + cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4); | ||
910 | + rxdw1 = le32_to_cpu(val); | ||
911 | + cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4); | ||
912 | + rxbufLO = le32_to_cpu(val); | ||
913 | + cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4); | ||
914 | + rxbufHI = le32_to_cpu(val); | ||
915 | + | ||
916 | +#ifdef DEBUG_RTL8139 | ||
917 | + printf("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n", | ||
918 | + descriptor, | ||
919 | + rxdw0, rxdw1, rxbufLO, rxbufHI); | ||
920 | +#endif | ||
921 | + | ||
922 | + if (!(rxdw0 & CP_RX_OWN)) | ||
923 | + { | ||
924 | +#if defined(DEBUG_RTL8139) | ||
925 | + printf("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor); | ||
926 | +#endif | ||
927 | + s->IntrStatus |= RxOverflow; | ||
928 | + ++s->RxMissed; | ||
929 | + rtl8139_update_irq(s); | ||
930 | + return; | ||
931 | + } | ||
932 | + | ||
933 | + uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; | ||
934 | + | ||
935 | + if (size+4 > rx_space) | ||
936 | + { | ||
937 | +#if defined(DEBUG_RTL8139) | ||
938 | + printf("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n", | ||
939 | + descriptor, rx_space, size); | ||
940 | +#endif | ||
941 | + s->IntrStatus |= RxOverflow; | ||
942 | + ++s->RxMissed; | ||
943 | + rtl8139_update_irq(s); | ||
944 | + return; | ||
945 | + } | ||
946 | + | ||
947 | + target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); | ||
948 | + | ||
949 | + /* receive/copy to target memory */ | ||
950 | + cpu_physical_memory_write( rx_addr, buf, size ); | ||
951 | + | ||
952 | + /* write checksum */ | ||
953 | +#if defined (RTL8139_CALCULATE_RXCRC) | ||
954 | + val = cpu_to_le32(crc32(~0, buf, size)); | ||
955 | +#else | ||
956 | + val = 0; | ||
957 | +#endif | ||
958 | + cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4); | ||
959 | + | ||
960 | +/* first segment of received packet flag */ | ||
961 | +#define CP_RX_STATUS_FS (1<<29) | ||
962 | +/* last segment of received packet flag */ | ||
963 | +#define CP_RX_STATUS_LS (1<<28) | ||
964 | +/* multicast packet flag */ | ||
965 | +#define CP_RX_STATUS_MAR (1<<26) | ||
966 | +/* physical-matching packet flag */ | ||
967 | +#define CP_RX_STATUS_PAM (1<<25) | ||
968 | +/* broadcast packet flag */ | ||
969 | +#define CP_RX_STATUS_BAR (1<<24) | ||
970 | +/* runt packet flag */ | ||
971 | +#define CP_RX_STATUS_RUNT (1<<19) | ||
972 | +/* crc error flag */ | ||
973 | +#define CP_RX_STATUS_CRC (1<<18) | ||
974 | +/* IP checksum error flag */ | ||
975 | +#define CP_RX_STATUS_IPF (1<<15) | ||
976 | +/* UDP checksum error flag */ | ||
977 | +#define CP_RX_STATUS_UDPF (1<<14) | ||
978 | +/* TCP checksum error flag */ | ||
979 | +#define CP_RX_STATUS_TCPF (1<<13) | ||
980 | + | ||
981 | + /* transfer ownership to target */ | ||
982 | + rxdw0 &= ~CP_RX_OWN; | ||
983 | + | ||
984 | + /* set first segment bit */ | ||
985 | + rxdw0 |= CP_RX_STATUS_FS; | ||
986 | + | ||
987 | + /* set last segment bit */ | ||
988 | + rxdw0 |= CP_RX_STATUS_LS; | ||
989 | + | ||
990 | + /* set received packet type flags */ | ||
991 | + if (packet_header & RxBroadcast) | ||
992 | + rxdw0 |= CP_RX_STATUS_BAR; | ||
993 | + if (packet_header & RxMulticast) | ||
994 | + rxdw0 |= CP_RX_STATUS_MAR; | ||
995 | + if (packet_header & RxPhysical) | ||
996 | + rxdw0 |= CP_RX_STATUS_PAM; | ||
997 | + | ||
998 | + /* set received size */ | ||
999 | + rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; | ||
1000 | + rxdw0 |= (size+4); | ||
1001 | + | ||
1002 | + /* reset VLAN tag flag */ | ||
1003 | + rxdw1 &= ~CP_RX_TAVA; | ||
1004 | + | ||
1005 | + /* update ring data */ | ||
1006 | + val = cpu_to_le32(rxdw0); | ||
1007 | + cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4); | ||
1008 | + val = cpu_to_le32(rxdw1); | ||
1009 | + cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4); | ||
1010 | + | ||
1011 | + /* seek to next Rx descriptor */ | ||
1012 | + if (rxdw0 & CP_RX_EOR) | ||
1013 | + { | ||
1014 | + s->currCPlusRxDesc = 0; | ||
1015 | + } | ||
1016 | + else | ||
1017 | + { | ||
1018 | + ++s->currCPlusRxDesc; | ||
1019 | + } | ||
1020 | + | ||
1021 | +#if defined(DEBUG_RTL8139) | ||
1022 | + printf("RTL8139: done C+ Rx mode ----------------\n"); | ||
1023 | +#endif | ||
1024 | + | ||
1025 | + } | ||
1026 | + else | ||
1027 | + { | ||
1028 | +#if defined(DEBUG_RTL8139) | ||
1029 | + printf("RTL8139: in ring Rx mode ================\n"); | ||
1030 | +#endif | ||
1031 | + /* begin ring receiver mode */ | ||
1032 | + int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize); | ||
1033 | + | ||
1034 | + /* if receiver buffer is empty then avail == 0 */ | ||
1035 | + | ||
1036 | + if (avail != 0 && size + 8 >= avail) | ||
1037 | + { | ||
1038 | +#if defined(DEBUG_RTL8139) | ||
1039 | + printf("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n", | ||
1040 | + s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); | ||
1041 | +#endif | ||
1042 | + s->IntrStatus |= RxOverflow; | ||
1043 | + ++s->RxMissed; | ||
1044 | + rtl8139_update_irq(s); | ||
1045 | + return; | ||
1046 | + } | ||
1047 | + | ||
1048 | + packet_header |= RxStatusOK; | ||
1049 | + | ||
1050 | + packet_header |= (((size+4) << 16) & 0xffff0000); | ||
1051 | + | ||
1052 | + /* write header */ | ||
1053 | + uint32_t val = cpu_to_le32(packet_header); | ||
1054 | + | ||
1055 | + rtl8139_write_buffer(s, (uint8_t *)&val, 4); | ||
1056 | + | ||
1057 | + rtl8139_write_buffer(s, buf, size); | ||
1058 | + | ||
1059 | + /* write checksum */ | ||
1060 | +#if defined (RTL8139_CALCULATE_RXCRC) | ||
1061 | + val = cpu_to_le32(crc32(~0, buf, size)); | ||
1062 | +#else | ||
1063 | + val = 0; | ||
1064 | +#endif | ||
1065 | + | ||
1066 | + rtl8139_write_buffer(s, (uint8_t *)&val, 4); | ||
1067 | + | ||
1068 | + /* correct buffer write pointer */ | ||
1069 | + s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize); | ||
1070 | + | ||
1071 | + /* now we can signal we have received something */ | ||
1072 | + | ||
1073 | +#if defined(DEBUG_RTL8139) | ||
1074 | + printf(" received: rx buffer length %d head 0x%04x read 0x%04x\n", | ||
1075 | + s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); | ||
1076 | +#endif | ||
1077 | + | ||
1078 | + } | ||
1079 | + | ||
1080 | + s->IntrStatus |= RxOK; | ||
1081 | + rtl8139_update_irq(s); | ||
1082 | +} | ||
1083 | + | ||
1084 | +static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) | ||
1085 | +{ | ||
1086 | + s->RxBufferSize = bufferSize; | ||
1087 | + s->RxBufPtr = 0; | ||
1088 | + s->RxBufAddr = 0; | ||
1089 | +} | ||
1090 | + | ||
1091 | +static void rtl8139_reset(RTL8139State *s) | ||
1092 | +{ | ||
1093 | + int i; | ||
1094 | + | ||
1095 | + /* restore MAC address */ | ||
1096 | + memcpy(s->phys, s->macaddr, 6); | ||
1097 | + | ||
1098 | + /* reset interrupt mask */ | ||
1099 | + s->IntrStatus = 0; | ||
1100 | + s->IntrMask = 0; | ||
1101 | + | ||
1102 | + rtl8139_update_irq(s); | ||
1103 | + | ||
1104 | + /* prepare eeprom */ | ||
1105 | + s->eeprom.contents[0] = 0x8129; | ||
1106 | + memcpy(&s->eeprom.contents[7], s->macaddr, 6); | ||
1107 | + | ||
1108 | + /* mark all status registers as owned by host */ | ||
1109 | + for (i = 0; i < 4; ++i) | ||
1110 | + { | ||
1111 | + s->TxStatus[i] = TxHostOwns; | ||
1112 | + } | ||
1113 | + | ||
1114 | + s->currTxDesc = 0; | ||
1115 | + s->currCPlusRxDesc = 0; | ||
1116 | + s->currCPlusTxDesc = 0; | ||
1117 | + | ||
1118 | + s->RxRingAddrLO = 0; | ||
1119 | + s->RxRingAddrHI = 0; | ||
1120 | + | ||
1121 | + s->RxBuf = 0; | ||
1122 | + | ||
1123 | + rtl8139_reset_rxring(s, 8192); | ||
1124 | + | ||
1125 | + /* ACK the reset */ | ||
1126 | + s->TxConfig = 0; | ||
1127 | + | ||
1128 | +#if 0 | ||
1129 | +// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk | ||
1130 | + s->clock_enabled = 0; | ||
1131 | +#else | ||
1132 | + s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 0, 0); // RTL-8139C HasLWake | ||
1133 | + s->clock_enabled = 1; | ||
1134 | +#endif | ||
1135 | + | ||
1136 | + s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */; | ||
1137 | + | ||
1138 | + /* set initial state data */ | ||
1139 | + s->Config0 = 0x0; /* No boot ROM */ | ||
1140 | + s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ | ||
1141 | + s->Config3 = 0x1; /* fast back-to-back compatible */ | ||
1142 | + s->Config5 = 0x0; | ||
1143 | + | ||
1144 | + s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; | ||
1145 | + | ||
1146 | + s->CpCmd = 0x0; /* reset C+ mode */ | ||
1147 | + | ||
1148 | +// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation | ||
1149 | +// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex | ||
1150 | + s->BasicModeCtrl = 0x1000; // autonegotiation | ||
1151 | + | ||
1152 | + s->BasicModeStatus = 0x7809; | ||
1153 | + //s->BasicModeStatus |= 0x0040; /* UTP medium */ | ||
1154 | + s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ | ||
1155 | + s->BasicModeStatus |= 0x0004; /* link is up */ | ||
1156 | + | ||
1157 | + s->NWayAdvert = 0x05e1; /* all modes, full duplex */ | ||
1158 | + s->NWayLPAR = 0x05e1; /* all modes, full duplex */ | ||
1159 | + s->NWayExpansion = 0x0001; /* autonegotiation supported */ | ||
1160 | +} | ||
1161 | + | ||
1162 | +static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) | ||
1163 | +{ | ||
1164 | + val &= 0xff; | ||
1165 | + | ||
1166 | +#ifdef DEBUG_RTL8139 | ||
1167 | + printf("RTL8139: ChipCmd write val=0x%08x\n", val); | ||
1168 | +#endif | ||
1169 | + | ||
1170 | + if (val & CmdReset) | ||
1171 | + { | ||
1172 | +#ifdef DEBUG_RTL8139 | ||
1173 | + printf("RTL8139: ChipCmd reset\n"); | ||
1174 | +#endif | ||
1175 | + rtl8139_reset(s); | ||
1176 | + } | ||
1177 | + if (val & CmdRxEnb) | ||
1178 | + { | ||
1179 | +#ifdef DEBUG_RTL8139 | ||
1180 | + printf("RTL8139: ChipCmd enable receiver\n"); | ||
1181 | +#endif | ||
1182 | + } | ||
1183 | + if (val & CmdTxEnb) | ||
1184 | + { | ||
1185 | +#ifdef DEBUG_RTL8139 | ||
1186 | + printf("RTL8139: ChipCmd enable transmitter\n"); | ||
1187 | +#endif | ||
1188 | + } | ||
1189 | + | ||
1190 | + /* mask unwriteable bits */ | ||
1191 | + val = SET_MASKED(val, 0xe3, s->bChipCmdState); | ||
1192 | + | ||
1193 | + /* Deassert reset pin before next read */ | ||
1194 | + val &= ~CmdReset; | ||
1195 | + | ||
1196 | + s->bChipCmdState = val; | ||
1197 | +} | ||
1198 | + | ||
1199 | +static int rtl8139_RxBufferEmpty(RTL8139State *s) | ||
1200 | +{ | ||
1201 | + int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize); | ||
1202 | + | ||
1203 | + if (unread != 0) | ||
1204 | + { | ||
1205 | +#ifdef DEBUG_RTL8139 | ||
1206 | + printf("RTL8139: receiver buffer data available 0x%04x\n", unread); | ||
1207 | +#endif | ||
1208 | + return 0; | ||
1209 | + } | ||
1210 | + | ||
1211 | +#ifdef DEBUG_RTL8139 | ||
1212 | + printf("RTL8139: receiver buffer is empty\n"); | ||
1213 | +#endif | ||
1214 | + | ||
1215 | + return 1; | ||
1216 | +} | ||
1217 | + | ||
1218 | +static uint32_t rtl8139_ChipCmd_read(RTL8139State *s) | ||
1219 | +{ | ||
1220 | + uint32_t ret = s->bChipCmdState; | ||
1221 | + | ||
1222 | + if (rtl8139_RxBufferEmpty(s)) | ||
1223 | + ret |= RxBufEmpty; | ||
1224 | + | ||
1225 | +#ifdef DEBUG_RTL8139 | ||
1226 | + printf("RTL8139: ChipCmd read val=0x%04x\n", ret); | ||
1227 | +#endif | ||
1228 | + | ||
1229 | + return ret; | ||
1230 | +} | ||
1231 | + | ||
1232 | +static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) | ||
1233 | +{ | ||
1234 | + val &= 0xffff; | ||
1235 | + | ||
1236 | +#ifdef DEBUG_RTL8139 | ||
1237 | + printf("RTL8139C+ command register write(w) val=0x%04x\n", val); | ||
1238 | +#endif | ||
1239 | + | ||
1240 | + /* mask unwriteable bits */ | ||
1241 | + val = SET_MASKED(val, 0xff84, s->CpCmd); | ||
1242 | + | ||
1243 | + s->CpCmd = val; | ||
1244 | +} | ||
1245 | + | ||
1246 | +static uint32_t rtl8139_CpCmd_read(RTL8139State *s) | ||
1247 | +{ | ||
1248 | + uint32_t ret = s->CpCmd; | ||
1249 | + | ||
1250 | +#ifdef DEBUG_RTL8139 | ||
1251 | + printf("RTL8139C+ command register read(w) val=0x%04x\n", ret); | ||
1252 | +#endif | ||
1253 | + | ||
1254 | + return ret; | ||
1255 | +} | ||
1256 | + | ||
1257 | +int rtl8139_config_writeable(RTL8139State *s) | ||
1258 | +{ | ||
1259 | + if (s->Cfg9346 & Cfg9346_Unlock) | ||
1260 | + { | ||
1261 | + return 1; | ||
1262 | + } | ||
1263 | + | ||
1264 | +#ifdef DEBUG_RTL8139 | ||
1265 | + printf("RTL8139: Configuration registers are write-protected\n"); | ||
1266 | +#endif | ||
1267 | + | ||
1268 | + return 0; | ||
1269 | +} | ||
1270 | + | ||
1271 | +static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) | ||
1272 | +{ | ||
1273 | + val &= 0xffff; | ||
1274 | + | ||
1275 | +#ifdef DEBUG_RTL8139 | ||
1276 | + printf("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val); | ||
1277 | +#endif | ||
1278 | + | ||
1279 | + /* mask unwriteable bits */ | ||
1280 | + uint32 mask = 0x4cff; | ||
1281 | + | ||
1282 | + if (1 || !rtl8139_config_writeable(s)) | ||
1283 | + { | ||
1284 | + /* Speed setting and autonegotiation enable bits are read-only */ | ||
1285 | + mask |= 0x3000; | ||
1286 | + /* Duplex mode setting is read-only */ | ||
1287 | + mask |= 0x0100; | ||
1288 | + } | ||
1289 | + | ||
1290 | + val = SET_MASKED(val, mask, s->BasicModeCtrl); | ||
1291 | + | ||
1292 | + s->BasicModeCtrl = val; | ||
1293 | +} | ||
1294 | + | ||
1295 | +static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s) | ||
1296 | +{ | ||
1297 | + uint32_t ret = s->BasicModeCtrl; | ||
1298 | + | ||
1299 | +#ifdef DEBUG_RTL8139 | ||
1300 | + printf("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret); | ||
1301 | +#endif | ||
1302 | + | ||
1303 | + return ret; | ||
1304 | +} | ||
1305 | + | ||
1306 | +static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) | ||
1307 | +{ | ||
1308 | + val &= 0xffff; | ||
1309 | + | ||
1310 | +#ifdef DEBUG_RTL8139 | ||
1311 | + printf("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val); | ||
1312 | +#endif | ||
1313 | + | ||
1314 | + /* mask unwriteable bits */ | ||
1315 | + val = SET_MASKED(val, 0xff3f, s->BasicModeStatus); | ||
1316 | + | ||
1317 | + s->BasicModeStatus = val; | ||
1318 | +} | ||
1319 | + | ||
1320 | +static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s) | ||
1321 | +{ | ||
1322 | + uint32_t ret = s->BasicModeStatus; | ||
1323 | + | ||
1324 | +#ifdef DEBUG_RTL8139 | ||
1325 | + printf("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret); | ||
1326 | +#endif | ||
1327 | + | ||
1328 | + return ret; | ||
1329 | +} | ||
1330 | + | ||
1331 | +static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) | ||
1332 | +{ | ||
1333 | + val &= 0xff; | ||
1334 | + | ||
1335 | +#ifdef DEBUG_RTL8139 | ||
1336 | + printf("RTL8139: Cfg9346 write val=0x%02x\n", val); | ||
1337 | +#endif | ||
1338 | + | ||
1339 | + /* mask unwriteable bits */ | ||
1340 | + val = SET_MASKED(val, 0x31, s->Cfg9346); | ||
1341 | + | ||
1342 | + uint32_t opmode = val & 0xc0; | ||
1343 | + uint32_t eeprom_val = val & 0xf; | ||
1344 | + | ||
1345 | + if (opmode == 0x80) { | ||
1346 | + /* eeprom access */ | ||
1347 | + int eecs = (eeprom_val & 0x08)?1:0; | ||
1348 | + int eesk = (eeprom_val & 0x04)?1:0; | ||
1349 | + int eedi = (eeprom_val & 0x02)?1:0; | ||
1350 | + prom9346_set_wire(s, eecs, eesk, eedi); | ||
1351 | + } else if (opmode == 0x40) { | ||
1352 | + /* Reset. */ | ||
1353 | + val = 0; | ||
1354 | + rtl8139_reset(s); | ||
1355 | + } | ||
1356 | + | ||
1357 | + s->Cfg9346 = val; | ||
1358 | +} | ||
1359 | + | ||
1360 | +static uint32_t rtl8139_Cfg9346_read(RTL8139State *s) | ||
1361 | +{ | ||
1362 | + uint32_t ret = s->Cfg9346; | ||
1363 | + | ||
1364 | + uint32_t opmode = ret & 0xc0; | ||
1365 | + | ||
1366 | + if (opmode == 0x80) | ||
1367 | + { | ||
1368 | + /* eeprom access */ | ||
1369 | + int eedo = prom9346_get_wire(s); | ||
1370 | + if (eedo) | ||
1371 | + { | ||
1372 | + ret |= 0x01; | ||
1373 | + } | ||
1374 | + else | ||
1375 | + { | ||
1376 | + ret &= ~0x01; | ||
1377 | + } | ||
1378 | + } | ||
1379 | + | ||
1380 | +#ifdef DEBUG_RTL8139 | ||
1381 | + printf("RTL8139: Cfg9346 read val=0x%02x\n", ret); | ||
1382 | +#endif | ||
1383 | + | ||
1384 | + return ret; | ||
1385 | +} | ||
1386 | + | ||
1387 | +static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) | ||
1388 | +{ | ||
1389 | + val &= 0xff; | ||
1390 | + | ||
1391 | +#ifdef DEBUG_RTL8139 | ||
1392 | + printf("RTL8139: Config0 write val=0x%02x\n", val); | ||
1393 | +#endif | ||
1394 | + | ||
1395 | + if (!rtl8139_config_writeable(s)) | ||
1396 | + return; | ||
1397 | + | ||
1398 | + /* mask unwriteable bits */ | ||
1399 | + val = SET_MASKED(val, 0xf8, s->Config0); | ||
1400 | + | ||
1401 | + s->Config0 = val; | ||
1402 | +} | ||
1403 | + | ||
1404 | +static uint32_t rtl8139_Config0_read(RTL8139State *s) | ||
1405 | +{ | ||
1406 | + uint32_t ret = s->Config0; | ||
1407 | + | ||
1408 | +#ifdef DEBUG_RTL8139 | ||
1409 | + printf("RTL8139: Config0 read val=0x%02x\n", ret); | ||
1410 | +#endif | ||
1411 | + | ||
1412 | + return ret; | ||
1413 | +} | ||
1414 | + | ||
1415 | +static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) | ||
1416 | +{ | ||
1417 | + val &= 0xff; | ||
1418 | + | ||
1419 | +#ifdef DEBUG_RTL8139 | ||
1420 | + printf("RTL8139: Config1 write val=0x%02x\n", val); | ||
1421 | +#endif | ||
1422 | + | ||
1423 | + if (!rtl8139_config_writeable(s)) | ||
1424 | + return; | ||
1425 | + | ||
1426 | + /* mask unwriteable bits */ | ||
1427 | + val = SET_MASKED(val, 0xC, s->Config1); | ||
1428 | + | ||
1429 | + s->Config1 = val; | ||
1430 | +} | ||
1431 | + | ||
1432 | +static uint32_t rtl8139_Config1_read(RTL8139State *s) | ||
1433 | +{ | ||
1434 | + uint32_t ret = s->Config1; | ||
1435 | + | ||
1436 | +#ifdef DEBUG_RTL8139 | ||
1437 | + printf("RTL8139: Config1 read val=0x%02x\n", ret); | ||
1438 | +#endif | ||
1439 | + | ||
1440 | + return ret; | ||
1441 | +} | ||
1442 | + | ||
1443 | +static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) | ||
1444 | +{ | ||
1445 | + val &= 0xff; | ||
1446 | + | ||
1447 | +#ifdef DEBUG_RTL8139 | ||
1448 | + printf("RTL8139: Config3 write val=0x%02x\n", val); | ||
1449 | +#endif | ||
1450 | + | ||
1451 | + if (!rtl8139_config_writeable(s)) | ||
1452 | + return; | ||
1453 | + | ||
1454 | + /* mask unwriteable bits */ | ||
1455 | + val = SET_MASKED(val, 0x8F, s->Config3); | ||
1456 | + | ||
1457 | + s->Config3 = val; | ||
1458 | +} | ||
1459 | + | ||
1460 | +static uint32_t rtl8139_Config3_read(RTL8139State *s) | ||
1461 | +{ | ||
1462 | + uint32_t ret = s->Config3; | ||
1463 | + | ||
1464 | +#ifdef DEBUG_RTL8139 | ||
1465 | + printf("RTL8139: Config3 read val=0x%02x\n", ret); | ||
1466 | +#endif | ||
1467 | + | ||
1468 | + return ret; | ||
1469 | +} | ||
1470 | + | ||
1471 | +static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) | ||
1472 | +{ | ||
1473 | + val &= 0xff; | ||
1474 | + | ||
1475 | +#ifdef DEBUG_RTL8139 | ||
1476 | + printf("RTL8139: Config4 write val=0x%02x\n", val); | ||
1477 | +#endif | ||
1478 | + | ||
1479 | + if (!rtl8139_config_writeable(s)) | ||
1480 | + return; | ||
1481 | + | ||
1482 | + /* mask unwriteable bits */ | ||
1483 | + val = SET_MASKED(val, 0x0a, s->Config4); | ||
1484 | + | ||
1485 | + s->Config4 = val; | ||
1486 | +} | ||
1487 | + | ||
1488 | +static uint32_t rtl8139_Config4_read(RTL8139State *s) | ||
1489 | +{ | ||
1490 | + uint32_t ret = s->Config4; | ||
1491 | + | ||
1492 | +#ifdef DEBUG_RTL8139 | ||
1493 | + printf("RTL8139: Config4 read val=0x%02x\n", ret); | ||
1494 | +#endif | ||
1495 | + | ||
1496 | + return ret; | ||
1497 | +} | ||
1498 | + | ||
1499 | +static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) | ||
1500 | +{ | ||
1501 | + val &= 0xff; | ||
1502 | + | ||
1503 | +#ifdef DEBUG_RTL8139 | ||
1504 | + printf("RTL8139: Config5 write val=0x%02x\n", val); | ||
1505 | +#endif | ||
1506 | + | ||
1507 | + /* mask unwriteable bits */ | ||
1508 | + val = SET_MASKED(val, 0x80, s->Config5); | ||
1509 | + | ||
1510 | + s->Config5 = val; | ||
1511 | +} | ||
1512 | + | ||
1513 | +static uint32_t rtl8139_Config5_read(RTL8139State *s) | ||
1514 | +{ | ||
1515 | + uint32_t ret = s->Config5; | ||
1516 | + | ||
1517 | +#ifdef DEBUG_RTL8139 | ||
1518 | + printf("RTL8139: Config5 read val=0x%02x\n", ret); | ||
1519 | +#endif | ||
1520 | + | ||
1521 | + return ret; | ||
1522 | +} | ||
1523 | + | ||
1524 | +static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) | ||
1525 | +{ | ||
1526 | + if (!rtl8139_transmitter_enabled(s)) | ||
1527 | + { | ||
1528 | +#ifdef DEBUG_RTL8139 | ||
1529 | + printf("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val); | ||
1530 | +#endif | ||
1531 | + return; | ||
1532 | + } | ||
1533 | + | ||
1534 | +#ifdef DEBUG_RTL8139 | ||
1535 | + printf("RTL8139: TxConfig write val=0x%08x\n", val); | ||
1536 | +#endif | ||
1537 | + | ||
1538 | + val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig); | ||
1539 | + | ||
1540 | + s->TxConfig = val; | ||
1541 | +} | ||
1542 | + | ||
1543 | +static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) | ||
1544 | +{ | ||
1545 | +#ifdef DEBUG_RTL8139 | ||
1546 | + printf("RTL8139C TxConfig via write(b) val=0x%02x\n", val); | ||
1547 | +#endif | ||
1548 | + uint32_t tc = s->TxConfig; | ||
1549 | + tc &= 0xFFFFFF00; | ||
1550 | + tc |= (val & 0x000000FF); | ||
1551 | + rtl8139_TxConfig_write(s, tc); | ||
1552 | +} | ||
1553 | + | ||
1554 | +static uint32_t rtl8139_TxConfig_read(RTL8139State *s) | ||
1555 | +{ | ||
1556 | + uint32_t ret = s->TxConfig; | ||
1557 | + | ||
1558 | +#ifdef DEBUG_RTL8139 | ||
1559 | + printf("RTL8139: TxConfig read val=0x%04x\n", ret); | ||
1560 | +#endif | ||
1561 | + | ||
1562 | + return ret; | ||
1563 | +} | ||
1564 | + | ||
1565 | +static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) | ||
1566 | +{ | ||
1567 | +#ifdef DEBUG_RTL8139 | ||
1568 | + printf("RTL8139: RxConfig write val=0x%08x\n", val); | ||
1569 | +#endif | ||
1570 | + | ||
1571 | + /* mask unwriteable bits */ | ||
1572 | + val = SET_MASKED(val, 0xf0fc0040, s->RxConfig); | ||
1573 | + | ||
1574 | + s->RxConfig = val; | ||
1575 | + | ||
1576 | + /* reset buffer size and read/write pointers */ | ||
1577 | + rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); | ||
1578 | + | ||
1579 | +#ifdef DEBUG_RTL8139 | ||
1580 | + printf("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize); | ||
1581 | +#endif | ||
1582 | +} | ||
1583 | + | ||
1584 | +static uint32_t rtl8139_RxConfig_read(RTL8139State *s) | ||
1585 | +{ | ||
1586 | + uint32_t ret = s->RxConfig; | ||
1587 | + | ||
1588 | +#ifdef DEBUG_RTL8139 | ||
1589 | + printf("RTL8139: RxConfig read val=0x%08x\n", ret); | ||
1590 | +#endif | ||
1591 | + | ||
1592 | + return ret; | ||
1593 | +} | ||
1594 | + | ||
1595 | +static int rtl8139_transmit_one(RTL8139State *s, int descriptor) | ||
1596 | +{ | ||
1597 | + if (!rtl8139_transmitter_enabled(s)) | ||
1598 | + { | ||
1599 | +#ifdef DEBUG_RTL8139 | ||
1600 | + printf("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n", descriptor); | ||
1601 | +#endif | ||
1602 | + return 0; | ||
1603 | + } | ||
1604 | + | ||
1605 | + if (s->TxStatus[descriptor] & TxHostOwns) | ||
1606 | + { | ||
1607 | +#ifdef DEBUG_RTL8139 | ||
1608 | + printf("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n", descriptor, s->TxStatus[descriptor]); | ||
1609 | +#endif | ||
1610 | + return 0; | ||
1611 | + } | ||
1612 | + | ||
1613 | +#ifdef DEBUG_RTL8139 | ||
1614 | + printf("RTL8139: +++ transmitting from descriptor %d\n", descriptor); | ||
1615 | +#endif | ||
1616 | + | ||
1617 | + int txsize = s->TxStatus[descriptor] & 0x1fff; | ||
1618 | + uint8_t txbuffer[0x2000]; | ||
1619 | + | ||
1620 | +#ifdef DEBUG_RTL8139 | ||
1621 | + printf("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n", txsize, s->TxAddr[descriptor]); | ||
1622 | +#endif | ||
1623 | + cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize); | ||
1624 | + | ||
1625 | + qemu_send_packet(s->vc, txbuffer, txsize); | ||
1626 | + | ||
1627 | + /* Mark descriptor as transferred */ | ||
1628 | + s->TxStatus[descriptor] |= TxHostOwns; | ||
1629 | + s->TxStatus[descriptor] |= TxStatOK; | ||
1630 | + | ||
1631 | +#ifdef DEBUG_RTL8139 | ||
1632 | + printf("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor); | ||
1633 | +#endif | ||
1634 | + | ||
1635 | + /* update interrupt */ | ||
1636 | + s->IntrStatus |= TxOK; | ||
1637 | + rtl8139_update_irq(s); | ||
1638 | + | ||
1639 | + return 1; | ||
1640 | +} | ||
1641 | + | ||
1642 | +static int rtl8139_cplus_transmit_one(RTL8139State *s) | ||
1643 | +{ | ||
1644 | + if (!rtl8139_transmitter_enabled(s)) | ||
1645 | + { | ||
1646 | +#ifdef DEBUG_RTL8139 | ||
1647 | + printf("RTL8139: +++ C+ mode: transmitter disabled\n"); | ||
1648 | +#endif | ||
1649 | + return 0; | ||
1650 | + } | ||
1651 | + | ||
1652 | + if (!rtl8139_cp_transmitter_enabled(s)) | ||
1653 | + { | ||
1654 | +#ifdef DEBUG_RTL8139 | ||
1655 | + printf("RTL8139: +++ C+ mode: C+ transmitter disabled\n"); | ||
1656 | +#endif | ||
1657 | + return 0 ; | ||
1658 | + } | ||
1659 | + | ||
1660 | + int descriptor = s->currCPlusTxDesc; | ||
1661 | + | ||
1662 | + target_phys_addr_t cplus_tx_ring_desc = | ||
1663 | + rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); | ||
1664 | + | ||
1665 | + /* Normal priority ring */ | ||
1666 | + cplus_tx_ring_desc += 16 * descriptor; | ||
1667 | + | ||
1668 | +#ifdef DEBUG_RTL8139 | ||
1669 | + printf("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n", | ||
1670 | + descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc); | ||
1671 | +#endif | ||
1672 | + | ||
1673 | + uint32_t val, txdw0,txdw1,txbufLO,txbufHI; | ||
1674 | + | ||
1675 | + cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4); | ||
1676 | + txdw0 = le32_to_cpu(val); | ||
1677 | + cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4); | ||
1678 | + txdw1 = le32_to_cpu(val); | ||
1679 | + cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4); | ||
1680 | + txbufLO = le32_to_cpu(val); | ||
1681 | + cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4); | ||
1682 | + txbufHI = le32_to_cpu(val); | ||
1683 | + | ||
1684 | +#ifdef DEBUG_RTL8139 | ||
1685 | + printf("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", | ||
1686 | + descriptor, | ||
1687 | + txdw0, txdw1, txbufLO, txbufHI); | ||
1688 | +#endif | ||
1689 | + | ||
1690 | +/* w0 ownership flag */ | ||
1691 | +#define CP_TX_OWN (1<<31) | ||
1692 | +/* w0 end of ring flag */ | ||
1693 | +#define CP_TX_EOR (1<<30) | ||
1694 | +/* first segment of received packet flag */ | ||
1695 | +#define CP_TX_FS (1<<29) | ||
1696 | +/* last segment of received packet flag */ | ||
1697 | +#define CP_TX_LS (1<<28) | ||
1698 | +/* large send packet flag */ | ||
1699 | +#define CP_TX_LGSEN (1<<27) | ||
1700 | +/* IP checksum offload flag */ | ||
1701 | +#define CP_TX_IPCS (1<<18) | ||
1702 | +/* UDP checksum offload flag */ | ||
1703 | +#define CP_TX_UDPCS (1<<17) | ||
1704 | +/* TCP checksum offload flag */ | ||
1705 | +#define CP_TX_TCPCS (1<<16) | ||
1706 | + | ||
1707 | +/* w0 bits 0...15 : buffer size */ | ||
1708 | +#define CP_TX_BUFFER_SIZE (1<<16) | ||
1709 | +#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) | ||
1710 | +/* w1 tag available flag */ | ||
1711 | +#define CP_RX_TAGC (1<<17) | ||
1712 | +/* w1 bits 0...15 : VLAN tag */ | ||
1713 | +#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) | ||
1714 | +/* w2 low 32bit of Rx buffer ptr */ | ||
1715 | +/* w3 high 32bit of Rx buffer ptr */ | ||
1716 | + | ||
1717 | +/* set after transmission */ | ||
1718 | +/* FIFO underrun flag */ | ||
1719 | +#define CP_TX_STATUS_UNF (1<<25) | ||
1720 | +/* transmit error summary flag, valid if set any of three below */ | ||
1721 | +#define CP_TX_STATUS_TES (1<<23) | ||
1722 | +/* out-of-window collision flag */ | ||
1723 | +#define CP_TX_STATUS_OWC (1<<22) | ||
1724 | +/* link failure flag */ | ||
1725 | +#define CP_TX_STATUS_LNKF (1<<21) | ||
1726 | +/* excessive collisions flag */ | ||
1727 | +#define CP_TX_STATUS_EXC (1<<20) | ||
1728 | + | ||
1729 | + if (!(txdw0 & CP_TX_OWN)) | ||
1730 | + { | ||
1731 | +#if defined(DEBUG_RTL8139) | ||
1732 | + printf("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor); | ||
1733 | +#endif | ||
1734 | + return 0 ; | ||
1735 | + } | ||
1736 | + | ||
1737 | +#ifdef DEBUG_RTL8139 | ||
1738 | + printf("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor); | ||
1739 | +#endif | ||
1740 | + | ||
1741 | + int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; | ||
1742 | + target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); | ||
1743 | + | ||
1744 | + uint8_t txbuffer[CP_TX_BUFFER_SIZE]; | ||
1745 | + | ||
1746 | +#ifdef DEBUG_RTL8139 | ||
1747 | + printf("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at 0x%08x\n", txsize, tx_addr); | ||
1748 | +#endif | ||
1749 | + cpu_physical_memory_read(tx_addr, txbuffer, txsize); | ||
1750 | + | ||
1751 | + /* transmit the packet */ | ||
1752 | + qemu_send_packet(s->vc, txbuffer, txsize); | ||
1753 | + | ||
1754 | + /* transfer ownership to target */ | ||
1755 | + txdw0 &= ~CP_RX_OWN; | ||
1756 | + | ||
1757 | + /* reset error indicator bits */ | ||
1758 | + txdw0 &= ~CP_TX_STATUS_UNF; | ||
1759 | + txdw0 &= ~CP_TX_STATUS_TES; | ||
1760 | + txdw0 &= ~CP_TX_STATUS_OWC; | ||
1761 | + txdw0 &= ~CP_TX_STATUS_LNKF; | ||
1762 | + txdw0 &= ~CP_TX_STATUS_EXC; | ||
1763 | + | ||
1764 | + /* update ring data */ | ||
1765 | + val = cpu_to_le32(txdw0); | ||
1766 | + cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4); | ||
1767 | +// val = cpu_to_le32(txdw1); | ||
1768 | +// cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4); | ||
1769 | + | ||
1770 | + /* seek to next Rx descriptor */ | ||
1771 | + if (txdw0 & CP_TX_EOR) | ||
1772 | + { | ||
1773 | + s->currCPlusTxDesc = 0; | ||
1774 | + } | ||
1775 | + else | ||
1776 | + { | ||
1777 | + ++s->currCPlusTxDesc; | ||
1778 | + } | ||
1779 | + | ||
1780 | +#ifdef DEBUG_RTL8139 | ||
1781 | + printf("RTL8139: +++ C+ mode transmitted %d bytes from descriptor %d\n", txsize, descriptor); | ||
1782 | +#endif | ||
1783 | + return 1; | ||
1784 | +} | ||
1785 | + | ||
1786 | +static void rtl8139_cplus_transmit(RTL8139State *s) | ||
1787 | +{ | ||
1788 | + int txcount = 0; | ||
1789 | + | ||
1790 | + while (rtl8139_cplus_transmit_one(s)) | ||
1791 | + { | ||
1792 | + ++txcount; | ||
1793 | + } | ||
1794 | + | ||
1795 | + /* Mark transfer completed */ | ||
1796 | + if (!txcount) | ||
1797 | + { | ||
1798 | +#ifdef DEBUG_RTL8139 | ||
1799 | + printf("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n", s->currCPlusTxDesc); | ||
1800 | +#endif | ||
1801 | + } | ||
1802 | + else | ||
1803 | + { | ||
1804 | + /* update interrupt status */ | ||
1805 | + s->IntrStatus |= TxOK; | ||
1806 | + rtl8139_update_irq(s); | ||
1807 | + } | ||
1808 | +} | ||
1809 | + | ||
1810 | +static void rtl8139_transmit(RTL8139State *s) | ||
1811 | +{ | ||
1812 | + int descriptor = s->currTxDesc, txcount = 0; | ||
1813 | + | ||
1814 | + /*while*/ | ||
1815 | + if (rtl8139_transmit_one(s, descriptor)) | ||
1816 | + { | ||
1817 | + ++s->currTxDesc; | ||
1818 | + s->currTxDesc %= 4; | ||
1819 | + ++txcount; | ||
1820 | + } | ||
1821 | + | ||
1822 | + /* Mark transfer completed */ | ||
1823 | + if (!txcount) | ||
1824 | + { | ||
1825 | +#ifdef DEBUG_RTL8139 | ||
1826 | + printf("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc); | ||
1827 | +#endif | ||
1828 | + } | ||
1829 | +} | ||
1830 | + | ||
1831 | +static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) | ||
1832 | +{ | ||
1833 | + | ||
1834 | + int descriptor = txRegOffset/4; | ||
1835 | +#ifdef DEBUG_RTL8139 | ||
1836 | + printf("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor); | ||
1837 | +#endif | ||
1838 | + | ||
1839 | + /* mask only reserved bits */ | ||
1840 | + val &= ~0xff00c000; /* these bits are reset on write */ | ||
1841 | + val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]); | ||
1842 | + | ||
1843 | + s->TxStatus[descriptor] = val; | ||
1844 | + | ||
1845 | + /* attempt to start transmission */ | ||
1846 | + rtl8139_transmit(s); | ||
1847 | +} | ||
1848 | + | ||
1849 | +static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset) | ||
1850 | +{ | ||
1851 | + uint32_t ret = s->TxStatus[txRegOffset/4]; | ||
1852 | + | ||
1853 | +#ifdef DEBUG_RTL8139 | ||
1854 | + printf("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret); | ||
1855 | +#endif | ||
1856 | + | ||
1857 | + return ret; | ||
1858 | +} | ||
1859 | + | ||
1860 | +static uint16_t rtl8139_TSAD_read(RTL8139State *s) | ||
1861 | +{ | ||
1862 | + uint16_t ret = 0; | ||
1863 | + | ||
1864 | + /* Simulate TSAD, it is read only anyway */ | ||
1865 | + | ||
1866 | + ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) | ||
1867 | + |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) | ||
1868 | + |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) | ||
1869 | + |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) | ||
1870 | + | ||
1871 | + |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) | ||
1872 | + |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) | ||
1873 | + |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) | ||
1874 | + |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) | ||
1875 | + | ||
1876 | + |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) | ||
1877 | + |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) | ||
1878 | + |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) | ||
1879 | + |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) | ||
1880 | + | ||
1881 | + |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) | ||
1882 | + |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) | ||
1883 | + |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) | ||
1884 | + |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; | ||
1885 | + | ||
1886 | + | ||
1887 | +#ifdef DEBUG_RTL8139 | ||
1888 | + printf("RTL8139: TSAD read val=0x%04x\n", ret); | ||
1889 | +#endif | ||
1890 | + | ||
1891 | + return ret; | ||
1892 | +} | ||
1893 | + | ||
1894 | +static uint16_t rtl8139_CSCR_read(RTL8139State *s) | ||
1895 | +{ | ||
1896 | + uint16_t ret = s->CSCR; | ||
1897 | + | ||
1898 | +#ifdef DEBUG_RTL8139 | ||
1899 | + printf("RTL8139: CSCR read val=0x%04x\n", ret); | ||
1900 | +#endif | ||
1901 | + | ||
1902 | + return ret; | ||
1903 | +} | ||
1904 | + | ||
1905 | +static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) | ||
1906 | +{ | ||
1907 | +#ifdef DEBUG_RTL8139 | ||
1908 | + printf("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val); | ||
1909 | +#endif | ||
1910 | + | ||
1911 | + s->TxAddr[txAddrOffset/4] = le32_to_cpu(val); | ||
1912 | +} | ||
1913 | + | ||
1914 | +static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset) | ||
1915 | +{ | ||
1916 | + uint32_t ret = cpu_to_le32(s->TxAddr[txAddrOffset/4]); | ||
1917 | + | ||
1918 | +#ifdef DEBUG_RTL8139 | ||
1919 | + printf("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret); | ||
1920 | +#endif | ||
1921 | + | ||
1922 | + return ret; | ||
1923 | +} | ||
1924 | + | ||
1925 | +static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) | ||
1926 | +{ | ||
1927 | +#ifdef DEBUG_RTL8139 | ||
1928 | + printf("RTL8139: RxBufPtr write val=0x%04x\n", val); | ||
1929 | +#endif | ||
1930 | + | ||
1931 | + /* this value is off by 16 */ | ||
1932 | + s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize); | ||
1933 | + | ||
1934 | +#if defined(DEBUG_RTL8139) | ||
1935 | + printf(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n", | ||
1936 | + s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); | ||
1937 | +#endif | ||
1938 | +} | ||
1939 | + | ||
1940 | +static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s) | ||
1941 | +{ | ||
1942 | + /* this value is off by 16 */ | ||
1943 | + uint32_t ret = s->RxBufPtr - 0x10; | ||
1944 | + | ||
1945 | +#ifdef DEBUG_RTL8139 | ||
1946 | + printf("RTL8139: RxBufPtr read val=0x%04x\n", ret); | ||
1947 | +#endif | ||
1948 | + | ||
1949 | + return ret; | ||
1950 | +} | ||
1951 | + | ||
1952 | +static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) | ||
1953 | +{ | ||
1954 | +#ifdef DEBUG_RTL8139 | ||
1955 | + printf("RTL8139: RxBuf write val=0x%08x\n", val); | ||
1956 | +#endif | ||
1957 | + | ||
1958 | + s->RxBuf = val; | ||
1959 | + | ||
1960 | + /* may need to reset rxring here */ | ||
1961 | +} | ||
1962 | + | ||
1963 | +static uint32_t rtl8139_RxBuf_read(RTL8139State *s) | ||
1964 | +{ | ||
1965 | + uint32_t ret = s->RxBuf; | ||
1966 | + | ||
1967 | +#ifdef DEBUG_RTL8139 | ||
1968 | + printf("RTL8139: RxBuf read val=0x%08x\n", ret); | ||
1969 | +#endif | ||
1970 | + | ||
1971 | + return ret; | ||
1972 | +} | ||
1973 | + | ||
1974 | +static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) | ||
1975 | +{ | ||
1976 | +#ifdef DEBUG_RTL8139 | ||
1977 | + printf("RTL8139: IntrMask write(w) val=0x%04x\n", val); | ||
1978 | +#endif | ||
1979 | + | ||
1980 | + /* mask unwriteable bits */ | ||
1981 | + val = SET_MASKED(val, 0x1e00, s->IntrMask); | ||
1982 | + | ||
1983 | + s->IntrMask = val; | ||
1984 | + | ||
1985 | + rtl8139_update_irq(s); | ||
1986 | +} | ||
1987 | + | ||
1988 | +static uint32_t rtl8139_IntrMask_read(RTL8139State *s) | ||
1989 | +{ | ||
1990 | + uint32_t ret = s->IntrMask; | ||
1991 | + | ||
1992 | +#ifdef DEBUG_RTL8139 | ||
1993 | + printf("RTL8139: IntrMask read(w) val=0x%04x\n", ret); | ||
1994 | +#endif | ||
1995 | + | ||
1996 | + return ret; | ||
1997 | +} | ||
1998 | + | ||
1999 | +static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) | ||
2000 | +{ | ||
2001 | +#ifdef DEBUG_RTL8139 | ||
2002 | + printf("RTL8139: IntrStatus write(w) val=0x%04x\n", val); | ||
2003 | +#endif | ||
2004 | + | ||
2005 | +#if 0 | ||
2006 | + | ||
2007 | + /* writing to ISR has no effect */ | ||
2008 | + | ||
2009 | + return; | ||
2010 | + | ||
2011 | +#else | ||
2012 | + uint16_t newStatus = s->IntrStatus & ~val; | ||
2013 | + | ||
2014 | + /* mask unwriteable bits */ | ||
2015 | + newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus); | ||
2016 | + | ||
2017 | + /* writing 1 to interrupt status register bit clears it */ | ||
2018 | + s->IntrStatus = 0; | ||
2019 | + rtl8139_update_irq(s); | ||
2020 | + | ||
2021 | + s->IntrStatus = newStatus; | ||
2022 | + rtl8139_update_irq(s); | ||
2023 | +#endif | ||
2024 | +} | ||
2025 | + | ||
2026 | +static uint32_t rtl8139_IntrStatus_read(RTL8139State *s) | ||
2027 | +{ | ||
2028 | + uint32_t ret = s->IntrStatus; | ||
2029 | + | ||
2030 | +#ifdef DEBUG_RTL8139 | ||
2031 | + printf("RTL8139: IntrStatus read(w) val=0x%04x\n", ret); | ||
2032 | +#endif | ||
2033 | + | ||
2034 | +#if 0 | ||
2035 | + | ||
2036 | + /* reading ISR clears all interrupts */ | ||
2037 | + s->IntrStatus = 0; | ||
2038 | + | ||
2039 | + rtl8139_update_irq(s); | ||
2040 | + | ||
2041 | +#endif | ||
2042 | + | ||
2043 | + return ret; | ||
2044 | +} | ||
2045 | + | ||
2046 | +static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) | ||
2047 | +{ | ||
2048 | +#ifdef DEBUG_RTL8139 | ||
2049 | + printf("RTL8139: MultiIntr write(w) val=0x%04x\n", val); | ||
2050 | +#endif | ||
2051 | + | ||
2052 | + /* mask unwriteable bits */ | ||
2053 | + val = SET_MASKED(val, 0xf000, s->MultiIntr); | ||
2054 | + | ||
2055 | + s->MultiIntr = val; | ||
2056 | +} | ||
2057 | + | ||
2058 | +static uint32_t rtl8139_MultiIntr_read(RTL8139State *s) | ||
2059 | +{ | ||
2060 | + uint32_t ret = s->MultiIntr; | ||
2061 | + | ||
2062 | +#ifdef DEBUG_RTL8139 | ||
2063 | + printf("RTL8139: MultiIntr read(w) val=0x%04x\n", ret); | ||
2064 | +#endif | ||
2065 | + | ||
2066 | + return ret; | ||
2067 | +} | ||
2068 | + | ||
2069 | +static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) | ||
2070 | +{ | ||
2071 | + RTL8139State *s = opaque; | ||
2072 | + | ||
2073 | + addr &= 0xff; | ||
2074 | + | ||
2075 | + switch (addr) | ||
2076 | + { | ||
2077 | + case MAC0 ... MAC0+5: | ||
2078 | + s->phys[addr - MAC0] = val; | ||
2079 | + break; | ||
2080 | + case MAC0+6 ... MAC0+7: | ||
2081 | + /* reserved */ | ||
2082 | + break; | ||
2083 | + case MAR0 ... MAR0+7: | ||
2084 | + s->mult[addr - MAR0] = val; | ||
2085 | + break; | ||
2086 | + case ChipCmd: | ||
2087 | + rtl8139_ChipCmd_write(s, val); | ||
2088 | + break; | ||
2089 | + case Cfg9346: | ||
2090 | + rtl8139_Cfg9346_write(s, val); | ||
2091 | + break; | ||
2092 | + case TxConfig: /* windows driver sometimes writes using byte-lenth call */ | ||
2093 | + rtl8139_TxConfig_writeb(s, val); | ||
2094 | + break; | ||
2095 | + case Config0: | ||
2096 | + rtl8139_Config0_write(s, val); | ||
2097 | + break; | ||
2098 | + case Config1: | ||
2099 | + rtl8139_Config1_write(s, val); | ||
2100 | + break; | ||
2101 | + case Config3: | ||
2102 | + rtl8139_Config3_write(s, val); | ||
2103 | + break; | ||
2104 | + case Config4: | ||
2105 | + rtl8139_Config4_write(s, val); | ||
2106 | + break; | ||
2107 | + case Config5: | ||
2108 | + rtl8139_Config5_write(s, val); | ||
2109 | + break; | ||
2110 | + case MediaStatus: | ||
2111 | + /* ignore */ | ||
2112 | +#ifdef DEBUG_RTL8139 | ||
2113 | + printf("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val); | ||
2114 | +#endif | ||
2115 | + break; | ||
2116 | + | ||
2117 | + case HltClk: | ||
2118 | +#ifdef DEBUG_RTL8139 | ||
2119 | + printf("RTL8139: HltClk write val=0x%08x\n", val); | ||
2120 | +#endif | ||
2121 | + if (val == 'R') | ||
2122 | + { | ||
2123 | + s->clock_enabled = 1; | ||
2124 | + } | ||
2125 | + else if (val == 'H') | ||
2126 | + { | ||
2127 | + s->clock_enabled = 0; | ||
2128 | + } | ||
2129 | + break; | ||
2130 | + | ||
2131 | + case TxThresh: | ||
2132 | +#ifdef DEBUG_RTL8139 | ||
2133 | + printf("RTL8139C+ TxThresh write(b) val=0x%02x\n", val); | ||
2134 | +#endif | ||
2135 | + s->TxThresh = val; | ||
2136 | + break; | ||
2137 | + | ||
2138 | + case TxPoll: | ||
2139 | +#ifdef DEBUG_RTL8139 | ||
2140 | + printf("RTL8139C+ TxPoll write(b) val=0x%02x\n", val); | ||
2141 | +#endif | ||
2142 | + if (val & (1 << 7)) | ||
2143 | + { | ||
2144 | +#ifdef DEBUG_RTL8139 | ||
2145 | + printf("RTL8139C+ TxPoll high priority transmission (not implemented)\n"); | ||
2146 | +#endif | ||
2147 | + //rtl8139_cplus_transmit(s); | ||
2148 | + } | ||
2149 | + if (val & (1 << 6)) | ||
2150 | + { | ||
2151 | +#ifdef DEBUG_RTL8139 | ||
2152 | + printf("RTL8139C+ TxPoll normal priority transmission\n"); | ||
2153 | +#endif | ||
2154 | + rtl8139_cplus_transmit(s); | ||
2155 | + } | ||
2156 | + | ||
2157 | + break; | ||
2158 | + | ||
2159 | + default: | ||
2160 | +#ifdef DEBUG_RTL8139 | ||
2161 | + printf("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val); | ||
2162 | +#endif | ||
2163 | + break; | ||
2164 | + } | ||
2165 | +} | ||
2166 | + | ||
2167 | +static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) | ||
2168 | +{ | ||
2169 | + RTL8139State *s = opaque; | ||
2170 | + | ||
2171 | + addr &= 0xfe; | ||
2172 | + | ||
2173 | + switch (addr) | ||
2174 | + { | ||
2175 | + case IntrMask: | ||
2176 | + rtl8139_IntrMask_write(s, val); | ||
2177 | + break; | ||
2178 | + | ||
2179 | + case IntrStatus: | ||
2180 | + rtl8139_IntrStatus_write(s, val); | ||
2181 | + break; | ||
2182 | + | ||
2183 | + case MultiIntr: | ||
2184 | + rtl8139_MultiIntr_write(s, val); | ||
2185 | + break; | ||
2186 | + | ||
2187 | + case RxBufPtr: | ||
2188 | + rtl8139_RxBufPtr_write(s, val); | ||
2189 | + break; | ||
2190 | + | ||
2191 | + case BasicModeCtrl: | ||
2192 | + rtl8139_BasicModeCtrl_write(s, val); | ||
2193 | + break; | ||
2194 | + case BasicModeStatus: | ||
2195 | + rtl8139_BasicModeStatus_write(s, val); | ||
2196 | + break; | ||
2197 | + case NWayAdvert: | ||
2198 | +#ifdef DEBUG_RTL8139 | ||
2199 | + printf("RTL8139: NWayAdvert write(w) val=0x%04x\n", val); | ||
2200 | +#endif | ||
2201 | + s->NWayAdvert = val; | ||
2202 | + break; | ||
2203 | + case NWayLPAR: | ||
2204 | +#ifdef DEBUG_RTL8139 | ||
2205 | + printf("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val); | ||
2206 | +#endif | ||
2207 | + break; | ||
2208 | + case NWayExpansion: | ||
2209 | +#ifdef DEBUG_RTL8139 | ||
2210 | + printf("RTL8139: NWayExpansion write(w) val=0x%04x\n", val); | ||
2211 | +#endif | ||
2212 | + s->NWayExpansion = val; | ||
2213 | + break; | ||
2214 | + | ||
2215 | + case CpCmd: | ||
2216 | + rtl8139_CpCmd_write(s, val); | ||
2217 | + break; | ||
2218 | + | ||
2219 | + default: | ||
2220 | +#ifdef DEBUG_RTL8139 | ||
2221 | + printf("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val); | ||
2222 | +#endif | ||
2223 | + | ||
2224 | +#ifdef TARGET_WORDS_BIGENDIAN | ||
2225 | + rtl8139_io_writeb(opaque, addr, (val >> 8) & 0xff); | ||
2226 | + rtl8139_io_writeb(opaque, addr + 1, val & 0xff); | ||
2227 | +#else | ||
2228 | + rtl8139_io_writeb(opaque, addr, val & 0xff); | ||
2229 | + rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); | ||
2230 | +#endif | ||
2231 | + break; | ||
2232 | + } | ||
2233 | +} | ||
2234 | + | ||
2235 | +static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) | ||
2236 | +{ | ||
2237 | + RTL8139State *s = opaque; | ||
2238 | + | ||
2239 | + addr &= 0xfc; | ||
2240 | + | ||
2241 | + switch (addr) | ||
2242 | + { | ||
2243 | + case RxMissed: | ||
2244 | +#ifdef DEBUG_RTL8139 | ||
2245 | + printf("RTL8139: RxMissed clearing on write\n"); | ||
2246 | +#endif | ||
2247 | + s->RxMissed = 0; | ||
2248 | + break; | ||
2249 | + | ||
2250 | + case TxConfig: | ||
2251 | + rtl8139_TxConfig_write(s, val); | ||
2252 | + break; | ||
2253 | + | ||
2254 | + case RxConfig: | ||
2255 | + rtl8139_RxConfig_write(s, val); | ||
2256 | + break; | ||
2257 | + | ||
2258 | + case TxStatus0 ... TxStatus0+4*4-1: | ||
2259 | + rtl8139_TxStatus_write(s, addr-TxStatus0, val); | ||
2260 | + break; | ||
2261 | + | ||
2262 | + case TxAddr0 ... TxAddr0+4*4-1: | ||
2263 | + rtl8139_TxAddr_write(s, addr-TxAddr0, val); | ||
2264 | + break; | ||
2265 | + | ||
2266 | + case RxBuf: | ||
2267 | + rtl8139_RxBuf_write(s, val); | ||
2268 | + break; | ||
2269 | + | ||
2270 | + case RxRingAddrLO: | ||
2271 | +#ifdef DEBUG_RTL8139 | ||
2272 | + printf("RTL8139: C+ RxRing low bits write val=0x%08x\n", val); | ||
2273 | +#endif | ||
2274 | + s->RxRingAddrLO = val; | ||
2275 | + break; | ||
2276 | + | ||
2277 | + case RxRingAddrHI: | ||
2278 | +#ifdef DEBUG_RTL8139 | ||
2279 | + printf("RTL8139: C+ RxRing high bits write val=0x%08x\n", val); | ||
2280 | +#endif | ||
2281 | + s->RxRingAddrHI = val; | ||
2282 | + break; | ||
2283 | + | ||
2284 | + default: | ||
2285 | +#ifdef DEBUG_RTL8139 | ||
2286 | + printf("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val); | ||
2287 | +#endif | ||
2288 | +#ifdef TARGET_WORDS_BIGENDIAN | ||
2289 | + rtl8139_io_writeb(opaque, addr, (val >> 24) & 0xff); | ||
2290 | + rtl8139_io_writeb(opaque, addr + 1, (val >> 16) & 0xff); | ||
2291 | + rtl8139_io_writeb(opaque, addr + 2, (val >> 8) & 0xff); | ||
2292 | + rtl8139_io_writeb(opaque, addr + 3, val & 0xff); | ||
2293 | +#else | ||
2294 | + rtl8139_io_writeb(opaque, addr, val & 0xff); | ||
2295 | + rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); | ||
2296 | + rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); | ||
2297 | + rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); | ||
2298 | +#endif | ||
2299 | + break; | ||
2300 | + } | ||
2301 | +} | ||
2302 | + | ||
2303 | +static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) | ||
2304 | +{ | ||
2305 | + RTL8139State *s = opaque; | ||
2306 | + int ret; | ||
2307 | + | ||
2308 | + addr &= 0xff; | ||
2309 | + | ||
2310 | + switch (addr) | ||
2311 | + { | ||
2312 | + case MAC0 ... MAC0+5: | ||
2313 | + ret = s->phys[addr - MAC0]; | ||
2314 | + break; | ||
2315 | + case MAC0+6 ... MAC0+7: | ||
2316 | + ret = 0; | ||
2317 | + break; | ||
2318 | + case MAR0 ... MAR0+7: | ||
2319 | + ret = s->mult[addr - MAR0]; | ||
2320 | + break; | ||
2321 | + case ChipCmd: | ||
2322 | + ret = rtl8139_ChipCmd_read(s); | ||
2323 | + break; | ||
2324 | + case Cfg9346: | ||
2325 | + ret = rtl8139_Cfg9346_read(s); | ||
2326 | + break; | ||
2327 | + case Config0: | ||
2328 | + ret = rtl8139_Config0_read(s); | ||
2329 | + break; | ||
2330 | + case Config1: | ||
2331 | + ret = rtl8139_Config1_read(s); | ||
2332 | + break; | ||
2333 | + case Config3: | ||
2334 | + ret = rtl8139_Config3_read(s); | ||
2335 | + break; | ||
2336 | + case Config4: | ||
2337 | + ret = rtl8139_Config4_read(s); | ||
2338 | + break; | ||
2339 | + case Config5: | ||
2340 | + ret = rtl8139_Config5_read(s); | ||
2341 | + break; | ||
2342 | + | ||
2343 | + case MediaStatus: | ||
2344 | + ret = 0xd0; | ||
2345 | +#ifdef DEBUG_RTL8139 | ||
2346 | + printf("RTL8139: MediaStatus read 0x%x\n", ret); | ||
2347 | +#endif | ||
2348 | + break; | ||
2349 | + | ||
2350 | + case HltClk: | ||
2351 | + ret = s->clock_enabled; | ||
2352 | +#ifdef DEBUG_RTL8139 | ||
2353 | + printf("RTL8139: HltClk read 0x%x\n", ret); | ||
2354 | +#endif | ||
2355 | + break; | ||
2356 | + | ||
2357 | + case PCIRevisionID: | ||
2358 | + ret = 0x10; | ||
2359 | +#ifdef DEBUG_RTL8139 | ||
2360 | + printf("RTL8139: PCI Revision ID read 0x%x\n", ret); | ||
2361 | +#endif | ||
2362 | + break; | ||
2363 | + | ||
2364 | + case TxThresh: | ||
2365 | + ret = s->TxThresh; | ||
2366 | +#ifdef DEBUG_RTL8139 | ||
2367 | + printf("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret); | ||
2368 | +#endif | ||
2369 | + break; | ||
2370 | + | ||
2371 | + case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ | ||
2372 | + ret = s->TxConfig >> 24; | ||
2373 | +#ifdef DEBUG_RTL8139 | ||
2374 | + printf("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret); | ||
2375 | +#endif | ||
2376 | + break; | ||
2377 | + | ||
2378 | + default: | ||
2379 | +#ifdef DEBUG_RTL8139 | ||
2380 | + printf("RTL8139: not implemented read(b) addr=0x%x\n", addr); | ||
2381 | +#endif | ||
2382 | + ret = 0; | ||
2383 | + break; | ||
2384 | + } | ||
2385 | + | ||
2386 | + return ret; | ||
2387 | +} | ||
2388 | + | ||
2389 | +static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) | ||
2390 | +{ | ||
2391 | + RTL8139State *s = opaque; | ||
2392 | + uint32_t ret; | ||
2393 | + | ||
2394 | + addr &= 0xfe; /* mask lower bit */ | ||
2395 | + | ||
2396 | + switch (addr) | ||
2397 | + { | ||
2398 | + case IntrMask: | ||
2399 | + ret = rtl8139_IntrMask_read(s); | ||
2400 | + break; | ||
2401 | + | ||
2402 | + case IntrStatus: | ||
2403 | + ret = rtl8139_IntrStatus_read(s); | ||
2404 | + break; | ||
2405 | + | ||
2406 | + case MultiIntr: | ||
2407 | + ret = rtl8139_MultiIntr_read(s); | ||
2408 | + break; | ||
2409 | + | ||
2410 | + case RxBufPtr: | ||
2411 | + ret = rtl8139_RxBufPtr_read(s); | ||
2412 | + break; | ||
2413 | + | ||
2414 | + case BasicModeCtrl: | ||
2415 | + ret = rtl8139_BasicModeCtrl_read(s); | ||
2416 | + break; | ||
2417 | + case BasicModeStatus: | ||
2418 | + ret = rtl8139_BasicModeStatus_read(s); | ||
2419 | + break; | ||
2420 | + case NWayAdvert: | ||
2421 | + ret = s->NWayAdvert; | ||
2422 | +#ifdef DEBUG_RTL8139 | ||
2423 | + printf("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret); | ||
2424 | +#endif | ||
2425 | + break; | ||
2426 | + case NWayLPAR: | ||
2427 | + ret = s->NWayLPAR; | ||
2428 | +#ifdef DEBUG_RTL8139 | ||
2429 | + printf("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret); | ||
2430 | +#endif | ||
2431 | + break; | ||
2432 | + case NWayExpansion: | ||
2433 | + ret = s->NWayExpansion; | ||
2434 | +#ifdef DEBUG_RTL8139 | ||
2435 | + printf("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret); | ||
2436 | +#endif | ||
2437 | + break; | ||
2438 | + | ||
2439 | + case CpCmd: | ||
2440 | + ret = rtl8139_CpCmd_read(s); | ||
2441 | + break; | ||
2442 | + | ||
2443 | + case TxSummary: | ||
2444 | + ret = rtl8139_TSAD_read(s); | ||
2445 | + break; | ||
2446 | + | ||
2447 | + case CSCR: | ||
2448 | + ret = rtl8139_CSCR_read(s); | ||
2449 | + break; | ||
2450 | + | ||
2451 | + default: | ||
2452 | +#ifdef DEBUG_RTL8139 | ||
2453 | + printf("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr); | ||
2454 | +#endif | ||
2455 | + | ||
2456 | +#ifdef TARGET_WORDS_BIGENDIAN | ||
2457 | + ret = rtl8139_io_readb(opaque, addr) << 8; | ||
2458 | + ret |= rtl8139_io_readb(opaque, addr + 1); | ||
2459 | +#else | ||
2460 | + ret = rtl8139_io_readb(opaque, addr); | ||
2461 | + ret |= rtl8139_io_readb(opaque, addr + 1) << 8; | ||
2462 | +#endif | ||
2463 | + | ||
2464 | +#ifdef DEBUG_RTL8139 | ||
2465 | + printf("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret); | ||
2466 | +#endif | ||
2467 | + break; | ||
2468 | + } | ||
2469 | + | ||
2470 | + return ret; | ||
2471 | +} | ||
2472 | + | ||
2473 | +static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) | ||
2474 | +{ | ||
2475 | + RTL8139State *s = opaque; | ||
2476 | + uint32_t ret; | ||
2477 | + | ||
2478 | + addr &= 0xfc; /* also mask low 2 bits */ | ||
2479 | + | ||
2480 | + switch (addr) | ||
2481 | + { | ||
2482 | + case RxMissed: | ||
2483 | + ret = s->RxMissed; | ||
2484 | + | ||
2485 | +#ifdef DEBUG_RTL8139 | ||
2486 | + printf("RTL8139: RxMissed read val=0x%08x\n", ret); | ||
2487 | +#endif | ||
2488 | + break; | ||
2489 | + | ||
2490 | + case TxConfig: | ||
2491 | + ret = rtl8139_TxConfig_read(s); | ||
2492 | + break; | ||
2493 | + | ||
2494 | + case RxConfig: | ||
2495 | + ret = rtl8139_RxConfig_read(s); | ||
2496 | + break; | ||
2497 | + | ||
2498 | + case TxStatus0 ... TxStatus0+4*4-1: | ||
2499 | + ret = rtl8139_TxStatus_read(s, addr-TxStatus0); | ||
2500 | + break; | ||
2501 | + | ||
2502 | + case TxAddr0 ... TxAddr0+4*4-1: | ||
2503 | + ret = rtl8139_TxAddr_read(s, addr-TxAddr0); | ||
2504 | + break; | ||
2505 | + | ||
2506 | + case RxBuf: | ||
2507 | + ret = rtl8139_RxBuf_read(s); | ||
2508 | + break; | ||
2509 | + | ||
2510 | + case RxRingAddrLO: | ||
2511 | + ret = s->RxRingAddrLO; | ||
2512 | +#ifdef DEBUG_RTL8139 | ||
2513 | + printf("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret); | ||
2514 | +#endif | ||
2515 | + break; | ||
2516 | + | ||
2517 | + case RxRingAddrHI: | ||
2518 | + ret = s->RxRingAddrHI; | ||
2519 | +#ifdef DEBUG_RTL8139 | ||
2520 | + printf("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret); | ||
2521 | +#endif | ||
2522 | + break; | ||
2523 | + | ||
2524 | + default: | ||
2525 | +#ifdef DEBUG_RTL8139 | ||
2526 | + printf("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr); | ||
2527 | +#endif | ||
2528 | + | ||
2529 | +#ifdef TARGET_WORDS_BIGENDIAN | ||
2530 | + ret = rtl8139_io_readb(opaque, addr) << 24; | ||
2531 | + ret |= rtl8139_io_readb(opaque, addr + 1) << 16; | ||
2532 | + ret |= rtl8139_io_readb(opaque, addr + 2) << 8; | ||
2533 | + ret |= rtl8139_io_readb(opaque, addr + 3); | ||
2534 | +#else | ||
2535 | + ret = rtl8139_io_readb(opaque, addr); | ||
2536 | + ret |= rtl8139_io_readb(opaque, addr + 1) << 8; | ||
2537 | + ret |= rtl8139_io_readb(opaque, addr + 2) << 16; | ||
2538 | + ret |= rtl8139_io_readb(opaque, addr + 3) << 24; | ||
2539 | +#endif | ||
2540 | + | ||
2541 | +#ifdef DEBUG_RTL8139 | ||
2542 | + printf("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret); | ||
2543 | +#endif | ||
2544 | + break; | ||
2545 | + } | ||
2546 | + | ||
2547 | + return ret; | ||
2548 | +} | ||
2549 | + | ||
2550 | +/* */ | ||
2551 | + | ||
2552 | +static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) | ||
2553 | +{ | ||
2554 | + rtl8139_io_writeb(opaque, addr & 0xFF, val); | ||
2555 | +} | ||
2556 | + | ||
2557 | +static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val) | ||
2558 | +{ | ||
2559 | + rtl8139_io_writew(opaque, addr & 0xFF, val); | ||
2560 | +} | ||
2561 | + | ||
2562 | +static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val) | ||
2563 | +{ | ||
2564 | + rtl8139_io_writel(opaque, addr & 0xFF, val); | ||
2565 | +} | ||
2566 | + | ||
2567 | +static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr) | ||
2568 | +{ | ||
2569 | + return rtl8139_io_readb(opaque, addr & 0xFF); | ||
2570 | +} | ||
2571 | + | ||
2572 | +static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr) | ||
2573 | +{ | ||
2574 | + return rtl8139_io_readw(opaque, addr & 0xFF); | ||
2575 | +} | ||
2576 | + | ||
2577 | +static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr) | ||
2578 | +{ | ||
2579 | + return rtl8139_io_readl(opaque, addr & 0xFF); | ||
2580 | +} | ||
2581 | + | ||
2582 | +/* */ | ||
2583 | + | ||
2584 | +static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | ||
2585 | +{ | ||
2586 | + rtl8139_io_writeb(opaque, addr & 0xFF, val); | ||
2587 | +} | ||
2588 | + | ||
2589 | +static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) | ||
2590 | +{ | ||
2591 | + rtl8139_io_writew(opaque, addr & 0xFF, val); | ||
2592 | +} | ||
2593 | + | ||
2594 | +static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | ||
2595 | +{ | ||
2596 | + rtl8139_io_writel(opaque, addr & 0xFF, val); | ||
2597 | +} | ||
2598 | + | ||
2599 | +static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr) | ||
2600 | +{ | ||
2601 | + return rtl8139_io_readb(opaque, addr & 0xFF); | ||
2602 | +} | ||
2603 | + | ||
2604 | +static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr) | ||
2605 | +{ | ||
2606 | + return rtl8139_io_readw(opaque, addr & 0xFF); | ||
2607 | +} | ||
2608 | + | ||
2609 | +static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr) | ||
2610 | +{ | ||
2611 | + return rtl8139_io_readl(opaque, addr & 0xFF); | ||
2612 | +} | ||
2613 | + | ||
2614 | +/* */ | ||
2615 | + | ||
2616 | +static void rtl8139_save(QEMUFile* f,void* opaque) | ||
2617 | +{ | ||
2618 | + RTL8139State* s=(RTL8139State*)opaque; | ||
2619 | + int i; | ||
2620 | + | ||
2621 | + qemu_put_buffer(f, s->phys, 6); | ||
2622 | + qemu_put_buffer(f, s->mult, 8); | ||
2623 | + | ||
2624 | + for (i=0; i<4; ++i) | ||
2625 | + { | ||
2626 | + qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */ | ||
2627 | + } | ||
2628 | + for (i=0; i<4; ++i) | ||
2629 | + { | ||
2630 | + qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */ | ||
2631 | + } | ||
2632 | + | ||
2633 | + qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */ | ||
2634 | + qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */ | ||
2635 | + qemu_put_be32s(f, &s->RxBufPtr); | ||
2636 | + qemu_put_be32s(f, &s->RxBufAddr); | ||
2637 | + | ||
2638 | + qemu_put_be16s(f, &s->IntrStatus); | ||
2639 | + qemu_put_be16s(f, &s->IntrMask); | ||
2640 | + | ||
2641 | + qemu_put_be32s(f, &s->TxConfig); | ||
2642 | + qemu_put_be32s(f, &s->RxConfig); | ||
2643 | + qemu_put_be32s(f, &s->RxMissed); | ||
2644 | + qemu_put_be16s(f, &s->CSCR); | ||
2645 | + | ||
2646 | + qemu_put_8s(f, &s->Cfg9346); | ||
2647 | + qemu_put_8s(f, &s->Config0); | ||
2648 | + qemu_put_8s(f, &s->Config1); | ||
2649 | + qemu_put_8s(f, &s->Config3); | ||
2650 | + qemu_put_8s(f, &s->Config4); | ||
2651 | + qemu_put_8s(f, &s->Config5); | ||
2652 | + | ||
2653 | + qemu_put_8s(f, &s->clock_enabled); | ||
2654 | + qemu_put_8s(f, &s->bChipCmdState); | ||
2655 | + | ||
2656 | + qemu_put_be16s(f, &s->MultiIntr); | ||
2657 | + | ||
2658 | + qemu_put_be16s(f, &s->BasicModeCtrl); | ||
2659 | + qemu_put_be16s(f, &s->BasicModeStatus); | ||
2660 | + qemu_put_be16s(f, &s->NWayAdvert); | ||
2661 | + qemu_put_be16s(f, &s->NWayLPAR); | ||
2662 | + qemu_put_be16s(f, &s->NWayExpansion); | ||
2663 | + | ||
2664 | + qemu_put_be16s(f, &s->CpCmd); | ||
2665 | + qemu_put_8s(f, &s->TxThresh); | ||
2666 | + | ||
2667 | + qemu_put_be32s(f, &s->irq); | ||
2668 | + qemu_put_buffer(f, s->macaddr, 6); | ||
2669 | + qemu_put_be32s(f, &s->rtl8139_mmio_io_addr); | ||
2670 | + | ||
2671 | + qemu_put_be32s(f, &s->currTxDesc); | ||
2672 | + qemu_put_be32s(f, &s->currCPlusRxDesc); | ||
2673 | + qemu_put_be32s(f, &s->currCPlusTxDesc); | ||
2674 | + qemu_put_be32s(f, &s->RxRingAddrLO); | ||
2675 | + qemu_put_be32s(f, &s->RxRingAddrHI); | ||
2676 | + | ||
2677 | + for (i=0; i<EEPROM_9346_SIZE; ++i) | ||
2678 | + { | ||
2679 | + qemu_put_be16s(f, &s->eeprom.contents[i]); | ||
2680 | + } | ||
2681 | + qemu_put_be32s(f, &s->eeprom.mode); | ||
2682 | + qemu_put_be32s(f, &s->eeprom.tick); | ||
2683 | + qemu_put_8s(f, &s->eeprom.address); | ||
2684 | + qemu_put_be16s(f, &s->eeprom.input); | ||
2685 | + qemu_put_be16s(f, &s->eeprom.output); | ||
2686 | + | ||
2687 | + qemu_put_8s(f, &s->eeprom.eecs); | ||
2688 | + qemu_put_8s(f, &s->eeprom.eesk); | ||
2689 | + qemu_put_8s(f, &s->eeprom.eedi); | ||
2690 | + qemu_put_8s(f, &s->eeprom.eedo); | ||
2691 | +} | ||
2692 | + | ||
2693 | +static int rtl8139_load(QEMUFile* f,void* opaque,int version_id) | ||
2694 | +{ | ||
2695 | + RTL8139State* s=(RTL8139State*)opaque; | ||
2696 | + int i; | ||
2697 | + | ||
2698 | + if (version_id != 1) | ||
2699 | + return -EINVAL; | ||
2700 | + | ||
2701 | + qemu_get_buffer(f, s->phys, 6); | ||
2702 | + qemu_get_buffer(f, s->mult, 8); | ||
2703 | + | ||
2704 | + for (i=0; i<4; ++i) | ||
2705 | + { | ||
2706 | + qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */ | ||
2707 | + } | ||
2708 | + for (i=0; i<4; ++i) | ||
2709 | + { | ||
2710 | + qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */ | ||
2711 | + } | ||
2712 | + | ||
2713 | + qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */ | ||
2714 | + qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */ | ||
2715 | + qemu_get_be32s(f, &s->RxBufPtr); | ||
2716 | + qemu_get_be32s(f, &s->RxBufAddr); | ||
2717 | + | ||
2718 | + qemu_get_be16s(f, &s->IntrStatus); | ||
2719 | + qemu_get_be16s(f, &s->IntrMask); | ||
2720 | + | ||
2721 | + qemu_get_be32s(f, &s->TxConfig); | ||
2722 | + qemu_get_be32s(f, &s->RxConfig); | ||
2723 | + qemu_get_be32s(f, &s->RxMissed); | ||
2724 | + qemu_get_be16s(f, &s->CSCR); | ||
2725 | + | ||
2726 | + qemu_get_8s(f, &s->Cfg9346); | ||
2727 | + qemu_get_8s(f, &s->Config0); | ||
2728 | + qemu_get_8s(f, &s->Config1); | ||
2729 | + qemu_get_8s(f, &s->Config3); | ||
2730 | + qemu_get_8s(f, &s->Config4); | ||
2731 | + qemu_get_8s(f, &s->Config5); | ||
2732 | + | ||
2733 | + qemu_get_8s(f, &s->clock_enabled); | ||
2734 | + qemu_get_8s(f, &s->bChipCmdState); | ||
2735 | + | ||
2736 | + qemu_get_be16s(f, &s->MultiIntr); | ||
2737 | + | ||
2738 | + qemu_get_be16s(f, &s->BasicModeCtrl); | ||
2739 | + qemu_get_be16s(f, &s->BasicModeStatus); | ||
2740 | + qemu_get_be16s(f, &s->NWayAdvert); | ||
2741 | + qemu_get_be16s(f, &s->NWayLPAR); | ||
2742 | + qemu_get_be16s(f, &s->NWayExpansion); | ||
2743 | + | ||
2744 | + qemu_get_be16s(f, &s->CpCmd); | ||
2745 | + qemu_get_8s(f, &s->TxThresh); | ||
2746 | + | ||
2747 | + qemu_get_be32s(f, &s->irq); | ||
2748 | + qemu_get_buffer(f, s->macaddr, 6); | ||
2749 | + qemu_get_be32s(f, &s->rtl8139_mmio_io_addr); | ||
2750 | + | ||
2751 | + qemu_get_be32s(f, &s->currTxDesc); | ||
2752 | + qemu_get_be32s(f, &s->currCPlusRxDesc); | ||
2753 | + qemu_get_be32s(f, &s->currCPlusTxDesc); | ||
2754 | + qemu_get_be32s(f, &s->RxRingAddrLO); | ||
2755 | + qemu_get_be32s(f, &s->RxRingAddrHI); | ||
2756 | + | ||
2757 | + for (i=0; i<EEPROM_9346_SIZE; ++i) | ||
2758 | + { | ||
2759 | + qemu_get_be16s(f, &s->eeprom.contents[i]); | ||
2760 | + } | ||
2761 | + qemu_get_be32s(f, &s->eeprom.mode); | ||
2762 | + qemu_get_be32s(f, &s->eeprom.tick); | ||
2763 | + qemu_get_8s(f, &s->eeprom.address); | ||
2764 | + qemu_get_be16s(f, &s->eeprom.input); | ||
2765 | + qemu_get_be16s(f, &s->eeprom.output); | ||
2766 | + | ||
2767 | + qemu_get_8s(f, &s->eeprom.eecs); | ||
2768 | + qemu_get_8s(f, &s->eeprom.eesk); | ||
2769 | + qemu_get_8s(f, &s->eeprom.eedi); | ||
2770 | + qemu_get_8s(f, &s->eeprom.eedo); | ||
2771 | + | ||
2772 | + return 0; | ||
2773 | +} | ||
2774 | + | ||
2775 | +/***********************************************************/ | ||
2776 | +/* PCI RTL8139 definitions */ | ||
2777 | + | ||
2778 | +typedef struct PCIRTL8139State { | ||
2779 | + PCIDevice dev; | ||
2780 | + RTL8139State rtl8139; | ||
2781 | +} PCIRTL8139State; | ||
2782 | + | ||
2783 | +static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num, | ||
2784 | + uint32_t addr, uint32_t size, int type) | ||
2785 | +{ | ||
2786 | + PCIRTL8139State *d = (PCIRTL8139State *)pci_dev; | ||
2787 | + RTL8139State *s = &d->rtl8139; | ||
2788 | + | ||
2789 | + cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr); | ||
2790 | +} | ||
2791 | + | ||
2792 | +static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num, | ||
2793 | + uint32_t addr, uint32_t size, int type) | ||
2794 | +{ | ||
2795 | + PCIRTL8139State *d = (PCIRTL8139State *)pci_dev; | ||
2796 | + RTL8139State *s = &d->rtl8139; | ||
2797 | + | ||
2798 | + register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s); | ||
2799 | + register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s); | ||
2800 | + | ||
2801 | + register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s); | ||
2802 | + register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s); | ||
2803 | + | ||
2804 | + register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s); | ||
2805 | + register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s); | ||
2806 | +} | ||
2807 | + | ||
2808 | +static CPUReadMemoryFunc *rtl8139_mmio_read[3] = { | ||
2809 | + rtl8139_mmio_readb, | ||
2810 | + rtl8139_mmio_readw, | ||
2811 | + rtl8139_mmio_readl, | ||
2812 | +}; | ||
2813 | + | ||
2814 | +static CPUWriteMemoryFunc *rtl8139_mmio_write[3] = { | ||
2815 | + rtl8139_mmio_writeb, | ||
2816 | + rtl8139_mmio_writew, | ||
2817 | + rtl8139_mmio_writel, | ||
2818 | +}; | ||
2819 | + | ||
2820 | +void pci_rtl8139_init(PCIBus *bus, NICInfo *nd) | ||
2821 | +{ | ||
2822 | + PCIRTL8139State *d; | ||
2823 | + RTL8139State *s; | ||
2824 | + uint8_t *pci_conf; | ||
2825 | + | ||
2826 | + d = (PCIRTL8139State *)pci_register_device(bus, | ||
2827 | + "RTL8139", sizeof(PCIRTL8139State), | ||
2828 | + -1, | ||
2829 | + NULL, NULL); | ||
2830 | + pci_conf = d->dev.config; | ||
2831 | + pci_conf[0x00] = 0xec; /* Realtek 8139 */ | ||
2832 | + pci_conf[0x01] = 0x10; | ||
2833 | + pci_conf[0x02] = 0x39; | ||
2834 | + pci_conf[0x03] = 0x81; | ||
2835 | + pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */ | ||
2836 | + pci_conf[0x08] = 0x20; /* 0x10 */ /* PCI revision ID; >=0x20 is for 8139C+ */ | ||
2837 | + pci_conf[0x0a] = 0x00; /* ethernet network controller */ | ||
2838 | + pci_conf[0x0b] = 0x02; | ||
2839 | + pci_conf[0x0e] = 0x00; /* header_type */ | ||
2840 | + pci_conf[0x3d] = 1; /* interrupt pin 0 */ | ||
2841 | + pci_conf[0x34] = 0xdc; | ||
2842 | + | ||
2843 | + s = &d->rtl8139; | ||
2844 | + | ||
2845 | + /* I/O handler for memory-mapped I/O */ | ||
2846 | + s->rtl8139_mmio_io_addr = | ||
2847 | + cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s); | ||
2848 | + | ||
2849 | + pci_register_io_region(&d->dev, 0, 0x100, | ||
2850 | + PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map); | ||
2851 | + | ||
2852 | + pci_register_io_region(&d->dev, 1, 0x100, | ||
2853 | + PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map); | ||
2854 | + | ||
2855 | + s->irq = 16; /* PCI interrupt */ | ||
2856 | + s->pci_dev = (PCIDevice *)d; | ||
2857 | + memcpy(s->macaddr, nd->macaddr, 6); | ||
2858 | + rtl8139_reset(s); | ||
2859 | + s->vc = qemu_new_vlan_client(nd->vlan, rtl8139_receive, | ||
2860 | + rtl8139_can_receive, s); | ||
2861 | + | ||
2862 | + snprintf(s->vc->info_str, sizeof(s->vc->info_str), | ||
2863 | + "rtl8139 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x", | ||
2864 | + s->macaddr[0], | ||
2865 | + s->macaddr[1], | ||
2866 | + s->macaddr[2], | ||
2867 | + s->macaddr[3], | ||
2868 | + s->macaddr[4], | ||
2869 | + s->macaddr[5]); | ||
2870 | + | ||
2871 | + /* XXX: instance number ? */ | ||
2872 | + register_savevm("rtl8139", 0, 1, rtl8139_save, rtl8139_load, s); | ||
2873 | + register_savevm("rtl8139_pci", 0, 1, generic_pci_save, generic_pci_load, | ||
2874 | + &d->dev); | ||
2875 | +} |
hw/sun4m.c
@@ -257,7 +257,15 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device, | @@ -257,7 +257,15 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device, | ||
257 | } | 257 | } |
258 | 258 | ||
259 | tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height); | 259 | tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height); |
260 | - lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA); | 260 | + if (nd_table[0].vlan) { |
261 | + if (nd_table[0].model == NULL | ||
262 | + || strcmp(nd_table[0].model, "lance") == 0) { | ||
263 | + lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA); | ||
264 | + } else { | ||
265 | + fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | ||
266 | + exit (1); | ||
267 | + } | ||
268 | + } | ||
261 | nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8); | 269 | nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8); |
262 | for (i = 0; i < MAX_CPUS; i++) { | 270 | for (i = 0; i < MAX_CPUS; i++) { |
263 | slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i); | 271 | slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i); |
hw/sun4u.c
@@ -347,7 +347,9 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, | @@ -347,7 +347,9 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, | ||
347 | } | 347 | } |
348 | 348 | ||
349 | for(i = 0; i < nb_nics; i++) { | 349 | for(i = 0; i < nb_nics; i++) { |
350 | - pci_ne2000_init(pci_bus, &nd_table[i]); | 350 | + if (!nd_table[i].model) |
351 | + nd_table[i].model = "ne2k_pci"; | ||
352 | + pci_nic_init(pci_bus, &nd_table[i]); | ||
351 | } | 353 | } |
352 | 354 | ||
353 | pci_cmd646_ide_init(pci_bus, bs_table, 1); | 355 | pci_cmd646_ide_init(pci_bus, bs_table, 1); |
qemu-doc.texi
@@ -252,11 +252,15 @@ Network options: | @@ -252,11 +252,15 @@ Network options: | ||
252 | 252 | ||
253 | @table @option | 253 | @table @option |
254 | 254 | ||
255 | -@item -net nic[,vlan=n][,macaddr=addr] | 255 | +@item -net nic[,vlan=n][,macaddr=addr][,model=type] |
256 | Create a new Network Interface Card and connect it to VLAN @var{n} (@var{n} | 256 | Create a new Network Interface Card and connect it to VLAN @var{n} (@var{n} |
257 | = 0 is the default). The NIC is currently an NE2000 on the PC | 257 | = 0 is the default). The NIC is currently an NE2000 on the PC |
258 | target. Optionally, the MAC address can be changed. If no | 258 | target. Optionally, the MAC address can be changed. If no |
259 | @option{-net} option is specified, a single NIC is created. | 259 | @option{-net} option is specified, a single NIC is created. |
260 | +Qemu can emulate several different models of network card. Valid values for | ||
261 | +@var{type} are @code{ne2k_pci}, @code{ne2k_isa}, @code{rtl8139}, | ||
262 | +@code{smc91c111} and @code{lance}. Not all devices are supported on all | ||
263 | +targets. | ||
260 | 264 | ||
261 | @item -net user[,vlan=n] | 265 | @item -net user[,vlan=n] |
262 | Use the user mode network stack which requires no administrator | 266 | Use the user mode network stack which requires no administrator |
vl.c
@@ -2718,6 +2718,9 @@ int net_client_init(const char *str) | @@ -2718,6 +2718,9 @@ int net_client_init(const char *str) | ||
2718 | return -1; | 2718 | return -1; |
2719 | } | 2719 | } |
2720 | } | 2720 | } |
2721 | + if (get_param_value(buf, sizeof(buf), "model", p)) { | ||
2722 | + nd->model = strdup(buf); | ||
2723 | + } | ||
2721 | nd->vlan = vlan; | 2724 | nd->vlan = vlan; |
2722 | nb_nics++; | 2725 | nb_nics++; |
2723 | ret = 0; | 2726 | ret = 0; |
@@ -4110,7 +4113,7 @@ void help(void) | @@ -4110,7 +4113,7 @@ void help(void) | ||
4110 | #endif | 4113 | #endif |
4111 | "\n" | 4114 | "\n" |
4112 | "Network options:\n" | 4115 | "Network options:\n" |
4113 | - "-net nic[,vlan=n][,macaddr=addr]\n" | 4116 | + "-net nic[,vlan=n][,macaddr=addr][,model=type]\n" |
4114 | " create a new Network Interface Card and connect it to VLAN 'n'\n" | 4117 | " create a new Network Interface Card and connect it to VLAN 'n'\n" |
4115 | #ifdef CONFIG_SLIRP | 4118 | #ifdef CONFIG_SLIRP |
4116 | "-net user[,vlan=n]\n" | 4119 | "-net user[,vlan=n]\n" |
vl.h
@@ -315,6 +315,7 @@ void tap_win32_poll(void); | @@ -315,6 +315,7 @@ void tap_win32_poll(void); | ||
315 | 315 | ||
316 | typedef struct NICInfo { | 316 | typedef struct NICInfo { |
317 | uint8_t macaddr[6]; | 317 | uint8_t macaddr[6]; |
318 | + const char *model; | ||
318 | VLANState *vlan; | 319 | VLANState *vlan; |
319 | } NICInfo; | 320 | } NICInfo; |
320 | 321 | ||
@@ -616,6 +617,8 @@ PCIBus *pci_grackle_init(uint32_t base); | @@ -616,6 +617,8 @@ PCIBus *pci_grackle_init(uint32_t base); | ||
616 | PCIBus *pci_pmac_init(void); | 617 | PCIBus *pci_pmac_init(void); |
617 | PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base); | 618 | PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base); |
618 | 619 | ||
620 | +void pci_nic_init(PCIBus *bus, NICInfo *nd); | ||
621 | + | ||
619 | /* openpic.c */ | 622 | /* openpic.c */ |
620 | typedef struct openpic_t openpic_t; | 623 | typedef struct openpic_t openpic_t; |
621 | void openpic_set_irq(void *opaque, int n_IRQ, int level); | 624 | void openpic_set_irq(void *opaque, int n_IRQ, int level); |
@@ -740,6 +743,10 @@ int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num); | @@ -740,6 +743,10 @@ int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num); | ||
740 | void isa_ne2000_init(int base, int irq, NICInfo *nd); | 743 | void isa_ne2000_init(int base, int irq, NICInfo *nd); |
741 | void pci_ne2000_init(PCIBus *bus, NICInfo *nd); | 744 | void pci_ne2000_init(PCIBus *bus, NICInfo *nd); |
742 | 745 | ||
746 | +/* rtl8139.c */ | ||
747 | + | ||
748 | +void pci_rtl8139_init(PCIBus *bus, NICInfo *nd); | ||
749 | + | ||
743 | /* pckbd.c */ | 750 | /* pckbd.c */ |
744 | 751 | ||
745 | void kbd_init(void); | 752 | void kbd_init(void); |