Commit a39f8f3ad95bcc9912e92a752f019e755dce8d5b

Authored by edgar_igl
1 parent 34808ac1

CRIS: Remove some old dyngen T0/T1 fiddle. More usage of the results from the x …

…flag liveness analysis.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4433 c046a42c-6fe2-441c-8c8c-71466251a162
Showing 1 changed file with 38 additions and 34 deletions
target-cris/translate.c
... ... @@ -483,24 +483,36 @@ static inline void t_gen_addx_carry(TCGv d)
483 483 tcg_gen_discard_tl(c);
484 484 }
485 485  
486   -static inline void t_gen_subx_carry(TCGv d)
  486 +static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
487 487 {
488   - TCGv x, c;
  488 + if (dc->flagx_live) {
  489 + TCGv x, c;
489 490  
490   - x = tcg_temp_new(TCG_TYPE_TL);
491   - c = tcg_temp_new(TCG_TYPE_TL);
492   - t_gen_mov_TN_preg(x, PR_CCS);
493   - tcg_gen_mov_tl(c, x);
  491 + x = tcg_temp_new(TCG_TYPE_TL);
  492 + c = tcg_temp_new(TCG_TYPE_TL);
  493 + t_gen_mov_TN_preg(x, PR_CCS);
  494 + tcg_gen_mov_tl(c, x);
494 495  
495   - /* Propagate carry into d if X is set. Branch free. */
496   - tcg_gen_andi_tl(c, c, C_FLAG);
497   - tcg_gen_andi_tl(x, x, X_FLAG);
498   - tcg_gen_shri_tl(x, x, 4);
  496 + /* Propagate carry into d if X is set. Branch free. */
  497 + tcg_gen_andi_tl(c, c, C_FLAG);
  498 + tcg_gen_andi_tl(x, x, X_FLAG);
  499 + tcg_gen_shri_tl(x, x, 4);
499 500  
500   - tcg_gen_and_tl(x, x, c);
501   - tcg_gen_sub_tl(d, d, x);
502   - tcg_gen_discard_tl(x);
503   - tcg_gen_discard_tl(c);
  501 + tcg_gen_and_tl(x, x, c);
  502 + tcg_gen_sub_tl(d, d, x);
  503 + tcg_gen_discard_tl(x);
  504 + tcg_gen_discard_tl(c);
  505 + } else {
  506 + if (dc->flags_x) {
  507 + TCGv c;
  508 +
  509 + c = tcg_temp_new(TCG_TYPE_TL);
  510 + /* C flag is already at bit 0. */
  511 + tcg_gen_andi_tl(c, c, C_FLAG);
  512 + tcg_gen_add_tl(d, d, c);
  513 + tcg_gen_discard_tl(c);
  514 + }
  515 + }
504 516 }
505 517  
506 518 /* Swap the two bytes within each half word of the s operand.
... ... @@ -633,7 +645,7 @@ static inline void cris_clear_x_flag(DisasContext *dc)
633 645 {
634 646 if (!dc->flagx_live
635 647 || (dc->flagx_live && dc->flags_x)
636   - || dc->cc_op != CC_OP_FLAGS)
  648 + || dc->cc_op == CC_OP_FLAGS)
637 649 tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
638 650 dc->flagx_live = 1;
639 651 dc->flags_x = 0;
... ... @@ -760,7 +772,7 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
760 772 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
761 773  
762 774 /* Extended arithmetics. */
763   - t_gen_subx_carry(cpu_T[0]);
  775 + t_gen_subx_carry(dc, cpu_T[0]);
764 776 break;
765 777 case CC_OP_MOVE:
766 778 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
... ... @@ -786,7 +798,7 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
786 798 case CC_OP_NEG:
787 799 tcg_gen_neg_tl(cpu_T[0], cpu_T[1]);
788 800 /* Extended arithmetics. */
789   - t_gen_subx_carry(cpu_T[0]);
  801 + t_gen_subx_carry(dc, cpu_T[0]);
790 802 break;
791 803 case CC_OP_LZ:
792 804 t_gen_lz_i32(cpu_T[0], cpu_T[1]);
... ... @@ -827,15 +839,12 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
827 839 }
828 840 break;
829 841 case CC_OP_CMP:
830   - tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
831   - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
832   - /* CRIS flag evaluation needs ~src. */
833   - tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
  842 + tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
834 843 /* CRIS flag evaluation needs ~src. */
835   - tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
  844 + tcg_gen_xori_tl(cpu_T[1], cpu_T[1], ~0);
836 845  
837 846 /* Extended arithmetics. */
838   - t_gen_subx_carry(cpu_T[0]);
  847 + t_gen_subx_carry(dc, cpu_T[0]);
839 848 writeback = 0;
840 849 break;
841 850 default:
... ... @@ -855,17 +864,13 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
855 864 /* Writeback. */
856 865 if (writeback) {
857 866 if (size == 4)
858   - t_gen_mov_reg_TN(rd, cpu_T[0]);
  867 + tcg_gen_mov_tl(cpu_R[rd], cpu_T[0]);
859 868 else {
860   - tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
861   - t_gen_mov_TN_reg(cpu_T[0], rd);
862 869 if (size == 1)
863   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);
  870 + tcg_gen_andi_tl(cpu_R[rd], cpu_R[rd], ~0xff);
864 871 else
865   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);
866   - tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
867   - t_gen_mov_reg_TN(rd, cpu_T[0]);
868   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  872 + tcg_gen_andi_tl(cpu_R[rd], cpu_R[rd], ~0xffff);
  873 + tcg_gen_or_tl(cpu_R[rd], cpu_R[rd], cpu_T[0]);
869 874 }
870 875 }
871 876 if (dc->update_cc)
... ... @@ -1208,7 +1213,6 @@ static inline void do_postinc (DisasContext *dc, int size)
1208 1213 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1209 1214 }
1210 1215  
1211   -
1212 1216 static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1213 1217 int size, int s_ext)
1214 1218 {
... ... @@ -1352,7 +1356,7 @@ static unsigned int dec_moveq(DisasContext *dc)
1352 1356 imm = sign_extend(dc->op1, 5);
1353 1357 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1354 1358  
1355   - t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
  1359 + tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
1356 1360 return 2;
1357 1361 }
1358 1362 static unsigned int dec_subq(DisasContext *dc)
... ... @@ -1363,7 +1367,7 @@ static unsigned int dec_subq(DisasContext *dc)
1363 1367  
1364 1368 cris_cc_mask(dc, CC_MASK_NZVC);
1365 1369 /* Fetch register operand, */
1366   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  1370 + tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
1367 1371 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1368 1372 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1369 1373 return 2;
... ...