gwj / at91sam9263 · Commits

Commit a35e86c55fa2858c7828058f2e59956597aaa7af

Authored by malc
1 parent d50997f9

Shuffle contents of tcg_target_reg_alloc_order 

Move reserved/volatile registers down. Currently qemu_ld/stXX are
marked with TCG_OPF_CALL_CLOBBER and since memory accesses are
frequent and R3 through R12 are volatile moving this down results in
less spills and tighter generated code.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4778 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 18 additions and 18 deletions
tcg/ppc/tcg-target.c
  View file @a35e86c
... ... @@ -67,9 +67,20 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
67 67 };
68 68  
69 69 static const int tcg_target_reg_alloc_order[] = {
70   - TCG_REG_R0,
71   - TCG_REG_R1,
72   - TCG_REG_R2,
  70 + TCG_REG_R14,
  71 + TCG_REG_R15,
  72 + TCG_REG_R16,
  73 + TCG_REG_R17,
  74 + TCG_REG_R18,
  75 + TCG_REG_R19,
  76 + TCG_REG_R20,
  77 + TCG_REG_R21,
  78 + TCG_REG_R22,
  79 + TCG_REG_R23,
  80 + TCG_REG_R28,
  81 + TCG_REG_R29,
  82 + TCG_REG_R30,
  83 + TCG_REG_R31,
73 84 TCG_REG_R3,
74 85 TCG_REG_R4,
75 86 TCG_REG_R5,
... ... @@ -81,24 +92,13 @@ static const int tcg_target_reg_alloc_order[] = {
81 92 TCG_REG_R11,
82 93 TCG_REG_R12,
83 94 TCG_REG_R13,
84   - TCG_REG_R14,
85   - TCG_REG_R15,
86   - TCG_REG_R16,
87   - TCG_REG_R17,
88   - TCG_REG_R18,
89   - TCG_REG_R19,
90   - TCG_REG_R20,
91   - TCG_REG_R21,
92   - TCG_REG_R22,
93   - TCG_REG_R23,
  95 + TCG_REG_R0,
  96 + TCG_REG_R1,
  97 + TCG_REG_R2,
94 98 TCG_REG_R24,
95 99 TCG_REG_R25,
96 100 TCG_REG_R26,
97   - TCG_REG_R27,
98   - TCG_REG_R28,
99   - TCG_REG_R29,
100   - TCG_REG_R30,
101   - TCG_REG_R31
  101 + TCG_REG_R27
102 102 };
103 103  
104 104 static const int tcg_target_call_iarg_regs[] = {
... ...