Commit a343df1659d59fa20b8fa642f5eb92c5aad2eab9
1 parent
98ff7d30
ne2000 reset fix - start/stop registers read access (aka OS/2 Warp V4 fix) (lukewarm)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1422 c046a42c-6fe2-441c-8c8c-71466251a162
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11 additions
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2 deletions
hw/ne2000.c
| @@ -61,6 +61,9 @@ | @@ -61,6 +61,9 @@ | ||
| 61 | #define EN1_CURPAG 0x17 | 61 | #define EN1_CURPAG 0x17 |
| 62 | #define EN1_MULT 0x18 | 62 | #define EN1_MULT 0x18 |
| 63 | 63 | ||
| 64 | +#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ | ||
| 65 | +#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ | ||
| 66 | + | ||
| 64 | /* Register accessed at EN_CMD, the 8390 base addr. */ | 67 | /* Register accessed at EN_CMD, the 8390 base addr. */ |
| 65 | #define E8390_STOP 0x01 /* Stop and reset the chip */ | 68 | #define E8390_STOP 0x01 /* Stop and reset the chip */ |
| 66 | #define E8390_START 0x02 /* Start the chip, clear reset */ | 69 | #define E8390_START 0x02 /* Start the chip, clear reset */ |
| @@ -150,7 +153,7 @@ static void ne2000_reset(NE2000State *s) | @@ -150,7 +153,7 @@ static void ne2000_reset(NE2000State *s) | ||
| 150 | static void ne2000_update_irq(NE2000State *s) | 153 | static void ne2000_update_irq(NE2000State *s) |
| 151 | { | 154 | { |
| 152 | int isr; | 155 | int isr; |
| 153 | - isr = s->isr & s->imr; | 156 | + isr = (s->isr & s->imr) & 0x7f; |
| 154 | #if defined(DEBUG_NE2000) | 157 | #if defined(DEBUG_NE2000) |
| 155 | printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n", | 158 | printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n", |
| 156 | s->irq, isr ? 1 : 0, s->isr, s->imr); | 159 | s->irq, isr ? 1 : 0, s->isr, s->imr); |
| @@ -255,7 +258,7 @@ static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) | @@ -255,7 +258,7 @@ static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) | ||
| 255 | if (addr == E8390_CMD) { | 258 | if (addr == E8390_CMD) { |
| 256 | /* control register */ | 259 | /* control register */ |
| 257 | s->cmd = val; | 260 | s->cmd = val; |
| 258 | - if (val & E8390_START) { | 261 | + if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ |
| 259 | s->isr &= ~ENISR_RESET; | 262 | s->isr &= ~ENISR_RESET; |
| 260 | /* test specific case: zero length transfert */ | 263 | /* test specific case: zero length transfert */ |
| 261 | if ((val & (E8390_RREAD | E8390_RWRITE)) && | 264 | if ((val & (E8390_RREAD | E8390_RWRITE)) && |
| @@ -376,6 +379,12 @@ static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) | @@ -376,6 +379,12 @@ static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) | ||
| 376 | case EN0_RSR: | 379 | case EN0_RSR: |
| 377 | ret = s->rsr; | 380 | ret = s->rsr; |
| 378 | break; | 381 | break; |
| 382 | + case EN2_STARTPG: | ||
| 383 | + ret = s->start >> 8; | ||
| 384 | + break; | ||
| 385 | + case EN2_STOPPG: | ||
| 386 | + ret = s->stop >> 8; | ||
| 387 | + break; | ||
| 379 | default: | 388 | default: |
| 380 | ret = 0x00; | 389 | ret = 0x00; |
| 381 | break; | 390 | break; |