gwj / at91sam9263 · Commits

Commit a23978077ba006c8afdd842a448d5ac7106827ff

Authored by Jan Kiszka
Committed by Anthony Liguori
1 parent 37cb6fc3

x86: Add support for resume flag 

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Inline Side-by-side
Showing 4 changed files with 17 additions and 4 deletions
target-i386/cpu.h
  View file @a239780
@@ -145,11 +145,12 @@ @@ -145,11 +145,12 @@
145 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 145 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
146 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 146 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
147 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 147 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
148 -#define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */ 148 +#define HF_RF_SHIFT 16 /* must be same as eflags */
149 #define HF_VM_SHIFT 17 /* must be same as eflags */ 149 #define HF_VM_SHIFT 17 /* must be same as eflags */
150 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 150 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
151 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 151 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
152 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ 152 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */
  153 +#define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
153 154
154 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 155 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
155 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) 156 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
@@ -165,11 +166,12 @@ @@ -165,11 +166,12 @@
165 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 166 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
166 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 167 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
167 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 168 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
168 -#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 169 +#define HF_RF_MASK (1 << HF_RF_SHIFT)
169 #define HF_VM_MASK (1 << HF_VM_SHIFT) 170 #define HF_VM_MASK (1 << HF_VM_SHIFT)
170 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 171 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
171 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 172 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
172 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) 173 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
  174 +#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
173 175
174 /* hflags2 */ 176 /* hflags2 */
175 177
@@ -881,7 +883,8 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, @@ -881,7 +883,8 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
881 { 883 {
882 *cs_base = env->segs[R_CS].base; 884 *cs_base = env->segs[R_CS].base;
883 *pc = *cs_base + env->eip; 885 *pc = *cs_base + env->eip;
884 - *flags = env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); 886 + *flags = env->hflags |
  887 + (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
885 } 888 }
886 889
887 #endif /* CPU_I386_H */ 890 #endif /* CPU_I386_H */
target-i386/helper.h
  View file @a239780
@@ -62,6 +62,7 @@ DEF_HELPER_1(hlt, void, int) @@ -62,6 +62,7 @@ DEF_HELPER_1(hlt, void, int)
62 DEF_HELPER_1(monitor, void, tl) 62 DEF_HELPER_1(monitor, void, tl)
63 DEF_HELPER_1(mwait, void, int) 63 DEF_HELPER_1(mwait, void, int)
64 DEF_HELPER_0(debug, void) 64 DEF_HELPER_0(debug, void)
  65 +DEF_HELPER_0(reset_rf, void)
65 DEF_HELPER_2(raise_interrupt, void, int, int) 66 DEF_HELPER_2(raise_interrupt, void, int, int)
66 DEF_HELPER_1(raise_exception, void, int) 67 DEF_HELPER_1(raise_exception, void, int)
67 DEF_HELPER_0(cli, void) 68 DEF_HELPER_0(cli, void)
target-i386/op_helper.c
  View file @a239780
@@ -4688,6 +4688,11 @@ void helper_debug(void) @@ -4688,6 +4688,11 @@ void helper_debug(void)
4688 cpu_loop_exit(); 4688 cpu_loop_exit();
4689 } 4689 }
4690 4690
  4691 +void helper_reset_rf(void)
  4692 +{
  4693 + env->eflags &= ~RF_MASK;
  4694 +}
  4695 +
4691 void helper_raise_interrupt(int intno, int next_eip_addend) 4696 void helper_raise_interrupt(int intno, int next_eip_addend)
4692 { 4697 {
4693 raise_interrupt(intno, 1, 0, next_eip_addend); 4698 raise_interrupt(intno, 1, 0, next_eip_addend);
target-i386/translate.c
  View file @a239780
@@ -2704,6 +2704,9 @@ static void gen_eob(DisasContext *s) @@ -2704,6 +2704,9 @@ static void gen_eob(DisasContext *s)
2704 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { 2704 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2705 gen_helper_reset_inhibit_irq(); 2705 gen_helper_reset_inhibit_irq();
2706 } 2706 }
  2707 + if (s->tb->flags & HF_RF_MASK) {
  2708 + gen_helper_reset_rf();
  2709 + }
2707 if (s->singlestep_enabled) { 2710 if (s->singlestep_enabled) {
2708 gen_helper_debug(); 2711 gen_helper_debug();
2709 } else if (s->tf) { 2712 } else if (s->tf) {
@@ -7687,7 +7690,8 @@ static inline void gen_intermediate_code_internal(CPUState *env, @@ -7687,7 +7690,8 @@ static inline void gen_intermediate_code_internal(CPUState *env,
7687 for(;;) { 7690 for(;;) {
7688 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { 7691 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7689 TAILQ_FOREACH(bp, &env->breakpoints, entry) { 7692 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
7690 - if (bp->pc == pc_ptr) { 7693 + if (bp->pc == pc_ptr &&
  7694 + !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
7691 gen_debug(dc, pc_ptr - dc->cs_base); 7695 gen_debug(dc, pc_ptr - dc->cs_base);
7692 break; 7696 break;
7693 } 7697 }