gwj / at91sam9263 · Commits

Commit a21ae81d8ad647cb9b7869367edf646f37e4e4e5

Authored by bellard
1 parent aeb3c85f

change ID to CLGD5446 - added solidfill support - fixed hidden dac access 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@899 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 205 additions and 73 deletions
hw/cirrus_vga.c
  View file @a21ae81
... ... @@ -30,6 +30,7 @@
30 30 #include "vga_int.h"
31 31  
32 32 //#define DEBUG_CIRRUS
  33 +//#define DEBUG_BITBLT
33 34  
34 35 /***************************************
35 36 *
... ... @@ -46,8 +47,14 @@
46 47 #define CIRRUS_ID_CLGD5428 (0x26<<2)
47 48 #define CIRRUS_ID_CLGD5430 (0x28<<2)
48 49 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
  50 +#define CIRRUS_ID_CLGD5436 (0x2B<<2)
49 51 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
50 52  
  53 +/* this define is used to select the exact CLGD implementation we
  54 + emulate. */
  55 +//#define CIRRUS_ID CIRRUS_ID_CLGD5430
  56 +#define CIRRUS_ID CIRRUS_ID_CLGD5446
  57 +
51 58 // sequencer 0x07
52 59 #define CIRRUS_SR7_BPP_VGA 0x00
53 60 #define CIRRUS_SR7_BPP_SVGA 0x01
... ... @@ -120,6 +127,9 @@
120 127 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
121 128 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
122 129  
  130 +// control 0x33
  131 +#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
  132 +
123 133 // memory-mapped IO
124 134 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
125 135 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
... ... @@ -153,12 +163,10 @@
153 163  
154 164 // PCI 0x00: vendor, 0x02: device
155 165 #define PCI_VENDOR_CIRRUS 0x1013
156   -#define PCI_DEVICE_CLGD5430 0x00a0 // CLGD5430 or CLGD5440
157   -#define PCI_DEVICE_CLGD5434 0x00a8
158   -#define PCI_DEVICE_CLGD5436 0x00ac
159   -#define PCI_DEVICE_CLGD5446 0x00b8
  166 +#define PCI_DEVICE_ID CIRRUS_ID
160 167 #define PCI_DEVICE_CLGD5462 0x00d0
161 168 #define PCI_DEVICE_CLGD5465 0x00d6
  169 +
162 170 // PCI 0x04: command(word), 0x06(word): status
163 171 #define PCI_COMMAND_IOACCESS 0x0001
164 172 #define PCI_COMMAND_MEMACCESS 0x0002
... ... @@ -195,7 +203,7 @@
195 203 // PCI 0x38: reserved
196 204 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
197 205  
198   -#define CIRRUS_PNPMMIO_SIZE 0x800
  206 +#define CIRRUS_PNPMMIO_SIZE 0x1000
199 207  
200 208  
201 209 /* I/O and memory hook */
... ... @@ -264,7 +272,7 @@ static void cirrus_bitblt_reset(CirrusVGAState * s);
264 272 *
265 273 ***************************************/
266 274  
267   -#define IMPLEMENT_FORWARD_BITBLT(name,opline) \
  275 +#define IMPLEMENT_BITBLT(name,opline) \
268 276 static void \
269 277 cirrus_bitblt_rop_fwd_##name( \
270 278 uint8_t *dst,const uint8_t *src, \
... ... @@ -283,9 +291,8 @@ static void cirrus_bitblt_reset(CirrusVGAState * s);
283 291 dst += dstpitch; \
284 292 src += srcpitch; \
285 293 } \
286   - }
287   -
288   -#define IMPLEMENT_BACKWARD_BITBLT(name,opline) \
  294 + } \
  295 + \
289 296 static void \
290 297 cirrus_bitblt_rop_bkwd_##name( \
291 298 uint8_t *dst,const uint8_t *src, \
... ... @@ -306,39 +313,22 @@ static void cirrus_bitblt_reset(CirrusVGAState * s);
306 313 } \
307 314 }
308 315  
309   -IMPLEMENT_FORWARD_BITBLT(0, *dst = 0)
310   - IMPLEMENT_FORWARD_BITBLT(src_and_dst, *dst = (*src) & (*dst))
311   - IMPLEMENT_FORWARD_BITBLT(nop, (void) 0)
312   - IMPLEMENT_FORWARD_BITBLT(src_and_notdst, *dst = (*src) & (~(*dst)))
313   - IMPLEMENT_FORWARD_BITBLT(notdst, *dst = ~(*dst))
314   - IMPLEMENT_FORWARD_BITBLT(src, *dst = *src)
315   - IMPLEMENT_FORWARD_BITBLT(1, *dst = 0xff)
316   - IMPLEMENT_FORWARD_BITBLT(notsrc_and_dst, *dst = (~(*src)) & (*dst))
317   - IMPLEMENT_FORWARD_BITBLT(src_xor_dst, *dst = (*src) ^ (*dst))
318   - IMPLEMENT_FORWARD_BITBLT(src_or_dst, *dst = (*src) | (*dst))
319   - IMPLEMENT_FORWARD_BITBLT(notsrc_or_notdst, *dst = (~(*src)) | (~(*dst)))
320   - IMPLEMENT_FORWARD_BITBLT(src_notxor_dst, *dst = ~((*src) ^ (*dst)))
321   - IMPLEMENT_FORWARD_BITBLT(src_or_notdst, *dst = (*src) | (~(*dst)))
322   - IMPLEMENT_FORWARD_BITBLT(notsrc, *dst = (~(*src)))
323   - IMPLEMENT_FORWARD_BITBLT(notsrc_or_dst, *dst = (~(*src)) | (*dst))
324   - IMPLEMENT_FORWARD_BITBLT(notsrc_and_notdst, *dst = (~(*src)) & (~(*dst)))
325   -
326   - IMPLEMENT_BACKWARD_BITBLT(0, *dst = 0)
327   - IMPLEMENT_BACKWARD_BITBLT(src_and_dst, *dst = (*src) & (*dst))
328   - IMPLEMENT_BACKWARD_BITBLT(nop, (void) 0)
329   - IMPLEMENT_BACKWARD_BITBLT(src_and_notdst, *dst = (*src) & (~(*dst)))
330   - IMPLEMENT_BACKWARD_BITBLT(notdst, *dst = ~(*dst))
331   - IMPLEMENT_BACKWARD_BITBLT(src, *dst = *src)
332   - IMPLEMENT_BACKWARD_BITBLT(1, *dst = 0xff)
333   - IMPLEMENT_BACKWARD_BITBLT(notsrc_and_dst, *dst = (~(*src)) & (*dst))
334   - IMPLEMENT_BACKWARD_BITBLT(src_xor_dst, *dst = (*src) ^ (*dst))
335   - IMPLEMENT_BACKWARD_BITBLT(src_or_dst, *dst = (*src) | (*dst))
336   - IMPLEMENT_BACKWARD_BITBLT(notsrc_or_notdst, *dst = (~(*src)) | (~(*dst)))
337   - IMPLEMENT_BACKWARD_BITBLT(src_notxor_dst, *dst = ~((*src) ^ (*dst)))
338   - IMPLEMENT_BACKWARD_BITBLT(src_or_notdst, *dst = (*src) | (~(*dst)))
339   - IMPLEMENT_BACKWARD_BITBLT(notsrc, *dst = (~(*src)))
340   - IMPLEMENT_BACKWARD_BITBLT(notsrc_or_dst, *dst = (~(*src)) | (*dst))
341   - IMPLEMENT_BACKWARD_BITBLT(notsrc_and_notdst, *dst = (~(*src)) & (~(*dst)))
  316 +IMPLEMENT_BITBLT(0, *dst = 0)
  317 +IMPLEMENT_BITBLT(src_and_dst, *dst = (*src) & (*dst))
  318 +IMPLEMENT_BITBLT(nop, (void) 0)
  319 +IMPLEMENT_BITBLT(src_and_notdst, *dst = (*src) & (~(*dst)))
  320 +IMPLEMENT_BITBLT(notdst, *dst = ~(*dst))
  321 +IMPLEMENT_BITBLT(src, *dst = *src)
  322 +IMPLEMENT_BITBLT(1, *dst = 0xff)
  323 +IMPLEMENT_BITBLT(notsrc_and_dst, *dst = (~(*src)) & (*dst))
  324 +IMPLEMENT_BITBLT(src_xor_dst, *dst = (*src) ^ (*dst))
  325 +IMPLEMENT_BITBLT(src_or_dst, *dst = (*src) | (*dst))
  326 +IMPLEMENT_BITBLT(notsrc_or_notdst, *dst = (~(*src)) | (~(*dst)))
  327 +IMPLEMENT_BITBLT(src_notxor_dst, *dst = ~((*src) ^ (*dst)))
  328 +IMPLEMENT_BITBLT(src_or_notdst, *dst = (*src) | (~(*dst)))
  329 +IMPLEMENT_BITBLT(notsrc, *dst = (~(*src)))
  330 +IMPLEMENT_BITBLT(notsrc_or_dst, *dst = (~(*src)) | (*dst))
  331 +IMPLEMENT_BITBLT(notsrc_and_notdst, *dst = (~(*src)) & (~(*dst)))
342 332  
343 333 static cirrus_bitblt_rop_t cirrus_get_fwd_rop_handler(uint8_t rop)
344 334 {
... ... @@ -666,7 +656,7 @@ static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
666 656 #endif
667 657 return 0;
668 658 }
669   -
  659 +
670 660 dst = s->vram_ptr + s->cirrus_blt_dstaddr;
671 661 for (y = 0; y < s->cirrus_blt_height; y += 8) {
672 662 dstc = dst;
... ... @@ -686,6 +676,120 @@ static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
686 676 return 1;
687 677 }
688 678  
  679 +/* fill */
  680 +
  681 +static void cirrus_fill_8(CirrusVGAState *s,
  682 + uint8_t *dst, int dst_pitch, int width, int height)
  683 +{
  684 + uint8_t *d, *d1;
  685 + uint32_t val;
  686 + int x, y;
  687 +
  688 + val = s->cirrus_shadow_gr1;
  689 +
  690 + d1 = dst;
  691 + for(y = 0; y < height; y++) {
  692 + d = d1;
  693 + for(x = 0; x < width; x++) {
  694 + *d++ = val;
  695 + }
  696 + d1 += dst_pitch;
  697 + }
  698 +}
  699 +
  700 +static void cirrus_fill_16(CirrusVGAState *s,
  701 + uint8_t *dst, int dst_pitch, int width, int height)
  702 +{
  703 + uint8_t *d, *d1;
  704 + uint32_t val;
  705 + int x, y;
  706 +
  707 + val = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
  708 + val = le16_to_cpu(val);
  709 + width >>= 1;
  710 +
  711 + d1 = dst;
  712 + for(y = 0; y < height; y++) {
  713 + d = d1;
  714 + for(x = 0; x < width; x++) {
  715 + ((uint16_t *)d)[0] = val;
  716 + d += 2;
  717 + }
  718 + d1 += dst_pitch;
  719 + }
  720 +}
  721 +
  722 +static void cirrus_fill_24(CirrusVGAState *s,
  723 + uint8_t *dst, int dst_pitch, int width, int height)
  724 +{
  725 + uint8_t *d, *d1;
  726 + int x, y;
  727 +
  728 + d1 = dst;
  729 + for(y = 0; y < height; y++) {
  730 + d = d1;
  731 + for(x = 0; x < width; x += 3) {
  732 + *d++ = s->cirrus_shadow_gr1;
  733 + *d++ = s->gr[0x11];
  734 + *d++ = s->gr[0x13];
  735 + }
  736 + d1 += dst_pitch;
  737 + }
  738 +}
  739 +
  740 +static void cirrus_fill_32(CirrusVGAState *s,
  741 + uint8_t *dst, int dst_pitch, int width, int height)
  742 +{
  743 + uint8_t *d, *d1;
  744 + uint32_t val;
  745 + int x, y;
  746 +
  747 + val = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
  748 + (s->gr[0x13] << 8) | (s->gr[0x15] << 8);
  749 + val = le32_to_cpu(val);
  750 + width >>= 2;
  751 +
  752 + d1 = dst;
  753 + for(y = 0; y < height; y++) {
  754 + d = d1;
  755 + for(x = 0; x < width; x++) {
  756 + ((uint32_t *)d)[0] = val;
  757 + d += 4;
  758 + }
  759 + d1 += dst_pitch;
  760 + }
  761 +}
  762 +
  763 +static int cirrus_bitblt_solidfill(CirrusVGAState *s)
  764 +{
  765 + uint8_t *dst;
  766 + dst = s->vram_ptr + s->cirrus_blt_dstaddr;
  767 + switch (s->cirrus_blt_pixelwidth) {
  768 + case 1:
  769 + cirrus_fill_8(s, dst, s->cirrus_blt_dstpitch,
  770 + s->cirrus_blt_width, s->cirrus_blt_height);
  771 + break;
  772 + case 2:
  773 + cirrus_fill_16(s, dst, s->cirrus_blt_dstpitch,
  774 + s->cirrus_blt_width, s->cirrus_blt_height);
  775 + break;
  776 + case 3:
  777 + cirrus_fill_24(s, dst, s->cirrus_blt_dstpitch,
  778 + s->cirrus_blt_width, s->cirrus_blt_height);
  779 + break;
  780 + default:
  781 + case 4:
  782 + cirrus_fill_32(s, dst, s->cirrus_blt_dstpitch,
  783 + s->cirrus_blt_width, s->cirrus_blt_height);
  784 + break;
  785 + }
  786 + cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
  787 + s->cirrus_blt_dstpitch, s->cirrus_blt_width,
  788 + s->cirrus_blt_height);
  789 + cirrus_bitblt_reset(s);
  790 + return 1;
  791 +}
  792 +
689 793 /***************************************
690 794 *
691 795 * bitblt (video-to-video)
... ... @@ -952,6 +1056,19 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
952 1056 s->cirrus_blt_mode = s->gr[0x30];
953 1057 blt_rop = s->gr[0x32];
954 1058  
  1059 +#ifdef DEBUG_BITBLT
  1060 + printf("rop=%02x mode=%02x modeext=%02x w=%d h=%d dpitch=%d spicth=%d daddr=%08x saddr=%08x\n",
  1061 + blt_rop,
  1062 + s->cirrus_blt_mode,
  1063 + s->gr[0x33],
  1064 + s->cirrus_blt_width,
  1065 + s->cirrus_blt_height,
  1066 + s->cirrus_blt_dstpitch,
  1067 + s->cirrus_blt_srcpitch,
  1068 + s->cirrus_blt_dstaddr,
  1069 + s->cirrus_blt_srcaddr);
  1070 +#endif
  1071 +
955 1072 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
956 1073 case CIRRUS_BLTMODE_PIXELWIDTH8:
957 1074 s->cirrus_blt_pixelwidth = 1;
... ... @@ -983,26 +1100,34 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
983 1100 goto bitblt_ignore;
984 1101 }
985 1102  
986   - if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
987   - s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
988   - s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
989   - s->cirrus_rop = cirrus_get_bkwd_rop_handler(blt_rop);
  1103 + if ((s->gr[0x33] & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
  1104 + (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
  1105 + CIRRUS_BLTMODE_TRANSPARENTCOMP |
  1106 + CIRRUS_BLTMODE_PATTERNCOPY |
  1107 + CIRRUS_BLTMODE_COLOREXPAND)) ==
  1108 + (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
  1109 + cirrus_bitblt_solidfill(s);
990 1110 } else {
991   - s->cirrus_rop = cirrus_get_fwd_rop_handler(blt_rop);
  1111 + if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
  1112 + s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
  1113 + s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
  1114 + s->cirrus_rop = cirrus_get_bkwd_rop_handler(blt_rop);
  1115 + } else {
  1116 + s->cirrus_rop = cirrus_get_fwd_rop_handler(blt_rop);
  1117 + }
  1118 +
  1119 + // setup bitblt engine.
  1120 + if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
  1121 + if (!cirrus_bitblt_cputovideo(s))
  1122 + goto bitblt_ignore;
  1123 + } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
  1124 + if (!cirrus_bitblt_videotocpu(s))
  1125 + goto bitblt_ignore;
  1126 + } else {
  1127 + if (!cirrus_bitblt_videotovideo(s))
  1128 + goto bitblt_ignore;
  1129 + }
992 1130 }
993   -
994   - // setup bitblt engine.
995   - if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
996   - if (!cirrus_bitblt_cputovideo(s))
997   - goto bitblt_ignore;
998   - } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
999   - if (!cirrus_bitblt_videotocpu(s))
1000   - goto bitblt_ignore;
1001   - } else {
1002   - if (!cirrus_bitblt_videotovideo(s))
1003   - goto bitblt_ignore;
1004   - }
1005   -
1006 1131 return;
1007 1132 bitblt_ignore:;
1008 1133 cirrus_bitblt_reset(s);
... ... @@ -1325,11 +1450,9 @@ cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1325 1450 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1326 1451 {
1327 1452 *reg_value = 0xff;
1328   - if (s->cirrus_hidden_dac_lockindex < 5) {
1329   - if (s->cirrus_hidden_dac_lockindex == 4) {
1330   - *reg_value = s->cirrus_hidden_dac_data;
1331   - }
1332   - s->cirrus_hidden_dac_lockindex++;
  1453 + if (++s->cirrus_hidden_dac_lockindex == 5) {
  1454 + *reg_value = s->cirrus_hidden_dac_data;
  1455 + s->cirrus_hidden_dac_lockindex = 0;
1333 1456 }
1334 1457 }
1335 1458  
... ... @@ -1337,7 +1460,7 @@ static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1337 1460 {
1338 1461 if (s->cirrus_hidden_dac_lockindex == 4) {
1339 1462 s->cirrus_hidden_dac_data = reg_value;
1340   -#ifdef DEBUG_CIRRUS
  1463 +#if defined(DEBUG_CIRRUS)
1341 1464 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1342 1465 #endif
1343 1466 }
... ... @@ -1468,6 +1591,7 @@ cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1468 1591 case 0x2d: // BLT SRC ADDR 0x00ff00
1469 1592 case 0x30: // BLT MODE
1470 1593 case 0x32: // RASTER OP
  1594 + case 0x33: // BLT MODEEXT
1471 1595 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1472 1596 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1473 1597 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
... ... @@ -1703,6 +1827,9 @@ static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1703 1827 case CIRRUS_MMIO_BLTROP:
1704 1828 cirrus_hook_read_gr(s, 0x32, &value);
1705 1829 break;
  1830 + case CIRRUS_MMIO_BLTMODEEXT:
  1831 + cirrus_hook_read_gr(s, 0x33, &value);
  1832 + break;
1706 1833 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1707 1834 cirrus_hook_read_gr(s, 0x34, &value);
1708 1835 break;
... ... @@ -1810,6 +1937,9 @@ static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1810 1937 case CIRRUS_MMIO_BLTROP:
1811 1938 cirrus_hook_write_gr(s, 0x32, value);
1812 1939 break;
  1940 + case CIRRUS_MMIO_BLTMODEEXT:
  1941 + cirrus_hook_write_gr(s, 0x33, value);
  1942 + break;
1813 1943 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1814 1944 cirrus_hook_write_gr(s, 0x34, value);
1815 1945 break;
... ... @@ -2592,7 +2722,7 @@ static void cirrus_init_common(CirrusVGAState * s)
2592 2722 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
2593 2723 s->sr[0x1F] = 0x22; // MemClock
2594 2724  
2595   - s->cr[0x27] = CIRRUS_ID_CLGD5430;
  2725 + s->cr[0x27] = CIRRUS_ID;
2596 2726  
2597 2727 s->cirrus_hidden_dac_lockindex = 5;
2598 2728 s->cirrus_hidden_dac_data = 0;
... ... @@ -2670,8 +2800,8 @@ void pci_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
2670 2800 pci_conf = d->dev.config;
2671 2801 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
2672 2802 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
2673   - pci_conf[0x02] = (uint8_t) (PCI_DEVICE_CLGD5430 & 0xff);
2674   - pci_conf[0x03] = (uint8_t) (PCI_DEVICE_CLGD5430 >> 8);
  2803 + pci_conf[0x02] = (uint8_t) (PCI_DEVICE_ID & 0xff);
  2804 + pci_conf[0x03] = (uint8_t) (PCI_DEVICE_ID >> 8);
2675 2805 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
2676 2806 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
2677 2807 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
... ... @@ -2689,8 +2819,10 @@ void pci_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
2689 2819 /* memory #1 memory-mapped I/O */
2690 2820 /* XXX: s->vram_size must be a power of two */
2691 2821 pci_register_io_region((PCIDevice *)d, 0, s->vram_size,
2692   - PCI_ADDRESS_SPACE_MEM, cirrus_pci_lfb_map);
2693   - pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
2694   - PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
  2822 + PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
  2823 + if (CIRRUS_ID == CIRRUS_ID_CLGD5446) {
  2824 + pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
  2825 + PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
  2826 + }
2695 2827 /* XXX: ROM BIOS */
2696 2828 }
... ...