Commit a20e31dcf0260ced84729ebab39c0181ae1966d7
1 parent
002bac8e
Use a common constant for temp_buf size
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4176 c046a42c-6fe2-441c-8c8c-71466251a162
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4 additions
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2 deletions
cpu-defs.h
| @@ -132,6 +132,7 @@ typedef struct CPUTLBEntry { | @@ -132,6 +132,7 @@ typedef struct CPUTLBEntry { | ||
| 132 | sizeof(target_phys_addr_t))]; | 132 | sizeof(target_phys_addr_t))]; |
| 133 | } CPUTLBEntry; | 133 | } CPUTLBEntry; |
| 134 | 134 | ||
| 135 | +#define CPU_TEMP_BUF_NLONGS 128 | ||
| 135 | #define CPU_COMMON \ | 136 | #define CPU_COMMON \ |
| 136 | struct TranslationBlock *current_tb; /* currently executing TB */ \ | 137 | struct TranslationBlock *current_tb; /* currently executing TB */ \ |
| 137 | /* soft mmu support */ \ | 138 | /* soft mmu support */ \ |
| @@ -145,7 +146,8 @@ typedef struct CPUTLBEntry { | @@ -145,7 +146,8 @@ typedef struct CPUTLBEntry { | ||
| 145 | /* The meaning of the MMU modes is defined in the target code. */ \ | 146 | /* The meaning of the MMU modes is defined in the target code. */ \ |
| 146 | CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ | 147 | CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
| 147 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ | 148 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ |
| 148 | - long temp_buf[128]; /* buffer for temporaries in the code generator */ \ | 149 | + /* buffer for temporaries in the code generator */ \ |
| 150 | + long temp_buf[CPU_TEMP_BUF_NLONGS]; \ | ||
| 149 | \ | 151 | \ |
| 150 | /* from this point: preserved by CPU reset */ \ | 152 | /* from this point: preserved by CPU reset */ \ |
| 151 | /* ice debug support */ \ | 153 | /* ice debug support */ \ |
translate-all.c
| @@ -85,7 +85,7 @@ void cpu_gen_init(void) | @@ -85,7 +85,7 @@ void cpu_gen_init(void) | ||
| 85 | { | 85 | { |
| 86 | tcg_context_init(&tcg_ctx); | 86 | tcg_context_init(&tcg_ctx); |
| 87 | tcg_set_frame(&tcg_ctx, TCG_AREG0, offsetof(CPUState, temp_buf), | 87 | tcg_set_frame(&tcg_ctx, TCG_AREG0, offsetof(CPUState, temp_buf), |
| 88 | - 128 * sizeof(long)); | 88 | + CPU_TEMP_BUF_NLONGS * sizeof(long)); |
| 89 | } | 89 | } |
| 90 | 90 | ||
| 91 | /* return non zero if the very first instruction is invalid so that | 91 | /* return non zero if the very first instruction is invalid so that |