Commit 9e85e9bdcf473f2e28072602fff7dc96f9025f6d
1 parent
8632fb9a
alpha: fix lit sign
according to the alpha arch reference, the literal field of an operate instruction is unsigned: If bit <12> of the instruction is 1, an 8-bit zero-extended literal constant is formed by bits <20:13> of the instruction. The l teral is interpreted as a positive integer bet ween 0 and 255 and is zero-extended to 64 bits. This patch fixes the mis-interpretation of the literal field. (Tristan Gingold) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5211 c046a42c-6fe2-441c-8c8c-71466251a162
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3 additions
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3 deletions
target-alpha/translate.c
| @@ -351,7 +351,7 @@ static always_inline void gen_fbcond (DisasContext *ctx, | @@ -351,7 +351,7 @@ static always_inline void gen_fbcond (DisasContext *ctx, | ||
| 351 | 351 | ||
| 352 | static always_inline void gen_arith2 (DisasContext *ctx, | 352 | static always_inline void gen_arith2 (DisasContext *ctx, |
| 353 | void (*gen_arith_op)(void), | 353 | void (*gen_arith_op)(void), |
| 354 | - int rb, int rc, int islit, int8_t lit) | 354 | + int rb, int rc, int islit, uint8_t lit) |
| 355 | { | 355 | { |
| 356 | if (islit) | 356 | if (islit) |
| 357 | tcg_gen_movi_i64(cpu_T[0], lit); | 357 | tcg_gen_movi_i64(cpu_T[0], lit); |
| @@ -367,7 +367,7 @@ static always_inline void gen_arith2 (DisasContext *ctx, | @@ -367,7 +367,7 @@ static always_inline void gen_arith2 (DisasContext *ctx, | ||
| 367 | static always_inline void gen_arith3 (DisasContext *ctx, | 367 | static always_inline void gen_arith3 (DisasContext *ctx, |
| 368 | void (*gen_arith_op)(void), | 368 | void (*gen_arith_op)(void), |
| 369 | int ra, int rb, int rc, | 369 | int ra, int rb, int rc, |
| 370 | - int islit, int8_t lit) | 370 | + int islit, uint8_t lit) |
| 371 | { | 371 | { |
| 372 | if (ra != 31) | 372 | if (ra != 31) |
| 373 | tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); | 373 | tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); |
| @@ -387,7 +387,7 @@ static always_inline void gen_arith3 (DisasContext *ctx, | @@ -387,7 +387,7 @@ static always_inline void gen_arith3 (DisasContext *ctx, | ||
| 387 | static always_inline void gen_cmov (DisasContext *ctx, | 387 | static always_inline void gen_cmov (DisasContext *ctx, |
| 388 | void (*gen_test_op)(void), | 388 | void (*gen_test_op)(void), |
| 389 | int ra, int rb, int rc, | 389 | int ra, int rb, int rc, |
| 390 | - int islit, int8_t lit) | 390 | + int islit, uint8_t lit) |
| 391 | { | 391 | { |
| 392 | if (ra != 31) | 392 | if (ra != 31) |
| 393 | tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); | 393 | tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); |