Commit 9d1d106a3d95ada648703e871975897c1cf05383
1 parent
ae022501
unaligned load fix (Ralf Baechle)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1471 c046a42c-6fe2-441c-8c8c-71466251a162
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target-mips/translate.c
| @@ -329,6 +329,7 @@ static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt, | @@ -329,6 +329,7 @@ static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt, | ||
| 329 | opn = "lbu"; | 329 | opn = "lbu"; |
| 330 | break; | 330 | break; |
| 331 | case OPC_LWL: | 331 | case OPC_LWL: |
| 332 | + GEN_LOAD_REG_TN(T1, rt); | ||
| 332 | op_ldst(lwl); | 333 | op_ldst(lwl); |
| 333 | GEN_STORE_TN_REG(rt, T0); | 334 | GEN_STORE_TN_REG(rt, T0); |
| 334 | opn = "lwl"; | 335 | opn = "lwl"; |
| @@ -339,6 +340,7 @@ static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt, | @@ -339,6 +340,7 @@ static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt, | ||
| 339 | opn = "swr"; | 340 | opn = "swr"; |
| 340 | break; | 341 | break; |
| 341 | case OPC_LWR: | 342 | case OPC_LWR: |
| 343 | + GEN_LOAD_REG_TN(T1, rt); | ||
| 342 | op_ldst(lwr); | 344 | op_ldst(lwr); |
| 343 | GEN_STORE_TN_REG(rt, T0); | 345 | GEN_STORE_TN_REG(rt, T0); |
| 344 | opn = "lwr"; | 346 | opn = "lwr"; |