Commit 9c6c6662d1f95a098c764adf8d5d2ea0f23f1b30
1 parent
ba28189b
Simplify some constant loads
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4383 c046a42c-6fe2-441c-8c8c-71466251a162
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14 additions
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17 deletions
target-sparc/translate.c
| ... | ... | @@ -1909,8 +1909,7 @@ static void disas_sparc_insn(DisasContext * dc) |
| 1909 | 1909 | case 0x4: /* SETHI */ |
| 1910 | 1910 | if (rd) { // nop |
| 1911 | 1911 | uint32_t value = GET_FIELD(insn, 10, 31); |
| 1912 | - tcg_gen_movi_tl(cpu_dst, value << 10); | |
| 1913 | - gen_movl_TN_reg(rd, cpu_dst); | |
| 1912 | + gen_movl_TN_reg(rd, tcg_const_tl(value << 10)); | |
| 1914 | 1913 | } |
| 1915 | 1914 | break; |
| 1916 | 1915 | case 0x0: /* UNIMPL */ |
| ... | ... | @@ -2015,8 +2014,7 @@ static void disas_sparc_insn(DisasContext * dc) |
| 2015 | 2014 | } |
| 2016 | 2015 | break; |
| 2017 | 2016 | case 0x5: /* V9 rdpc */ |
| 2018 | - tcg_gen_movi_tl(cpu_dst, dc->pc); | |
| 2019 | - gen_movl_TN_reg(rd, cpu_dst); | |
| 2017 | + gen_movl_TN_reg(rd, tcg_const_tl(dc->pc)); | |
| 2020 | 2018 | break; |
| 2021 | 2019 | case 0x6: /* V9 rdfprs */ |
| 2022 | 2020 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs)); |
| ... | ... | @@ -2821,27 +2819,29 @@ static void disas_sparc_insn(DisasContext * dc) |
| 2821 | 2819 | // or %g0, x, y -> mov T0, x; mov y, T0 |
| 2822 | 2820 | if (IS_IMM) { /* immediate */ |
| 2823 | 2821 | rs2 = GET_FIELDs(insn, 19, 31); |
| 2824 | - tcg_gen_movi_tl(cpu_dst, (int)rs2); | |
| 2822 | + gen_movl_TN_reg(rd, tcg_const_tl((int)rs2)); | |
| 2825 | 2823 | } else { /* register */ |
| 2826 | 2824 | rs2 = GET_FIELD(insn, 27, 31); |
| 2827 | 2825 | gen_movl_reg_TN(rs2, cpu_dst); |
| 2826 | + gen_movl_TN_reg(rd, cpu_dst); | |
| 2828 | 2827 | } |
| 2829 | 2828 | } else { |
| 2830 | 2829 | cpu_src1 = get_src1(insn, cpu_src1); |
| 2831 | 2830 | if (IS_IMM) { /* immediate */ |
| 2832 | 2831 | rs2 = GET_FIELDs(insn, 19, 31); |
| 2833 | 2832 | tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2); |
| 2833 | + gen_movl_TN_reg(rd, cpu_dst); | |
| 2834 | 2834 | } else { /* register */ |
| 2835 | 2835 | // or x, %g0, y -> mov T1, x; mov y, T1 |
| 2836 | 2836 | rs2 = GET_FIELD(insn, 27, 31); |
| 2837 | 2837 | if (rs2 != 0) { |
| 2838 | 2838 | gen_movl_reg_TN(rs2, cpu_src2); |
| 2839 | 2839 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
| 2840 | + gen_movl_TN_reg(rd, cpu_dst); | |
| 2840 | 2841 | } else |
| 2841 | - tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
| 2842 | + gen_movl_TN_reg(rd, cpu_src1); | |
| 2842 | 2843 | } |
| 2843 | 2844 | } |
| 2844 | - gen_movl_TN_reg(rd, cpu_dst); | |
| 2845 | 2845 | #ifdef TARGET_SPARC64 |
| 2846 | 2846 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
| 2847 | 2847 | cpu_src1 = get_src1(insn, cpu_src1); |
| ... | ... | @@ -3405,12 +3405,12 @@ static void disas_sparc_insn(DisasContext * dc) |
| 3405 | 3405 | tcg_const_tl(0), l1); |
| 3406 | 3406 | if (IS_IMM) { /* immediate */ |
| 3407 | 3407 | rs2 = GET_FIELD_SPs(insn, 0, 10); |
| 3408 | - tcg_gen_movi_tl(cpu_dst, (int)rs2); | |
| 3408 | + gen_movl_TN_reg(rd, tcg_const_tl((int)rs2)); | |
| 3409 | 3409 | } else { |
| 3410 | 3410 | rs2 = GET_FIELD_SP(insn, 0, 4); |
| 3411 | - gen_movl_reg_TN(rs2, cpu_dst); | |
| 3411 | + gen_movl_reg_TN(rs2, cpu_tmp0); | |
| 3412 | + gen_movl_TN_reg(rd, cpu_tmp0); | |
| 3412 | 3413 | } |
| 3413 | - gen_movl_TN_reg(rd, cpu_dst); | |
| 3414 | 3414 | gen_set_label(l1); |
| 3415 | 3415 | break; |
| 3416 | 3416 | } |
| ... | ... | @@ -3438,12 +3438,12 @@ static void disas_sparc_insn(DisasContext * dc) |
| 3438 | 3438 | tcg_const_tl(0), l1); |
| 3439 | 3439 | if (IS_IMM) { /* immediate */ |
| 3440 | 3440 | rs2 = GET_FIELD_SPs(insn, 0, 9); |
| 3441 | - tcg_gen_movi_tl(cpu_dst, (int)rs2); | |
| 3441 | + gen_movl_TN_reg(rd, tcg_const_tl((int)rs2)); | |
| 3442 | 3442 | } else { |
| 3443 | 3443 | rs2 = GET_FIELD_SP(insn, 0, 4); |
| 3444 | - gen_movl_reg_TN(rs2, cpu_dst); | |
| 3444 | + gen_movl_reg_TN(rs2, cpu_tmp0); | |
| 3445 | + gen_movl_TN_reg(rd, cpu_tmp0); | |
| 3445 | 3446 | } |
| 3446 | - gen_movl_TN_reg(rd, cpu_dst); | |
| 3447 | 3447 | gen_set_label(l1); |
| 3448 | 3448 | break; |
| 3449 | 3449 | } |
| ... | ... | @@ -3900,10 +3900,7 @@ static void disas_sparc_insn(DisasContext * dc) |
| 3900 | 3900 | switch (xop) { |
| 3901 | 3901 | case 0x38: /* jmpl */ |
| 3902 | 3902 | { |
| 3903 | - if (rd != 0) { | |
| 3904 | - tcg_gen_movi_tl(cpu_tmp0, dc->pc); | |
| 3905 | - gen_movl_TN_reg(rd, cpu_tmp0); | |
| 3906 | - } | |
| 3903 | + gen_movl_TN_reg(rd, tcg_const_tl(dc->pc)); | |
| 3907 | 3904 | gen_mov_pc_npc(dc, cpu_cond); |
| 3908 | 3905 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3)); |
| 3909 | 3906 | tcg_gen_mov_tl(cpu_npc, cpu_dst); | ... | ... |