gwj / at91sam9263 · Commits

Commit 9a87ce9b9558fc0aacebfefdbcbd74fda8fc027f

Authored by blueswir1
1 parent e1dad5a6

Name the magic constants, fix a hex number without 0x 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3677 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 16 additions and 10 deletions
hw/slavio_intctl.c
  View file @9a87ce9
@@ -68,6 +68,12 @@ typedef struct SLAVIO_INTCTLState { @@ -68,6 +68,12 @@ typedef struct SLAVIO_INTCTLState {
68 #define INTCTLM_MAXADDR 0x13 68 #define INTCTLM_MAXADDR 0x13
69 #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1) 69 #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
70 #define INTCTLM_MASK 0x1f 70 #define INTCTLM_MASK 0x1f
  71 +#define MASTER_IRQ_MASK ~0x4fb2007f
  72 +#define MASTER_DISABLE 0x80000000
  73 +#define CPU_IRQ_MASK 0xfffe0000
  74 +#define CPU_IRQ_INT15_IN 0x0004000
  75 +#define CPU_IRQ_INT15_MASK 0x80000000
  76 +
71 static void slavio_check_interrupts(void *opaque); 77 static void slavio_check_interrupts(void *opaque);
72 78
73 // per-cpu interrupt controller 79 // per-cpu interrupt controller
@@ -103,15 +109,15 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint @@ -103,15 +109,15 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint
103 DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val); 109 DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
104 switch (saddr) { 110 switch (saddr) {
105 case 1: // clear pending softints 111 case 1: // clear pending softints
106 - if (val & 0x4000)  
107 - val |= 80000000;  
108 - val &= 0xfffe0000; 112 + if (val & CPU_IRQ_INT15_IN)
  113 + val |= CPU_IRQ_INT15_MASK;
  114 + val &= CPU_IRQ_MASK;
109 s->intreg_pending[cpu] &= ~val; 115 s->intreg_pending[cpu] &= ~val;
110 slavio_check_interrupts(s); 116 slavio_check_interrupts(s);
111 DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); 117 DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
112 break; 118 break;
113 case 2: // set softint 119 case 2: // set softint
114 - val &= 0xfffe0000; 120 + val &= CPU_IRQ_MASK;
115 s->intreg_pending[cpu] |= val; 121 s->intreg_pending[cpu] |= val;
116 slavio_check_interrupts(s); 122 slavio_check_interrupts(s);
117 DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); 123 DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
@@ -142,7 +148,7 @@ static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) @@ -142,7 +148,7 @@ static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
142 saddr = (addr & INTCTLM_MAXADDR) >> 2; 148 saddr = (addr & INTCTLM_MAXADDR) >> 2;
143 switch (saddr) { 149 switch (saddr) {
144 case 0: 150 case 0:
145 - ret = s->intregm_pending & 0x7fffffff; 151 + ret = s->intregm_pending & ~MASTER_DISABLE;
146 break; 152 break;
147 case 1: 153 case 1:
148 ret = s->intregm_disabled; 154 ret = s->intregm_disabled;
@@ -169,14 +175,14 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin @@ -169,14 +175,14 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin
169 switch (saddr) { 175 switch (saddr) {
170 case 2: // clear (enable) 176 case 2: // clear (enable)
171 // Force clear unused bits 177 // Force clear unused bits
172 - val &= ~0x4fb2007f; 178 + val &= MASTER_IRQ_MASK;
173 s->intregm_disabled &= ~val; 179 s->intregm_disabled &= ~val;
174 DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); 180 DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
175 slavio_check_interrupts(s); 181 slavio_check_interrupts(s);
176 break; 182 break;
177 case 3: // set (disable, clear pending) 183 case 3: // set (disable, clear pending)
178 // Force clear unused bits 184 // Force clear unused bits
179 - val &= ~0x4fb2007f; 185 + val &= MASTER_IRQ_MASK;
180 s->intregm_disabled |= val; 186 s->intregm_disabled |= val;
181 s->intregm_pending &= ~val; 187 s->intregm_pending &= ~val;
182 slavio_check_interrupts(s); 188 slavio_check_interrupts(s);
@@ -244,14 +250,14 @@ static void slavio_check_interrupts(void *opaque) @@ -244,14 +250,14 @@ static void slavio_check_interrupts(void *opaque)
244 DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled); 250 DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
245 for (i = 0; i < MAX_CPUS; i++) { 251 for (i = 0; i < MAX_CPUS; i++) {
246 pil_pending = 0; 252 pil_pending = 0;
247 - if (pending && !(s->intregm_disabled & 0x80000000) && 253 + if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
248 (i == s->target_cpu)) { 254 (i == s->target_cpu)) {
249 for (j = 0; j < 32; j++) { 255 for (j = 0; j < 32; j++) {
250 if (pending & (1 << j)) 256 if (pending & (1 << j))
251 pil_pending |= 1 << s->intbit_to_level[j]; 257 pil_pending |= 1 << s->intbit_to_level[j];
252 } 258 }
253 } 259 }
254 - pil_pending |= (s->intreg_pending[i] >> 16) & 0xfffe; 260 + pil_pending |= (s->intreg_pending[i] & CPU_IRQ_MASK) >> 16;
255 261
256 for (j = 0; j < MAX_PILS; j++) { 262 for (j = 0; j < MAX_PILS; j++) {
257 if (pil_pending & (1 << j)) { 263 if (pil_pending & (1 << j)) {
@@ -346,7 +352,7 @@ static void slavio_intctl_reset(void *opaque) @@ -346,7 +352,7 @@ static void slavio_intctl_reset(void *opaque)
346 for (i = 0; i < MAX_CPUS; i++) { 352 for (i = 0; i < MAX_CPUS; i++) {
347 s->intreg_pending[i] = 0; 353 s->intreg_pending[i] = 0;
348 } 354 }
349 - s->intregm_disabled = ~0xffb2007f; 355 + s->intregm_disabled = ~MASTER_IRQ_MASK;
350 s->intregm_pending = 0; 356 s->intregm_pending = 0;
351 s->target_cpu = 0; 357 s->target_cpu = 0;
352 slavio_check_interrupts(s); 358 slavio_check_interrupts(s);