gwj / at91sam9263 · Commits

Commit 9898128f55e46b695a3d39ac091356c1c296e9b4

Authored by ths
1 parent e9a9a081

Simplify branch likely handling. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2676 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 8 additions and 6 deletions
target-mips/translate.c
  View file @9898128
@@ -1455,12 +1455,11 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) @@ -1455,12 +1455,11 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
1455 gen_op_goto_tb1(TBPARAM(tb)); 1455 gen_op_goto_tb1(TBPARAM(tb));
1456 gen_op_save_pc(dest); 1456 gen_op_save_pc(dest);
1457 gen_op_set_T0((long)tb + n); 1457 gen_op_set_T0((long)tb + n);
1458 - gen_op_exit_tb();  
1459 } else { 1458 } else {
1460 gen_op_save_pc(dest); 1459 gen_op_save_pc(dest);
1461 - gen_op_set_T0(0);  
1462 - gen_op_exit_tb(); 1460 + gen_op_reset_T0();
1463 } 1461 }
  1462 + gen_op_exit_tb();
1464 } 1463 }
1465 1464
1466 /* Branches (before delay slot) */ 1465 /* Branches (before delay slot) */
@@ -1565,18 +1564,21 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, @@ -1565,18 +1564,21 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1565 case OPC_BLTZAL: /* 0 < 0 */ 1564 case OPC_BLTZAL: /* 0 < 0 */
1566 gen_op_set_T0(ctx->pc + 8); 1565 gen_op_set_T0(ctx->pc + 8);
1567 gen_op_store_T0_gpr(31); 1566 gen_op_store_T0_gpr(31);
  1567 + MIPS_DEBUG("bnever and link");
1568 return; 1568 return;
1569 case OPC_BLTZALL: /* 0 < 0 likely */ 1569 case OPC_BLTZALL: /* 0 < 0 likely */
1570 gen_op_set_T0(ctx->pc + 8); 1570 gen_op_set_T0(ctx->pc + 8);
1571 gen_op_store_T0_gpr(31); 1571 gen_op_store_T0_gpr(31);
1572 - gen_goto_tb(ctx, 0, ctx->pc + 8); 1572 + /* Skip the instruction in the delay slot */
  1573 + MIPS_DEBUG("bnever, link and skip");
  1574 + ctx->pc += 4;
1573 return; 1575 return;
1574 case OPC_BNEL: /* rx != rx likely */ 1576 case OPC_BNEL: /* rx != rx likely */
1575 case OPC_BGTZL: /* 0 > 0 likely */ 1577 case OPC_BGTZL: /* 0 > 0 likely */
1576 case OPC_BLTZL: /* 0 < 0 likely */ 1578 case OPC_BLTZL: /* 0 < 0 likely */
1577 /* Skip the instruction in the delay slot */ 1579 /* Skip the instruction in the delay slot */
1578 MIPS_DEBUG("bnever and skip"); 1580 MIPS_DEBUG("bnever and skip");
1579 - gen_goto_tb(ctx, 0, ctx->pc + 8); 1581 + ctx->pc += 4;
1580 return; 1582 return;
1581 case OPC_J: 1583 case OPC_J:
1582 ctx->hflags |= MIPS_HFLAG_B; 1584 ctx->hflags |= MIPS_HFLAG_B;
@@ -5275,7 +5277,7 @@ done_generating: @@ -5275,7 +5277,7 @@ done_generating:
5275 #endif 5277 #endif
5276 if (loglevel & CPU_LOG_TB_IN_ASM) { 5278 if (loglevel & CPU_LOG_TB_IN_ASM) {
5277 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); 5279 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
5278 - target_disas(logfile, pc_start, ctx.pc - pc_start, 0); 5280 + target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
5279 fprintf(logfile, "\n"); 5281 fprintf(logfile, "\n");
5280 } 5282 }
5281 if (loglevel & CPU_LOG_TB_OP) { 5283 if (loglevel & CPU_LOG_TB_OP) {