Commit 985a19d6d1d7ab3705bf42698cc95abfbbfa24f8

Authored by bellard
1 parent 3f5dcc34

PowerPC merge (Jocelyn Mayer)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@566 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc/op.c
@@ -453,13 +453,6 @@ PPC_OP(reset_scrfx) @@ -453,13 +453,6 @@ PPC_OP(reset_scrfx)
453 RETURN(); 453 RETURN();
454 } 454 }
455 455
456 -/* Set reservation */  
457 -PPC_OP(set_reservation)  
458 -{  
459 - regs->reserve = T0 & ~0x03;  
460 - RETURN();  
461 -}  
462 -  
463 /* crf operations */ 456 /* crf operations */
464 PPC_OP(getbit_T0) 457 PPC_OP(getbit_T0)
465 { 458 {
target-ppc/op_helper.c
@@ -349,9 +349,13 @@ void do_fnabs (void) @@ -349,9 +349,13 @@ void do_fnabs (void)
349 } 349 }
350 350
351 /* Instruction cache invalidation helper */ 351 /* Instruction cache invalidation helper */
  352 +#define ICACHE_LINE_SIZE 32
  353 +
352 void do_icbi (void) 354 void do_icbi (void)
353 { 355 {
354 - // tb_invalidate_page(T0); 356 + /* Invalidate one cache line */
  357 + T0 &= ~(ICACHE_LINE_SIZE - 1);
  358 + tb_invalidate_page_range(T0, T0 + ICACHE_LINE_SIZE);
355 } 359 }
356 360
357 /* TLB invalidation helpers */ 361 /* TLB invalidation helpers */
target-ppc/op_mem.h
@@ -134,6 +134,19 @@ PPC_OP(glue(glue(l, name), MEMSUFFIX)) \ @@ -134,6 +134,19 @@ PPC_OP(glue(glue(l, name), MEMSUFFIX)) \
134 PPC_LDF_OP(fd, ldfq); 134 PPC_LDF_OP(fd, ldfq);
135 PPC_LDF_OP(fs, ldfl); 135 PPC_LDF_OP(fs, ldfl);
136 136
  137 +/* Load and set reservation */
  138 +PPC_OP(glue(lwarx, MEMSUFFIX))
  139 +{
  140 + if (T0 & 0x03) {
  141 + do_queue_exception(EXCP_ALIGN);
  142 + do_process_exceptions();
  143 + } else {
  144 + glue(ldl, MEMSUFFIX)((void *)T0);
  145 + regs->reserve = T0 & ~0x03;
  146 + }
  147 + RETURN();
  148 +}
  149 +
137 /* Store with reservation */ 150 /* Store with reservation */
138 PPC_OP(glue(stwcx, MEMSUFFIX)) 151 PPC_OP(glue(stwcx, MEMSUFFIX))
139 { 152 {
target-ppc/translate.c
@@ -1302,8 +1302,14 @@ GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM) @@ -1302,8 +1302,14 @@ GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1302 1302
1303 /* lwarx */ 1303 /* lwarx */
1304 #if defined(CONFIG_USER_ONLY) 1304 #if defined(CONFIG_USER_ONLY)
  1305 +#define op_lwarx() gen_op_lwarx_raw()
1305 #define op_stwcx() gen_op_stwcx_raw() 1306 #define op_stwcx() gen_op_stwcx_raw()
1306 #else 1307 #else
  1308 +#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
  1309 +static GenOpFunc *gen_op_lwarx[] = {
  1310 + &gen_op_lwarx_user,
  1311 + &gen_op_lwarx_kernel,
  1312 +};
1307 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])() 1313 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1308 static GenOpFunc *gen_op_stwcx[] = { 1314 static GenOpFunc *gen_op_stwcx[] = {
1309 &gen_op_stwcx_user, 1315 &gen_op_stwcx_user,
@@ -1320,9 +1326,8 @@ GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES) @@ -1320,9 +1326,8 @@ GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
1320 gen_op_load_gpr_T1(rB(ctx->opcode)); 1326 gen_op_load_gpr_T1(rB(ctx->opcode));
1321 gen_op_add(); 1327 gen_op_add();
1322 } 1328 }
1323 - op_ldst(lwz); 1329 + op_lwarx();
1324 gen_op_store_T1_gpr(rD(ctx->opcode)); 1330 gen_op_store_T1_gpr(rD(ctx->opcode));
1325 - gen_op_set_reservation();  
1326 } 1331 }
1327 1332
1328 /* stwcx. */ 1333 /* stwcx. */
@@ -3169,9 +3174,11 @@ int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, @@ -3169,9 +3174,11 @@ int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3169 while (lj <= j) 3174 while (lj <= j)
3170 gen_opc_instr_start[lj++] = 0; 3175 gen_opc_instr_start[lj++] = 0;
3171 tb->size = 0; 3176 tb->size = 0;
  3177 +#if 0
3172 if (loglevel > 0) { 3178 if (loglevel > 0) {
3173 page_dump(logfile); 3179 page_dump(logfile);
3174 } 3180 }
  3181 +#endif
3175 } else { 3182 } else {
3176 tb->size = (uint32_t)ctx.nip - pc_start; 3183 tb->size = (uint32_t)ctx.nip - pc_start;
3177 } 3184 }