gwj / at91sam9263 · Commits

Commit 981a2e99064ad52abf070d9e8d2a649535f0dd43

Authored by blueswir1
1 parent 8a93e02a

Improve iommu debugging, use register names 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3114 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 14 additions and 7 deletions
hw/iommu.c
  View file @981a2e9
@@ -100,7 +100,7 @@ static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr) @@ -100,7 +100,7 @@ static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
100 saddr = (addr - s->addr) >> 2; 100 saddr = (addr - s->addr) >> 2;
101 switch (saddr) { 101 switch (saddr) {
102 default: 102 default:
103 - DPRINTF("read reg[%d] = %x\n", saddr, s->regs[saddr]); 103 + DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
104 return s->regs[saddr]; 104 return s->regs[saddr];
105 break; 105 break;
106 } 106 }
@@ -113,7 +113,7 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val @@ -113,7 +113,7 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
113 target_phys_addr_t saddr; 113 target_phys_addr_t saddr;
114 114
115 saddr = (addr - s->addr) >> 2; 115 saddr = (addr - s->addr) >> 2;
116 - DPRINTF("write reg[%d] = %x\n", saddr, val); 116 + DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
117 switch (saddr) { 117 switch (saddr) {
118 case IOMMU_CTRL: 118 case IOMMU_CTRL:
119 switch (val & IOMMU_CTRL_RNGE) { 119 switch (val & IOMMU_CTRL_RNGE) {
@@ -143,7 +143,7 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val @@ -143,7 +143,7 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
143 s->iostart = 0xffffffff80000000ULL; 143 s->iostart = 0xffffffff80000000ULL;
144 break; 144 break;
145 } 145 }
146 - DPRINTF("iostart = %llx\n", s->iostart); 146 + DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
147 s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION); 147 s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
148 break; 148 break;
149 case IOMMU_BASE: 149 case IOMMU_BASE:
@@ -188,12 +188,19 @@ static CPUWriteMemoryFunc *iommu_mem_write[3] = { @@ -188,12 +188,19 @@ static CPUWriteMemoryFunc *iommu_mem_write[3] = {
188 188
189 static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr) 189 static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
190 { 190 {
191 - uint32_t iopte; 191 + uint32_t iopte, ret;
  192 +#ifdef DEBUG_IOMMU
  193 + target_phys_addr_t pa = addr;
  194 +#endif
192 195
193 - iopte = s->regs[1] << 4; 196 + iopte = s->regs[IOMMU_BASE] << 4;
194 addr &= ~s->iostart; 197 addr &= ~s->iostart;
195 iopte += (addr >> (PAGE_SHIFT - 2)) & ~3; 198 iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
196 - return ldl_phys(iopte); 199 + ret = ldl_phys(iopte);
  200 + DPRINTF("get flags addr " TARGET_FMT_plx " => pte %x, *ptes = %x\n", pa,
  201 + iopte, ret);
  202 +
  203 + return ret;
197 } 204 }
198 205
199 static target_phys_addr_t iommu_translate_pa(IOMMUState *s, 206 static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
@@ -271,7 +278,7 @@ static void iommu_reset(void *opaque) @@ -271,7 +278,7 @@ static void iommu_reset(void *opaque)
271 278
272 memset(s->regs, 0, IOMMU_NREGS * 4); 279 memset(s->regs, 0, IOMMU_NREGS * 4);
273 s->iostart = 0; 280 s->iostart = 0;
274 - s->regs[0] = IOMMU_VERSION; 281 + s->regs[IOMMU_CTRL] = IOMMU_VERSION;
275 } 282 }
276 283
277 void *iommu_init(target_phys_addr_t addr) 284 void *iommu_init(target_phys_addr_t addr)