gwj / at91sam9263 · Commits

Commit 97428a4d84a22795e0d9f1517677ec01cb1bede1

Authored by ths
1 parent dac93210

Fix exception handling cornercase for rdhwr. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2641 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 9 additions and 37 deletions
target-mips/op.c
  View file @97428a4
@@ -2126,7 +2126,7 @@ void op_deret (void) @@ -2126,7 +2126,7 @@ void op_deret (void)
2126 void op_rdhwr_cpunum(void) 2126 void op_rdhwr_cpunum(void)
2127 { 2127 {
2128 if (!(env->hflags & MIPS_HFLAG_UM) || 2128 if (!(env->hflags & MIPS_HFLAG_UM) ||
2129 - (env->CP0_HWREna & (1 << 0)) || 2129 + (env->CP0_HWREna & (1 << 0)) ||
2130 (env->CP0_Status & (1 << CP0St_CU0))) 2130 (env->CP0_Status & (1 << CP0St_CU0)))
2131 T0 = env->CP0_EBase & 0x3ff; 2131 T0 = env->CP0_EBase & 0x3ff;
2132 else 2132 else
@@ -2137,7 +2137,7 @@ void op_rdhwr_cpunum(void) @@ -2137,7 +2137,7 @@ void op_rdhwr_cpunum(void)
2137 void op_rdhwr_synci_step(void) 2137 void op_rdhwr_synci_step(void)
2138 { 2138 {
2139 if (!(env->hflags & MIPS_HFLAG_UM) || 2139 if (!(env->hflags & MIPS_HFLAG_UM) ||
2140 - (env->CP0_HWREna & (1 << 1)) || 2140 + (env->CP0_HWREna & (1 << 1)) ||
2141 (env->CP0_Status & (1 << CP0St_CU0))) 2141 (env->CP0_Status & (1 << CP0St_CU0)))
2142 T0 = env->SYNCI_Step; 2142 T0 = env->SYNCI_Step;
2143 else 2143 else
@@ -2148,7 +2148,7 @@ void op_rdhwr_synci_step(void) @@ -2148,7 +2148,7 @@ void op_rdhwr_synci_step(void)
2148 void op_rdhwr_cc(void) 2148 void op_rdhwr_cc(void)
2149 { 2149 {
2150 if (!(env->hflags & MIPS_HFLAG_UM) || 2150 if (!(env->hflags & MIPS_HFLAG_UM) ||
2151 - (env->CP0_HWREna & (1 << 2)) || 2151 + (env->CP0_HWREna & (1 << 2)) ||
2152 (env->CP0_Status & (1 << CP0St_CU0))) 2152 (env->CP0_Status & (1 << CP0St_CU0)))
2153 T0 = env->CP0_Count; 2153 T0 = env->CP0_Count;
2154 else 2154 else
@@ -2159,7 +2159,7 @@ void op_rdhwr_cc(void) @@ -2159,7 +2159,7 @@ void op_rdhwr_cc(void)
2159 void op_rdhwr_ccres(void) 2159 void op_rdhwr_ccres(void)
2160 { 2160 {
2161 if (!(env->hflags & MIPS_HFLAG_UM) || 2161 if (!(env->hflags & MIPS_HFLAG_UM) ||
2162 - (env->CP0_HWREna & (1 << 3)) || 2162 + (env->CP0_HWREna & (1 << 3)) ||
2163 (env->CP0_Status & (1 << CP0St_CU0))) 2163 (env->CP0_Status & (1 << CP0St_CU0)))
2164 T0 = env->CCRes; 2164 T0 = env->CCRes;
2165 else 2165 else
@@ -2167,28 +2167,6 @@ void op_rdhwr_ccres(void) @@ -2167,28 +2167,6 @@ void op_rdhwr_ccres(void)
2167 RETURN(); 2167 RETURN();
2168 } 2168 }
2169 2169
2170 -void op_rdhwr_unimpl30(void)  
2171 -{  
2172 - if (!(env->hflags & MIPS_HFLAG_UM) ||  
2173 - (env->CP0_HWREna & (1 << 30)) ||  
2174 - (env->CP0_Status & (1 << CP0St_CU0)))  
2175 - T0 = 0;  
2176 - else  
2177 - CALL_FROM_TB1(do_raise_exception, EXCP_RI);  
2178 - RETURN();  
2179 -}  
2180 -  
2181 -void op_rdhwr_unimpl31(void)  
2182 -{  
2183 - if (!(env->hflags & MIPS_HFLAG_UM) ||  
2184 - (env->CP0_HWREna & (1 << 31)) ||  
2185 - (env->CP0_Status & (1 << CP0St_CU0)))  
2186 - T0 = 0;  
2187 - else  
2188 - CALL_FROM_TB1(do_raise_exception, EXCP_RI);  
2189 - RETURN();  
2190 -}  
2191 -  
2192 void op_save_state (void) 2170 void op_save_state (void)
2193 { 2171 {
2194 env->hflags = PARAM1; 2172 env->hflags = PARAM1;
target-mips/translate.c
  View file @97428a4
@@ -4825,32 +4825,26 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -4825,32 +4825,26 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
4825 case OPC_RDHWR: 4825 case OPC_RDHWR:
4826 switch (rd) { 4826 switch (rd) {
4827 case 0: 4827 case 0:
  4828 + save_cpu_state(ctx, 1);
4828 gen_op_rdhwr_cpunum(); 4829 gen_op_rdhwr_cpunum();
4829 break; 4830 break;
4830 case 1: 4831 case 1:
  4832 + save_cpu_state(ctx, 1);
4831 gen_op_rdhwr_synci_step(); 4833 gen_op_rdhwr_synci_step();
4832 break; 4834 break;
4833 case 2: 4835 case 2:
  4836 + save_cpu_state(ctx, 1);
4834 gen_op_rdhwr_cc(); 4837 gen_op_rdhwr_cc();
4835 break; 4838 break;
4836 case 3: 4839 case 3:
  4840 + save_cpu_state(ctx, 1);
4837 gen_op_rdhwr_ccres(); 4841 gen_op_rdhwr_ccres();
4838 break; 4842 break;
4839 case 29: 4843 case 29:
4840 #if defined (CONFIG_USER_ONLY) 4844 #if defined (CONFIG_USER_ONLY)
4841 gen_op_tls_value (); 4845 gen_op_tls_value ();
4842 -#else  
4843 - generate_exception(ctx, EXCP_RI);  
4844 -#endif  
4845 - break;  
4846 - case 30:  
4847 - /* Implementation dependent */;  
4848 - gen_op_rdhwr_unimpl30();  
4849 - break;  
4850 - case 31:  
4851 - /* Implementation dependent */;  
4852 - gen_op_rdhwr_unimpl31();  
4853 break; 4846 break;
  4847 +#endif
4854 default: /* Invalid */ 4848 default: /* Invalid */
4855 MIPS_INVAL("rdhwr"); 4849 MIPS_INVAL("rdhwr");
4856 generate_exception(ctx, EXCP_RI); 4850 generate_exception(ctx, EXCP_RI);