Commit 970a87a6bb8dd0ac304a55aeed219e225fbbea38
1 parent
d8bc1fd0
new segment access
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@255 c046a42c-6fe2-441c-8c8c-71466251a162
Showing
3 changed files
with
14 additions
and
14 deletions
cpu-exec.c
... | ... | @@ -178,21 +178,21 @@ int cpu_exec(CPUState *env1) |
178 | 178 | /* we compute the CPU state. We assume it will not |
179 | 179 | change during the whole generated block. */ |
180 | 180 | #if defined(TARGET_I386) |
181 | - flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT; | |
182 | - flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT; | |
183 | - flags |= (((unsigned long)env->seg_cache[R_DS].base | | |
184 | - (unsigned long)env->seg_cache[R_ES].base | | |
185 | - (unsigned long)env->seg_cache[R_SS].base) != 0) << | |
181 | + flags = env->segs[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT; | |
182 | + flags |= env->segs[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT; | |
183 | + flags |= (((unsigned long)env->segs[R_DS].base | | |
184 | + (unsigned long)env->segs[R_ES].base | | |
185 | + (unsigned long)env->segs[R_SS].base) != 0) << | |
186 | 186 | GEN_FLAG_ADDSEG_SHIFT; |
187 | 187 | if (!(env->eflags & VM_MASK)) { |
188 | - flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT; | |
188 | + flags |= (env->segs[R_CS].selector & 3) << GEN_FLAG_CPL_SHIFT; | |
189 | 189 | } else { |
190 | 190 | /* NOTE: a dummy CPL is kept */ |
191 | 191 | flags |= (1 << GEN_FLAG_VM_SHIFT); |
192 | 192 | flags |= (3 << GEN_FLAG_CPL_SHIFT); |
193 | 193 | } |
194 | 194 | flags |= (env->eflags & (IOPL_MASK | TF_MASK)); |
195 | - cs_base = env->seg_cache[R_CS].base; | |
195 | + cs_base = env->segs[R_CS].base; | |
196 | 196 | pc = cs_base + env->eip; |
197 | 197 | #elif defined(TARGET_ARM) |
198 | 198 | flags = 0; |
... | ... | @@ -347,13 +347,13 @@ void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
347 | 347 | if (env->eflags & VM_MASK) { |
348 | 348 | SegmentCache *sc; |
349 | 349 | selector &= 0xffff; |
350 | - sc = &env->seg_cache[seg_reg]; | |
350 | + sc = &env->segs[seg_reg]; | |
351 | 351 | /* NOTE: in VM86 mode, limit and seg_32bit are never reloaded, |
352 | 352 | so we must load them here */ |
353 | 353 | sc->base = (void *)(selector << 4); |
354 | 354 | sc->limit = 0xffff; |
355 | 355 | sc->seg_32bit = 0; |
356 | - env->segs[seg_reg] = selector; | |
356 | + sc->selector = selector; | |
357 | 357 | } else { |
358 | 358 | load_seg(seg_reg, selector, 0); |
359 | 359 | } |
... | ... | @@ -426,7 +426,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
426 | 426 | return 0; |
427 | 427 | #if defined(TARGET_I386) |
428 | 428 | env->eip = found_pc - tb->cs_base; |
429 | - env->cr2 = address; | |
429 | + env->cr[2] = address; | |
430 | 430 | /* we restore the process signal mask as the sigreturn should |
431 | 431 | do it (XXX: use sigsetjmp) */ |
432 | 432 | sigprocmask(SIG_SETMASK, old_set, NULL); | ... | ... |
linux-user/main.c
... | ... | @@ -176,7 +176,7 @@ void cpu_loop(CPUX86State *env) |
176 | 176 | info.si_code = TARGET_SEGV_MAPERR; |
177 | 177 | else |
178 | 178 | info.si_code = TARGET_SEGV_ACCERR; |
179 | - info._sifields._sigfault._addr = env->cr2; | |
179 | + info._sifields._sigfault._addr = env->cr[2]; | |
180 | 180 | queue_signal(info.si_signo, &info); |
181 | 181 | break; |
182 | 182 | case EXCP00_DIVZ: |
... | ... | @@ -231,7 +231,7 @@ void cpu_loop(CPUX86State *env) |
231 | 231 | /* just indicate that signals should be handled asap */ |
232 | 232 | break; |
233 | 233 | default: |
234 | - pc = env->seg_cache[R_CS].base + env->eip; | |
234 | + pc = env->segs[R_CS].base + env->eip; | |
235 | 235 | fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", |
236 | 236 | (long)pc, trapnr); |
237 | 237 | abort(); | ... | ... |
ops_template.h
... | ... | @@ -828,7 +828,7 @@ void OPPROTO glue(glue(op_bsr, SUFFIX), _T0_cc)(void) |
828 | 828 | |
829 | 829 | #define STRING_SUFFIX _a32 |
830 | 830 | #define SI_ADDR (uint8_t *)A0 + ESI |
831 | -#define DI_ADDR env->seg_cache[R_ES].base + EDI | |
831 | +#define DI_ADDR env->segs[R_ES].base + EDI | |
832 | 832 | #define INC_SI() ESI += inc |
833 | 833 | #define INC_DI() EDI += inc |
834 | 834 | #define CX ECX |
... | ... | @@ -837,7 +837,7 @@ void OPPROTO glue(glue(op_bsr, SUFFIX), _T0_cc)(void) |
837 | 837 | |
838 | 838 | #define STRING_SUFFIX _a16 |
839 | 839 | #define SI_ADDR (uint8_t *)A0 + (ESI & 0xffff) |
840 | -#define DI_ADDR env->seg_cache[R_ES].base + (EDI & 0xffff) | |
840 | +#define DI_ADDR env->segs[R_ES].base + (EDI & 0xffff) | |
841 | 841 | #define INC_SI() ESI = (ESI & ~0xffff) | ((ESI + inc) & 0xffff) |
842 | 842 | #define INC_DI() EDI = (EDI & ~0xffff) | ((EDI + inc) & 0xffff) |
843 | 843 | #define CX (ECX & 0xffff) | ... | ... |