gwj / at91sam9263 · Commits

Commit 96e2fc41a94f190994dfb56d47d609a658bfe67c

Authored by aurel32
1 parent 380ce5ba

SH4: Use qemu_irq in timer emulation. 

        * hw/sh.h (tmu012_init): Accept qemu_irq, not intc_source.
        * hw/sh7750.c (sh7750_init): Pass qemu_irq to tmu012_init.
        * hw/sh_intc.c (sh_intc_set_irq): New.
        (sh_intc_init): Allocate irqs.
        * hw/sh_intc.h (struct intc_desc): New field irqs.
        * hw/sh_timer.c (sh_timer_state): Use qemu_irq, not intc_source.
        (sh_timer_update): Use qemu_set_irq, not sh_intc_toggle_source.
        (sh_timer_init, tmu012_init): Adjust.

(Vladimir Prus)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5768 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 5 changed files with 27 additions and 14 deletions
... ... @@ -28,8 +28,8 @@ int sh7750_register_io_device(struct SH7750State *s,
28 28 #define TMU012_FEAT_3CHAN (1 << 1)
29 29 #define TMU012_FEAT_EXTCLK (1 << 2)
30 30 void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
31   - struct intc_source *ch0_irq, struct intc_source *ch1_irq,
32   - struct intc_source *ch2_irq0, struct intc_source *ch2_irq1);
  31 + qemu_irq ch0_irq, qemu_irq ch1_irq,
  32 + qemu_irq ch2_irq0, qemu_irq ch2_irq1);
33 33  
34 34  
35 35 /* sh_serial.c */
... ...
hw/sh7750.c
  View file @96e2fc4
... ... @@ -678,10 +678,10 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
678 678 tmu012_init(0x1fd80000,
679 679 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
680 680 s->periph_freq,
681   - sh_intc_source(&s->intc, TMU0),
682   - sh_intc_source(&s->intc, TMU1),
683   - sh_intc_source(&s->intc, TMU2_TUNI),
684   - sh_intc_source(&s->intc, TMU2_TICPI));
  681 + s->intc.irqs[TMU0],
  682 + s->intc.irqs[TMU1],
  683 + s->intc.irqs[TMU2_TUNI],
  684 + s->intc.irqs[TMU2_TICPI]);
685 685  
686 686 if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
687 687 sh_intc_register_sources(&s->intc,
... ... @@ -700,8 +700,8 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
700 700 _INTC_ARRAY(vectors_tmu34),
701 701 NULL, 0);
702 702 tmu012_init(0x1e100000, 0, s->periph_freq,
703   - sh_intc_source(&s->intc, TMU3),
704   - sh_intc_source(&s->intc, TMU4),
  703 + s->intc.irqs[TMU3],
  704 + s->intc.irqs[TMU4],
705 705 NULL, NULL);
706 706 }
707 707  
... ...
hw/sh_intc.c
  View file @96e2fc4
... ... @@ -73,6 +73,14 @@ void sh_intc_toggle_source(struct intc_source *source,
73 73 }
74 74 }
75 75  
  76 +void sh_intc_set_irq (void *opaque, int n, int level)
  77 +{
  78 + struct intc_desc *desc = opaque;
  79 + struct intc_source *source = &(desc->sources[n]);
  80 +
  81 + sh_intc_toggle_source(source, 0, level ? 1 : -1);
  82 +}
  83 +
76 84 int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
77 85 {
78 86 unsigned int i;
... ... @@ -428,6 +436,8 @@ int sh_intc_init(struct intc_desc *desc,
428 436  
429 437 source->parent = desc;
430 438 }
  439 +
  440 + desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
431 441  
432 442 desc->iomemtype = cpu_register_io_memory(0, sh_intc_readfn,
433 443 sh_intc_writefn, desc);
... ...
hw/sh_intc.h
  View file @96e2fc4
1 1 #ifndef __SH_INTC_H__
2 2 #define __SH_INTC_H__
3 3  
  4 +#include "qemu-common.h"
  5 +#include "irq.h"
  6 +
4 7 typedef unsigned char intc_enum;
5 8  
6 9 struct intc_vect {
... ... @@ -43,13 +46,13 @@ struct intc_source {
43 46 };
44 47  
45 48 struct intc_desc {
  49 + qemu_irq *irqs;
46 50 struct intc_source *sources;
47 51 int nr_sources;
48 52 struct intc_mask_reg *mask_regs;
49 53 int nr_mask_regs;
50 54 struct intc_prio_reg *prio_regs;
51 55 int nr_prio_regs;
52   -
53 56 int iomemtype;
54 57 int pending; /* number of interrupt sources that has pending set */
55 58 };
... ...
hw/sh_timer.c
  View file @96e2fc4
... ... @@ -36,7 +36,7 @@ typedef struct {
36 36 int old_level;
37 37 int feat;
38 38 int enabled;
39   - struct intc_source *irq;
  39 + qemu_irq irq;
40 40 } sh_timer_state;
41 41  
42 42 /* Check all active timers, and schedule the next timer interrupt. */
... ... @@ -46,7 +46,7 @@ static void sh_timer_update(sh_timer_state *s)
46 46 int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
47 47  
48 48 if (new_level != s->old_level)
49   - sh_intc_toggle_source(s->irq, 0, new_level ? 1 : -1);
  49 + qemu_set_irq (s->irq, new_level);
50 50  
51 51 s->old_level = s->int_level;
52 52 s->int_level = new_level;
... ... @@ -185,7 +185,7 @@ static void sh_timer_tick(void *opaque)
185 185 sh_timer_update(s);
186 186 }
187 187  
188   -static void *sh_timer_init(uint32_t freq, int feat, struct intc_source *irq)
  188 +static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
189 189 {
190 190 sh_timer_state *s;
191 191 QEMUBH *bh;
... ... @@ -307,8 +307,8 @@ static CPUWriteMemoryFunc *tmu012_writefn[] = {
307 307 };
308 308  
309 309 void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
310   - struct intc_source *ch0_irq, struct intc_source *ch1_irq,
311   - struct intc_source *ch2_irq0, struct intc_source *ch2_irq1)
  310 + qemu_irq ch0_irq, qemu_irq ch1_irq,
  311 + qemu_irq ch2_irq0, qemu_irq ch2_irq1)
312 312 {
313 313 int iomemtype;
314 314 tmu012_state *s;
... ...