gwj / at91sam9263 · Commits

Commit 955a7dd5e857bdeb1d41893a5ac9c1e02c327382

Authored by balrog
1 parent ded9d295

ARM: fix smmul and smmla/smmls usage of registers (Mans Rullgard). 

This fixes the destination and accumulator registers for the smmul
and smmla instructions.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5913 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 3 additions and 3 deletions
target-arm/translate.c
  View file @955a7dd
... ... @@ -6507,8 +6507,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
6507 6507 tcg_gen_shri_i64(tmp64, tmp64, 32);
6508 6508 tmp = new_tmp();
6509 6509 tcg_gen_trunc_i64_i32(tmp, tmp64);
6510   - if (rn != 15) {
6511   - tmp2 = load_reg(s, rn);
  6510 + if (rd != 15) {
  6511 + tmp2 = load_reg(s, rd);
6512 6512 if (insn & (1 << 6)) {
6513 6513 tcg_gen_sub_i32(tmp, tmp, tmp2);
6514 6514 } else {
... ... @@ -6516,7 +6516,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
6516 6516 }
6517 6517 dead_tmp(tmp2);
6518 6518 }
6519   - store_reg(s, rd, tmp);
  6519 + store_reg(s, rn, tmp);
6520 6520 } else {
6521 6521 if (insn & (1 << 5))
6522 6522 gen_swap_half(tmp2);
... ...