gwj / at91sam9263 · Commits

Commit 9322a4bf0b735f4e75bca50671aba9693958be09

Authored by blueswir1
1 parent c48fcb47

Change handling of source register 1 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4134 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 36 additions and 31 deletions
target-sparc/translate.c
  View file @9322a4b
... ... @@ -1817,6 +1817,23 @@ static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1817 1817 }
1818 1818 #endif
1819 1819  
  1820 +static inline TCGv get_src1(unsigned int insn, TCGv def)
  1821 +{
  1822 + TCGv r_rs1 = def;
  1823 + unsigned int rs1;
  1824 +
  1825 + rs1 = GET_FIELD(insn, 13, 17);
  1826 + if (rs1 == 0)
  1827 + //r_rs1 = tcg_const_tl(0);
  1828 + tcg_gen_movi_tl(def, 0);
  1829 + else if (rs1 < 8)
  1830 + //r_rs1 = cpu_gregs[rs1];
  1831 + tcg_gen_mov_tl(def, cpu_gregs[rs1]);
  1832 + else
  1833 + tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
  1834 + return r_rs1;
  1835 +}
  1836 +
1820 1837 /* before an instruction, dc->pc must be static */
1821 1838 static void disas_sparc_insn(DisasContext * dc)
1822 1839 {
... ... @@ -1864,8 +1881,7 @@ static void disas_sparc_insn(DisasContext * dc)
1864 1881 (GET_FIELD_SP(insn, 20, 21) << 14);
1865 1882 target = sign_extend(target, 16);
1866 1883 target <<= 2;
1867   - rs1 = GET_FIELD(insn, 13, 17);
1868   - gen_movl_reg_TN(rs1, cpu_src1);
  1884 + cpu_src1 = get_src1(insn, cpu_src1);
1869 1885 do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1870 1886 goto jmp_insn;
1871 1887 }
... ... @@ -1939,8 +1955,7 @@ static void disas_sparc_insn(DisasContext * dc)
1939 1955 if (xop == 0x3a) { /* generate trap */
1940 1956 int cond;
1941 1957  
1942   - rs1 = GET_FIELD(insn, 13, 17);
1943   - gen_movl_reg_TN(rs1, cpu_src1);
  1958 + cpu_src1 = get_src1(insn, cpu_src1);
1944 1959 if (IS_IMM) {
1945 1960 rs2 = GET_FIELD(insn, 25, 31);
1946 1961 tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
... ... @@ -2637,8 +2652,7 @@ static void disas_sparc_insn(DisasContext * dc)
2637 2652  
2638 2653 l1 = gen_new_label();
2639 2654 cond = GET_FIELD_SP(insn, 14, 17);
2640   - rs1 = GET_FIELD(insn, 13, 17);
2641   - gen_movl_reg_TN(rs1, cpu_src1);
  2655 + cpu_src1 = get_src1(insn, cpu_src1);
2642 2656 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2643 2657 tcg_const_tl(0), l1);
2644 2658 gen_op_load_fpr_FT0(rs2);
... ... @@ -2650,8 +2664,7 @@ static void disas_sparc_insn(DisasContext * dc)
2650 2664  
2651 2665 l1 = gen_new_label();
2652 2666 cond = GET_FIELD_SP(insn, 14, 17);
2653   - rs1 = GET_FIELD(insn, 13, 17);
2654   - gen_movl_reg_TN(rs1, cpu_src1);
  2667 + cpu_src1 = get_src1(insn, cpu_src1);
2655 2668 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2656 2669 tcg_const_tl(0), l1);
2657 2670 gen_op_load_fpr_DT0(DFPREG(rs2));
... ... @@ -2664,8 +2677,7 @@ static void disas_sparc_insn(DisasContext * dc)
2664 2677  
2665 2678 l1 = gen_new_label();
2666 2679 cond = GET_FIELD_SP(insn, 14, 17);
2667   - rs1 = GET_FIELD(insn, 13, 17);
2668   - gen_movl_reg_TN(rs1, cpu_src1);
  2680 + cpu_src1 = get_src1(insn, cpu_src1);
2669 2681 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2670 2682 tcg_const_tl(0), l1);
2671 2683 gen_op_load_fpr_QT0(QFPREG(rs2));
... ... @@ -2848,7 +2860,7 @@ static void disas_sparc_insn(DisasContext * dc)
2848 2860 gen_movl_reg_TN(rs2, cpu_dst);
2849 2861 }
2850 2862 } else {
2851   - gen_movl_reg_TN(rs1, cpu_src1);
  2863 + cpu_src1 = get_src1(insn, cpu_src1);
2852 2864 if (IS_IMM) { /* immediate */
2853 2865 rs2 = GET_FIELDs(insn, 19, 31);
2854 2866 tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
... ... @@ -2865,8 +2877,7 @@ static void disas_sparc_insn(DisasContext * dc)
2865 2877 #endif
2866 2878 #ifdef TARGET_SPARC64
2867 2879 } else if (xop == 0x25) { /* sll, V9 sllx */
2868   - rs1 = GET_FIELD(insn, 13, 17);
2869   - gen_movl_reg_TN(rs1, cpu_src1);
  2880 + cpu_src1 = get_src1(insn, cpu_src1);
2870 2881 if (IS_IMM) { /* immediate */
2871 2882 rs2 = GET_FIELDs(insn, 20, 31);
2872 2883 if (insn & (1 << 12)) {
... ... @@ -2889,8 +2900,7 @@ static void disas_sparc_insn(DisasContext * dc)
2889 2900 }
2890 2901 gen_movl_TN_reg(rd, cpu_dst);
2891 2902 } else if (xop == 0x26) { /* srl, V9 srlx */
2892   - rs1 = GET_FIELD(insn, 13, 17);
2893   - gen_movl_reg_TN(rs1, cpu_src1);
  2903 + cpu_src1 = get_src1(insn, cpu_src1);
2894 2904 if (IS_IMM) { /* immediate */
2895 2905 rs2 = GET_FIELDs(insn, 20, 31);
2896 2906 if (insn & (1 << 12)) {
... ... @@ -2913,8 +2923,7 @@ static void disas_sparc_insn(DisasContext * dc)
2913 2923 }
2914 2924 gen_movl_TN_reg(rd, cpu_dst);
2915 2925 } else if (xop == 0x27) { /* sra, V9 srax */
2916   - rs1 = GET_FIELD(insn, 13, 17);
2917   - gen_movl_reg_TN(rs1, cpu_src1);
  2926 + cpu_src1 = get_src1(insn, cpu_src1);
2918 2927 if (IS_IMM) { /* immediate */
2919 2928 rs2 = GET_FIELDs(insn, 20, 31);
2920 2929 if (insn & (1 << 12)) {
... ... @@ -2939,8 +2948,7 @@ static void disas_sparc_insn(DisasContext * dc)
2939 2948 gen_movl_TN_reg(rd, cpu_dst);
2940 2949 #endif
2941 2950 } else if (xop < 0x36) {
2942   - rs1 = GET_FIELD(insn, 13, 17);
2943   - gen_movl_reg_TN(rs1, cpu_src1);
  2951 + cpu_src1 = get_src1(insn, cpu_src1);
2944 2952 if (IS_IMM) { /* immediate */
2945 2953 rs2 = GET_FIELDs(insn, 19, 31);
2946 2954 tcg_gen_movi_tl(cpu_src2, (int)rs2);
... ... @@ -3479,8 +3487,7 @@ static void disas_sparc_insn(DisasContext * dc)
3479 3487 int cond = GET_FIELD_SP(insn, 10, 12);
3480 3488 int l1;
3481 3489  
3482   - rs1 = GET_FIELD(insn, 13, 17);
3483   - gen_movl_reg_TN(rs1, cpu_src1);
  3490 + cpu_src1 = get_src1(insn, cpu_src1);
3484 3491  
3485 3492 l1 = gen_new_label();
3486 3493  
... ... @@ -3526,14 +3533,14 @@ static void disas_sparc_insn(DisasContext * dc)
3526 3533 // XXX
3527 3534 goto illegal_insn;
3528 3535 case 0x010: /* VIS I array8 */
3529   - gen_movl_reg_TN(rs1, cpu_src1);
  3536 + cpu_src1 = get_src1(insn, cpu_src1);
3530 3537 gen_movl_reg_TN(rs2, cpu_src2);
3531 3538 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3532 3539 cpu_src2);
3533 3540 gen_movl_TN_reg(rd, cpu_dst);
3534 3541 break;
3535 3542 case 0x012: /* VIS I array16 */
3536   - gen_movl_reg_TN(rs1, cpu_src1);
  3543 + cpu_src1 = get_src1(insn, cpu_src1);
3537 3544 gen_movl_reg_TN(rs2, cpu_src2);
3538 3545 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3539 3546 cpu_src2);
... ... @@ -3541,7 +3548,7 @@ static void disas_sparc_insn(DisasContext * dc)
3541 3548 gen_movl_TN_reg(rd, cpu_dst);
3542 3549 break;
3543 3550 case 0x014: /* VIS I array32 */
3544   - gen_movl_reg_TN(rs1, cpu_src1);
  3551 + cpu_src1 = get_src1(insn, cpu_src1);
3545 3552 gen_movl_reg_TN(rs2, cpu_src2);
3546 3553 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3547 3554 cpu_src2);
... ... @@ -3549,7 +3556,7 @@ static void disas_sparc_insn(DisasContext * dc)
3549 3556 gen_movl_TN_reg(rd, cpu_dst);
3550 3557 break;
3551 3558 case 0x018: /* VIS I alignaddr */
3552   - gen_movl_reg_TN(rs1, cpu_src1);
  3559 + cpu_src1 = get_src1(insn, cpu_src1);
3553 3560 gen_movl_reg_TN(rs2, cpu_src2);
3554 3561 tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3555 3562 cpu_src2);
... ... @@ -3914,9 +3921,8 @@ static void disas_sparc_insn(DisasContext * dc)
3914 3921 #endif
3915 3922 #ifdef TARGET_SPARC64
3916 3923 } else if (xop == 0x39) { /* V9 return */
3917   - rs1 = GET_FIELD(insn, 13, 17);
3918 3924 save_state(dc, cpu_cond);
3919   - gen_movl_reg_TN(rs1, cpu_src1);
  3925 + cpu_src1 = get_src1(insn, cpu_src1);
3920 3926 if (IS_IMM) { /* immediate */
3921 3927 rs2 = GET_FIELDs(insn, 19, 31);
3922 3928 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
... ... @@ -3939,8 +3945,7 @@ static void disas_sparc_insn(DisasContext * dc)
3939 3945 goto jmp_insn;
3940 3946 #endif
3941 3947 } else {
3942   - rs1 = GET_FIELD(insn, 13, 17);
3943   - gen_movl_reg_TN(rs1, cpu_src1);
  3948 + cpu_src1 = get_src1(insn, cpu_src1);
3944 3949 if (IS_IMM) { /* immediate */
3945 3950 rs2 = GET_FIELDs(insn, 19, 31);
3946 3951 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
... ... @@ -4028,9 +4033,9 @@ static void disas_sparc_insn(DisasContext * dc)
4028 4033 case 3: /* load/store instructions */
4029 4034 {
4030 4035 unsigned int xop = GET_FIELD(insn, 7, 12);
4031   - rs1 = GET_FIELD(insn, 13, 17);
  4036 +
4032 4037 save_state(dc, cpu_cond);
4033   - gen_movl_reg_TN(rs1, cpu_src1);
  4038 + cpu_src1 = get_src1(insn, cpu_src1);
4034 4039 if (xop == 0x3c || xop == 0x3e)
4035 4040 {
4036 4041 rs2 = GET_FIELD(insn, 27, 31);
... ...