gwj / at91sam9263 · Commits

Commit 92af06d216857de77bcadaf86cf9675cce9f1d3c

Authored by ths
1 parent 278ed7c3

Convert vr54xx multiply instructions to TCG. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4756 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 32 additions and 240 deletions
target-mips/helper.h
  View file @92af06d
... ... @@ -15,6 +15,21 @@ DEF_HELPER(void, do_dmult, (void))
15 15 DEF_HELPER(void, do_dmultu, (void))
16 16 #endif
17 17  
  18 +DEF_HELPER(void, do_muls, (void))
  19 +DEF_HELPER(void, do_mulsu, (void))
  20 +DEF_HELPER(void, do_macc, (void))
  21 +DEF_HELPER(void, do_maccu, (void))
  22 +DEF_HELPER(void, do_msac, (void))
  23 +DEF_HELPER(void, do_msacu, (void))
  24 +DEF_HELPER(void, do_mulhi, (void))
  25 +DEF_HELPER(void, do_mulhiu, (void))
  26 +DEF_HELPER(void, do_mulshi, (void))
  27 +DEF_HELPER(void, do_mulshiu, (void))
  28 +DEF_HELPER(void, do_macchi, (void))
  29 +DEF_HELPER(void, do_macchiu, (void))
  30 +DEF_HELPER(void, do_msachi, (void))
  31 +DEF_HELPER(void, do_msachiu, (void))
  32 +
18 33 /* CP0 helpers */
19 34 #ifndef CONFIG_USER_ONLY
20 35 DEF_HELPER(void, do_mfc0_mvpcontrol, (void))
... ...
target-mips/op.c
  View file @92af06d
... ... @@ -45,226 +45,3 @@
45 45 #include "op_mem.c"
46 46 #undef MEMSUFFIX
47 47 #endif
48   -
49   -/* 64 bits arithmetic */
50   -#if TARGET_LONG_BITS > HOST_LONG_BITS
51   -void op_madd (void)
52   -{
53   - CALL_FROM_TB0(do_madd);
54   - FORCE_RET();
55   -}
56   -
57   -void op_maddu (void)
58   -{
59   - CALL_FROM_TB0(do_maddu);
60   - FORCE_RET();
61   -}
62   -
63   -void op_msub (void)
64   -{
65   - CALL_FROM_TB0(do_msub);
66   - FORCE_RET();
67   -}
68   -
69   -void op_msubu (void)
70   -{
71   - CALL_FROM_TB0(do_msubu);
72   - FORCE_RET();
73   -}
74   -
75   -/* Multiplication variants of the vr54xx. */
76   -void op_muls (void)
77   -{
78   - CALL_FROM_TB0(do_muls);
79   - FORCE_RET();
80   -}
81   -
82   -void op_mulsu (void)
83   -{
84   - CALL_FROM_TB0(do_mulsu);
85   - FORCE_RET();
86   -}
87   -
88   -void op_macc (void)
89   -{
90   - CALL_FROM_TB0(do_macc);
91   - FORCE_RET();
92   -}
93   -
94   -void op_macchi (void)
95   -{
96   - CALL_FROM_TB0(do_macchi);
97   - FORCE_RET();
98   -}
99   -
100   -void op_maccu (void)
101   -{
102   - CALL_FROM_TB0(do_maccu);
103   - FORCE_RET();
104   -}
105   -void op_macchiu (void)
106   -{
107   - CALL_FROM_TB0(do_macchiu);
108   - FORCE_RET();
109   -}
110   -
111   -void op_msac (void)
112   -{
113   - CALL_FROM_TB0(do_msac);
114   - FORCE_RET();
115   -}
116   -
117   -void op_msachi (void)
118   -{
119   - CALL_FROM_TB0(do_msachi);
120   - FORCE_RET();
121   -}
122   -
123   -void op_msacu (void)
124   -{
125   - CALL_FROM_TB0(do_msacu);
126   - FORCE_RET();
127   -}
128   -
129   -void op_msachiu (void)
130   -{
131   - CALL_FROM_TB0(do_msachiu);
132   - FORCE_RET();
133   -}
134   -
135   -void op_mulhi (void)
136   -{
137   - CALL_FROM_TB0(do_mulhi);
138   - FORCE_RET();
139   -}
140   -
141   -void op_mulhiu (void)
142   -{
143   - CALL_FROM_TB0(do_mulhiu);
144   - FORCE_RET();
145   -}
146   -
147   -void op_mulshi (void)
148   -{
149   - CALL_FROM_TB0(do_mulshi);
150   - FORCE_RET();
151   -}
152   -
153   -void op_mulshiu (void)
154   -{
155   - CALL_FROM_TB0(do_mulshiu);
156   - FORCE_RET();
157   -}
158   -
159   -#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
160   -
161   -static always_inline uint64_t get_HILO (void)
162   -{
163   - return ((uint64_t)env->HI[env->current_tc][0] << 32) |
164   - ((uint64_t)(uint32_t)env->LO[env->current_tc][0]);
165   -}
166   -
167   -static always_inline void set_HILO (uint64_t HILO)
168   -{
169   - env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
170   - env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
171   -}
172   -
173   -static always_inline void set_HIT0_LO (uint64_t HILO)
174   -{
175   - env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
176   - T0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
177   -}
178   -
179   -static always_inline void set_HI_LOT0 (uint64_t HILO)
180   -{
181   - T0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
182   - env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
183   -}
184   -
185   -/* Multiplication variants of the vr54xx. */
186   -void op_muls (void)
187   -{
188   - set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
189   - FORCE_RET();
190   -}
191   -
192   -void op_mulsu (void)
193   -{
194   - set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
195   - FORCE_RET();
196   -}
197   -
198   -void op_macc (void)
199   -{
200   - set_HI_LOT0(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
201   - FORCE_RET();
202   -}
203   -
204   -void op_macchi (void)
205   -{
206   - set_HIT0_LO(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
207   - FORCE_RET();
208   -}
209   -
210   -void op_maccu (void)
211   -{
212   - set_HI_LOT0(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
213   - FORCE_RET();
214   -}
215   -
216   -void op_macchiu (void)
217   -{
218   - set_HIT0_LO(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
219   - FORCE_RET();
220   -}
221   -
222   -void op_msac (void)
223   -{
224   - set_HI_LOT0(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
225   - FORCE_RET();
226   -}
227   -
228   -void op_msachi (void)
229   -{
230   - set_HIT0_LO(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
231   - FORCE_RET();
232   -}
233   -
234   -void op_msacu (void)
235   -{
236   - set_HI_LOT0(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
237   - FORCE_RET();
238   -}
239   -
240   -void op_msachiu (void)
241   -{
242   - set_HIT0_LO(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
243   - FORCE_RET();
244   -}
245   -
246   -void op_mulhi (void)
247   -{
248   - set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
249   - FORCE_RET();
250   -}
251   -
252   -void op_mulhiu (void)
253   -{
254   - set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
255   - FORCE_RET();
256   -}
257   -
258   -void op_mulshi (void)
259   -{
260   - set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
261   - FORCE_RET();
262   -}
263   -
264   -void op_mulshiu (void)
265   -{
266   - set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
267   - FORCE_RET();
268   -}
269   -
270   -#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
... ...
target-mips/op_helper.c
  View file @92af06d
... ... @@ -168,10 +168,9 @@ void do_dclz (void)
168 168 #endif /* TARGET_MIPS64 */
169 169  
170 170 /* 64 bits arithmetic for 32 bits hosts */
171   -#if TARGET_LONG_BITS > HOST_LONG_BITS
172 171 static always_inline uint64_t get_HILO (void)
173 172 {
174   - return (env->HI[env->current_tc][0] << 32) | (uint32_t)env->LO[env->current_tc][0];
  173 + return ((uint64_t)(env->HI[env->current_tc][0]) << 32) | (uint32_t)env->LO[env->current_tc][0];
175 174 }
176 175  
177 176 static always_inline void set_HILO (uint64_t HILO)
... ... @@ -192,6 +191,7 @@ static always_inline void set_HI_LOT0 (uint64_t HILO)
192 191 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
193 192 }
194 193  
  194 +#if TARGET_LONG_BITS > HOST_LONG_BITS
195 195 void do_madd (void)
196 196 {
197 197 int64_t tmp;
... ... @@ -223,6 +223,7 @@ void do_msubu (void)
223 223 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
224 224 set_HILO(get_HILO() - tmp);
225 225 }
  226 +#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
226 227  
227 228 /* Multiplication variants of the vr54xx. */
228 229 void do_muls (void)
... ... @@ -294,7 +295,6 @@ void do_mulshiu (void)
294 295 {
295 296 set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
296 297 }
297   -#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
298 298  
299 299 #ifdef TARGET_MIPS64
300 300 void do_dmult (void)
... ...
target-mips/translate.c
  View file @92af06d
... ... @@ -2204,59 +2204,59 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
2204 2204  
2205 2205 switch (opc) {
2206 2206 case OPC_VR54XX_MULS:
2207   - gen_op_muls();
  2207 + tcg_gen_helper_0_0(do_muls);
2208 2208 opn = "muls";
2209 2209 break;
2210 2210 case OPC_VR54XX_MULSU:
2211   - gen_op_mulsu();
  2211 + tcg_gen_helper_0_0(do_mulsu);
2212 2212 opn = "mulsu";
2213 2213 break;
2214 2214 case OPC_VR54XX_MACC:
2215   - gen_op_macc();
  2215 + tcg_gen_helper_0_0(do_macc);
2216 2216 opn = "macc";
2217 2217 break;
2218 2218 case OPC_VR54XX_MACCU:
2219   - gen_op_maccu();
  2219 + tcg_gen_helper_0_0(do_maccu);
2220 2220 opn = "maccu";
2221 2221 break;
2222 2222 case OPC_VR54XX_MSAC:
2223   - gen_op_msac();
  2223 + tcg_gen_helper_0_0(do_msac);
2224 2224 opn = "msac";
2225 2225 break;
2226 2226 case OPC_VR54XX_MSACU:
2227   - gen_op_msacu();
  2227 + tcg_gen_helper_0_0(do_msacu);
2228 2228 opn = "msacu";
2229 2229 break;
2230 2230 case OPC_VR54XX_MULHI:
2231   - gen_op_mulhi();
  2231 + tcg_gen_helper_0_0(do_mulhi);
2232 2232 opn = "mulhi";
2233 2233 break;
2234 2234 case OPC_VR54XX_MULHIU:
2235   - gen_op_mulhiu();
  2235 + tcg_gen_helper_0_0(do_mulhiu);
2236 2236 opn = "mulhiu";
2237 2237 break;
2238 2238 case OPC_VR54XX_MULSHI:
2239   - gen_op_mulshi();
  2239 + tcg_gen_helper_0_0(do_mulshi);
2240 2240 opn = "mulshi";
2241 2241 break;
2242 2242 case OPC_VR54XX_MULSHIU:
2243   - gen_op_mulshiu();
  2243 + tcg_gen_helper_0_0(do_mulshiu);
2244 2244 opn = "mulshiu";
2245 2245 break;
2246 2246 case OPC_VR54XX_MACCHI:
2247   - gen_op_macchi();
  2247 + tcg_gen_helper_0_0(do_macchi);
2248 2248 opn = "macchi";
2249 2249 break;
2250 2250 case OPC_VR54XX_MACCHIU:
2251   - gen_op_macchiu();
  2251 + tcg_gen_helper_0_0(do_macchiu);
2252 2252 opn = "macchiu";
2253 2253 break;
2254 2254 case OPC_VR54XX_MSACHI:
2255   - gen_op_msachi();
  2255 + tcg_gen_helper_0_0(do_msachi);
2256 2256 opn = "msachi";
2257 2257 break;
2258 2258 case OPC_VR54XX_MSACHIU:
2259   - gen_op_msachiu();
  2259 + tcg_gen_helper_0_0(do_msachiu);
2260 2260 opn = "msachiu";
2261 2261 break;
2262 2262 default:
... ...