gwj / at91sam9263 · Commits

Commit 923e5e339f16d55109a75e3f99a2c668571cc58b

Authored by aurel32
1 parent 72fb7daa

qemu ppc uic: Order IRQ bit number as described in the UIC documentation. 

(Hollis Blanchard)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4273 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 24 additions and 23 deletions
hw/ppc405_uc.c
  View file @923e5e3
... ... @@ -2587,13 +2587,13 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
2587 2587 ppc405_dma_init(env, dma_irqs);
2588 2588 /* Serial ports */
2589 2589 if (serial_hds[0] != NULL) {
2590   - ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
  2590 + ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
2591 2591 }
2592 2592 if (serial_hds[1] != NULL) {
2593   - ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
  2593 + ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
2594 2594 }
2595 2595 /* IIC controller */
2596   - ppc405_i2c_init(env, mmio, 0x500, pic[29]);
  2596 + ppc405_i2c_init(env, mmio, 0x500, pic[2]);
2597 2597 /* GPIO */
2598 2598 ppc405_gpio_init(env, mmio, 0x700);
2599 2599 /* CPU control */
... ... @@ -2930,49 +2930,50 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
2930 2930 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2931 2931 *picp = pic;
2932 2932 /* SDRAM controller */
2933   - ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init);
  2933 + /* XXX 405EP has no ECC interrupt */
  2934 + ppc405_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
2934 2935 offset = 0;
2935 2936 for (i = 0; i < 2; i++)
2936 2937 offset += ram_sizes[i];
2937 2938 /* External bus controller */
2938 2939 ppc405_ebc_init(env);
2939 2940 /* DMA controller */
2940   - dma_irqs[0] = pic[26];
2941   - dma_irqs[1] = pic[25];
2942   - dma_irqs[2] = pic[24];
2943   - dma_irqs[3] = pic[23];
  2941 + dma_irqs[0] = pic[5];
  2942 + dma_irqs[1] = pic[6];
  2943 + dma_irqs[2] = pic[7];
  2944 + dma_irqs[3] = pic[8];
2944 2945 ppc405_dma_init(env, dma_irqs);
2945 2946 /* IIC controller */
2946   - ppc405_i2c_init(env, mmio, 0x500, pic[29]);
  2947 + ppc405_i2c_init(env, mmio, 0x500, pic[2]);
2947 2948 /* GPIO */
2948 2949 ppc405_gpio_init(env, mmio, 0x700);
2949 2950 /* Serial ports */
2950 2951 if (serial_hds[0] != NULL) {
2951   - ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
  2952 + ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
2952 2953 }
2953 2954 if (serial_hds[1] != NULL) {
2954   - ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
  2955 + ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
2955 2956 }
2956 2957 /* OCM */
2957 2958 ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]);
2958 2959 offset += 4096;
2959 2960 /* GPT */
2960   - gpt_irqs[0] = pic[12];
2961   - gpt_irqs[1] = pic[11];
2962   - gpt_irqs[2] = pic[10];
2963   - gpt_irqs[3] = pic[9];
2964   - gpt_irqs[4] = pic[8];
  2961 + gpt_irqs[0] = pic[19];
  2962 + gpt_irqs[1] = pic[20];
  2963 + gpt_irqs[2] = pic[21];
  2964 + gpt_irqs[3] = pic[22];
  2965 + gpt_irqs[4] = pic[23];
2965 2966 ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
2966 2967 /* PCI */
2967   - /* Uses pic[28], pic[15], pic[13] */
  2968 + /* Uses pic[3], pic[16], pic[18] */
2968 2969 /* MAL */
2969   - mal_irqs[0] = pic[20];
2970   - mal_irqs[1] = pic[19];
2971   - mal_irqs[2] = pic[18];
2972   - mal_irqs[3] = pic[17];
  2970 + mal_irqs[0] = pic[11];
  2971 + mal_irqs[1] = pic[12];
  2972 + mal_irqs[2] = pic[13];
  2973 + mal_irqs[3] = pic[14];
2973 2974 ppc405_mal_init(env, mal_irqs);
2974 2975 /* Ethernet */
2975   - /* Uses pic[22], pic[16], pic[14] */
  2976 + /* Uses pic[9], pic[15], pic[17] */
2976 2977 /* CPU control */
2977 2978 ppc405ep_cpc_init(env, clk_setup, sysclk);
2978 2979 *offsetp = offset;
... ...
hw/ppc4xx_devs.c
  View file @923e5e3
... ... @@ -365,7 +365,7 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
365 365 uint32_t mask, sr;
366 366  
367 367 uic = opaque;
368   - mask = 1 << irq_num;
  368 + mask = 1 << (31-irq_num);
369 369 #ifdef DEBUG_UIC
370 370 if (loglevel & CPU_LOG_INT) {
371 371 fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
... ...