gwj / at91sam9263 · Commits

Commit 923617a396249fcac8710048f9db76345246f999

Authored by ths
1 parent 4759513b

Improved debug output for the MIPS opcode decoder. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2801 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 77 additions and 85 deletions
target-mips/translate.c
  View file @923617a
... ... @@ -540,7 +540,7 @@ enum {
540 540 BS_EXCP = 3, /* We reached an exception condition */
541 541 };
542 542  
543   -#if defined MIPS_DEBUG_DISAS
  543 +#ifdef MIPS_DEBUG_DISAS
544 544 #define MIPS_DEBUG(fmt, args...) \
545 545 do { \
546 546 if (loglevel & CPU_LOG_TB_IN_ASM) { \
... ... @@ -710,7 +710,7 @@ OP_ST_TABLE(uxc1);
710 710 static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
711 711 int base, int16_t offset)
712 712 {
713   - const char *opn = "unk";
  713 + const char *opn = "ldst";
714 714  
715 715 if (base == 0) {
716 716 GEN_LOAD_IMM_TN(T0, offset);
... ... @@ -849,7 +849,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
849 849 opn = "sc";
850 850 break;
851 851 default:
852   - MIPS_INVAL("load/store");
  852 + MIPS_INVAL(opn);
853 853 generate_exception(ctx, EXCP_RI);
854 854 return;
855 855 }
... ... @@ -860,7 +860,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
860 860 static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
861 861 int base, int16_t offset)
862 862 {
863   - const char *opn = "unk";
  863 + const char *opn = "flt_ldst";
864 864  
865 865 if (base == 0) {
866 866 GEN_LOAD_IMM_TN(T0, offset);
... ... @@ -896,7 +896,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
896 896 opn = "sdc1";
897 897 break;
898 898 default:
899   - MIPS_INVAL("float load/store");
  899 + MIPS_INVAL(opn);
900 900 generate_exception(ctx, EXCP_RI);
901 901 return;
902 902 }
... ... @@ -908,7 +908,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
908 908 int rs, int16_t imm)
909 909 {
910 910 uint32_t uimm;
911   - const char *opn = "unk";
  911 + const char *opn = "imm arith";
912 912  
913 913 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
914 914 /* if no destination, treat it as a NOP
... ... @@ -1073,7 +1073,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
1073 1073 break;
1074 1074 #endif
1075 1075 default:
1076   - MIPS_INVAL("imm arith");
  1076 + MIPS_INVAL(opn);
1077 1077 generate_exception(ctx, EXCP_RI);
1078 1078 return;
1079 1079 }
... ... @@ -1085,7 +1085,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
1085 1085 static void gen_arith (DisasContext *ctx, uint32_t opc,
1086 1086 int rd, int rs, int rt)
1087 1087 {
1088   - const char *opn = "unk";
  1088 + const char *opn = "arith";
1089 1089  
1090 1090 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
1091 1091 && opc != OPC_DADD && opc != OPC_DSUB) {
... ... @@ -1223,7 +1223,7 @@ static void gen_arith (DisasContext *ctx, uint32_t opc,
1223 1223 break;
1224 1224 #endif
1225 1225 default:
1226   - MIPS_INVAL("arith");
  1226 + MIPS_INVAL(opn);
1227 1227 generate_exception(ctx, EXCP_RI);
1228 1228 return;
1229 1229 }
... ... @@ -1235,7 +1235,7 @@ static void gen_arith (DisasContext *ctx, uint32_t opc,
1235 1235 /* Arithmetic on HI/LO registers */
1236 1236 static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
1237 1237 {
1238   - const char *opn = "unk";
  1238 + const char *opn = "hilo";
1239 1239  
1240 1240 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
1241 1241 /* Treat as a NOP */
... ... @@ -1264,7 +1264,7 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
1264 1264 opn = "mtlo";
1265 1265 break;
1266 1266 default:
1267   - MIPS_INVAL("HILO");
  1267 + MIPS_INVAL(opn);
1268 1268 generate_exception(ctx, EXCP_RI);
1269 1269 return;
1270 1270 }
... ... @@ -1274,7 +1274,7 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
1274 1274 static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1275 1275 int rs, int rt)
1276 1276 {
1277   - const char *opn = "unk";
  1277 + const char *opn = "mul/div";
1278 1278  
1279 1279 GEN_LOAD_REG_TN(T0, rs);
1280 1280 GEN_LOAD_REG_TN(T1, rt);
... ... @@ -1330,7 +1330,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1330 1330 opn = "msubu";
1331 1331 break;
1332 1332 default:
1333   - MIPS_INVAL("mul/div");
  1333 + MIPS_INVAL(opn);
1334 1334 generate_exception(ctx, EXCP_RI);
1335 1335 return;
1336 1336 }
... ... @@ -1340,7 +1340,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1340 1340 static void gen_cl (DisasContext *ctx, uint32_t opc,
1341 1341 int rd, int rs)
1342 1342 {
1343   - const char *opn = "unk";
  1343 + const char *opn = "CLx";
1344 1344 if (rd == 0) {
1345 1345 /* Treat as a NOP */
1346 1346 MIPS_DEBUG("NOP");
... ... @@ -1367,7 +1367,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
1367 1367 break;
1368 1368 #endif
1369 1369 default:
1370   - MIPS_INVAL("CLx");
  1370 + MIPS_INVAL(opn);
1371 1371 generate_exception(ctx, EXCP_RI);
1372 1372 return;
1373 1373 }
... ... @@ -1431,7 +1431,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
1431 1431 /* Never trap: treat as NOP */
1432 1432 return;
1433 1433 default:
1434   - MIPS_INVAL("TRAP");
  1434 + MIPS_INVAL("trap");
1435 1435 generate_exception(ctx, EXCP_RI);
1436 1436 return;
1437 1437 }
... ... @@ -1462,7 +1462,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
1462 1462 gen_op_ne();
1463 1463 break;
1464 1464 default:
1465   - MIPS_INVAL("TRAP");
  1465 + MIPS_INVAL("trap");
1466 1466 generate_exception(ctx, EXCP_RI);
1467 1467 return;
1468 1468 }
... ... @@ -1499,12 +1499,13 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1499 1499 int bcond = 0;
1500 1500  
1501 1501 if (ctx->hflags & MIPS_HFLAG_BMASK) {
  1502 +#ifdef MIPS_DEBUG_DISAS
1502 1503 if (loglevel & CPU_LOG_TB_IN_ASM) {
1503 1504 fprintf(logfile,
1504 1505 "Branch in delay slot at PC 0x" TARGET_FMT_lx "\n",
1505 1506 ctx->pc);
1506 1507 }
1507   - MIPS_INVAL("branch/jump in bdelay slot");
  1508 +#endif
1508 1509 generate_exception(ctx, EXCP_RI);
1509 1510 return;
1510 1511 }
... ... @@ -1553,6 +1554,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1553 1554 if (offset != 0 && offset != 16) {
1554 1555 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
1555 1556 others are reserved. */
  1557 + MIPS_INVAL("jump hint");
1556 1558 generate_exception(ctx, EXCP_RI);
1557 1559 return;
1558 1560 }
... ... @@ -1610,12 +1612,12 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1610 1612 return;
1611 1613 case OPC_J:
1612 1614 ctx->hflags |= MIPS_HFLAG_B;
1613   - MIPS_DEBUG("j %08x", btarget);
  1615 + MIPS_DEBUG("j " TARGET_FMT_lx, btarget);
1614 1616 break;
1615 1617 case OPC_JAL:
1616 1618 blink = 31;
1617 1619 ctx->hflags |= MIPS_HFLAG_B;
1618   - MIPS_DEBUG("jal %08x", btarget);
  1620 + MIPS_DEBUG("jal " TARGET_FMT_lx, btarget);
1619 1621 break;
1620 1622 case OPC_JR:
1621 1623 ctx->hflags |= MIPS_HFLAG_BR;
... ... @@ -1635,70 +1637,70 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1635 1637 switch (opc) {
1636 1638 case OPC_BEQ:
1637 1639 gen_op_eq();
1638   - MIPS_DEBUG("beq %s, %s, %08x",
  1640 + MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
1639 1641 regnames[rs], regnames[rt], btarget);
1640 1642 goto not_likely;
1641 1643 case OPC_BEQL:
1642 1644 gen_op_eq();
1643   - MIPS_DEBUG("beql %s, %s, %08x",
  1645 + MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
1644 1646 regnames[rs], regnames[rt], btarget);
1645 1647 goto likely;
1646 1648 case OPC_BNE:
1647 1649 gen_op_ne();
1648   - MIPS_DEBUG("bne %s, %s, %08x",
  1650 + MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
1649 1651 regnames[rs], regnames[rt], btarget);
1650 1652 goto not_likely;
1651 1653 case OPC_BNEL:
1652 1654 gen_op_ne();
1653   - MIPS_DEBUG("bnel %s, %s, %08x",
  1655 + MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
1654 1656 regnames[rs], regnames[rt], btarget);
1655 1657 goto likely;
1656 1658 case OPC_BGEZ:
1657 1659 gen_op_gez();
1658   - MIPS_DEBUG("bgez %s, %08x", regnames[rs], btarget);
  1660 + MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btarget);
1659 1661 goto not_likely;
1660 1662 case OPC_BGEZL:
1661 1663 gen_op_gez();
1662   - MIPS_DEBUG("bgezl %s, %08x", regnames[rs], btarget);
  1664 + MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
1663 1665 goto likely;
1664 1666 case OPC_BGEZAL:
1665 1667 gen_op_gez();
1666   - MIPS_DEBUG("bgezal %s, %08x", regnames[rs], btarget);
  1668 + MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btarget);
1667 1669 blink = 31;
1668 1670 goto not_likely;
1669 1671 case OPC_BGEZALL:
1670 1672 gen_op_gez();
1671 1673 blink = 31;
1672   - MIPS_DEBUG("bgezall %s, %08x", regnames[rs], btarget);
  1674 + MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btarget);
1673 1675 goto likely;
1674 1676 case OPC_BGTZ:
1675 1677 gen_op_gtz();
1676   - MIPS_DEBUG("bgtz %s, %08x", regnames[rs], btarget);
  1678 + MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btarget);
1677 1679 goto not_likely;
1678 1680 case OPC_BGTZL:
1679 1681 gen_op_gtz();
1680   - MIPS_DEBUG("bgtzl %s, %08x", regnames[rs], btarget);
  1682 + MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
1681 1683 goto likely;
1682 1684 case OPC_BLEZ:
1683 1685 gen_op_lez();
1684   - MIPS_DEBUG("blez %s, %08x", regnames[rs], btarget);
  1686 + MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btarget);
1685 1687 goto not_likely;
1686 1688 case OPC_BLEZL:
1687 1689 gen_op_lez();
1688   - MIPS_DEBUG("blezl %s, %08x", regnames[rs], btarget);
  1690 + MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
1689 1691 goto likely;
1690 1692 case OPC_BLTZ:
1691 1693 gen_op_ltz();
1692   - MIPS_DEBUG("bltz %s, %08x", regnames[rs], btarget);
  1694 + MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btarget);
1693 1695 goto not_likely;
1694 1696 case OPC_BLTZL:
1695 1697 gen_op_ltz();
1696   - MIPS_DEBUG("bltzl %s, %08x", regnames[rs], btarget);
  1698 + MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
1697 1699 goto likely;
1698 1700 case OPC_BLTZAL:
1699 1701 gen_op_ltz();
1700 1702 blink = 31;
1701   - MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget);
  1703 + MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget);
1702 1704 not_likely:
1703 1705 ctx->hflags |= MIPS_HFLAG_BC;
1704 1706 gen_op_set_bcond();
... ... @@ -1706,7 +1708,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1706 1708 case OPC_BLTZALL:
1707 1709 gen_op_ltz();
1708 1710 blink = 31;
1709   - MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget);
  1711 + MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget);
1710 1712 likely:
1711 1713 ctx->hflags |= MIPS_HFLAG_BL;
1712 1714 gen_op_set_bcond();
... ... @@ -1718,7 +1720,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1718 1720 return;
1719 1721 }
1720 1722 }
1721   - MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
  1723 + MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx,
1722 1724 blink, ctx->hflags, btarget);
1723 1725 ctx->btarget = btarget;
1724 1726 if (blink > 0) {
... ... @@ -4221,6 +4223,7 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
4221 4223 case OPC_DERET:
4222 4224 opn = "deret";
4223 4225 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
  4226 + MIPS_INVAL(opn);
4224 4227 generate_exception(ctx, EXCP_RI);
4225 4228 } else {
4226 4229 save_cpu_state(ctx, 0);
... ... @@ -4238,11 +4241,7 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
4238 4241 ctx->bstate = BS_EXCP;
4239 4242 break;
4240 4243 default:
4241   - if (loglevel & CPU_LOG_TB_IN_ASM) {
4242   - fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
4243   - ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
4244   - ((ctx->opcode >> 16) & 0x1F));
4245   - }
  4244 + MIPS_INVAL(opn);
4246 4245 generate_exception(ctx, EXCP_RI);
4247 4246 return;
4248 4247 }
... ... @@ -4254,25 +4253,26 @@ static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
4254 4253 int32_t cc, int32_t offset)
4255 4254 {
4256 4255 target_ulong btarget;
  4256 + const char *opn = "cp1 cond branch";
4257 4257  
4258 4258 btarget = ctx->pc + 4 + offset;
4259 4259  
4260 4260 switch (op) {
4261 4261 case OPC_BC1F:
4262 4262 gen_op_bc1f(cc);
4263   - MIPS_DEBUG("bc1f " TARGET_FMT_lx, btarget);
  4263 + opn = "bc1f";
4264 4264 goto not_likely;
4265 4265 case OPC_BC1FL:
4266 4266 gen_op_bc1f(cc);
4267   - MIPS_DEBUG("bc1fl " TARGET_FMT_lx, btarget);
  4267 + opn = "bc1fl";
4268 4268 goto likely;
4269 4269 case OPC_BC1T:
4270 4270 gen_op_bc1t(cc);
4271   - MIPS_DEBUG("bc1t " TARGET_FMT_lx, btarget);
  4271 + opn = "bc1t";
4272 4272 goto not_likely;
4273 4273 case OPC_BC1TL:
4274 4274 gen_op_bc1t(cc);
4275   - MIPS_DEBUG("bc1tl " TARGET_FMT_lx, btarget);
  4275 + opn = "bc1tl";
4276 4276 likely:
4277 4277 ctx->hflags |= MIPS_HFLAG_BL;
4278 4278 gen_op_set_bcond();
... ... @@ -4280,34 +4280,31 @@ static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
4280 4280 break;
4281 4281 case OPC_BC1FANY2:
4282 4282 gen_op_bc1fany2(cc);
4283   - MIPS_DEBUG("bc1fany2 " TARGET_FMT_lx, btarget);
  4283 + opn = "bc1fany2";
4284 4284 goto not_likely;
4285 4285 case OPC_BC1TANY2:
4286 4286 gen_op_bc1tany2(cc);
4287   - MIPS_DEBUG("bc1tany2 " TARGET_FMT_lx, btarget);
  4287 + opn = "bc1tany2";
4288 4288 goto not_likely;
4289 4289 case OPC_BC1FANY4:
4290 4290 gen_op_bc1fany4(cc);
4291   - MIPS_DEBUG("bc1fany4 " TARGET_FMT_lx, btarget);
  4291 + opn = "bc1fany4";
4292 4292 goto not_likely;
4293 4293 case OPC_BC1TANY4:
4294 4294 gen_op_bc1tany4(cc);
4295   - MIPS_DEBUG("bc1tany4 " TARGET_FMT_lx, btarget);
  4295 + opn = "bc1tany4";
4296 4296 not_likely:
4297 4297 ctx->hflags |= MIPS_HFLAG_BC;
4298 4298 gen_op_set_bcond();
4299 4299 break;
4300 4300 default:
4301   - MIPS_INVAL("cp1 branch");
  4301 + MIPS_INVAL(opn);
4302 4302 generate_exception (ctx, EXCP_RI);
4303 4303 return;
4304 4304 }
4305   -
4306   - MIPS_DEBUG("enter ds: cond %02x target " TARGET_FMT_lx,
  4305 + MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
4307 4306 ctx->hflags, btarget);
4308 4307 ctx->btarget = btarget;
4309   -
4310   - return;
4311 4308 }
4312 4309  
4313 4310 /* Coprocessor 1 (FPU) */
... ... @@ -4325,18 +4322,19 @@ static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
4325 4322 * FIXME: This is broken for R2, it needs to be checked at runtime, not
4326 4323 * at translation time.
4327 4324 */
4328   -#define CHECK_FR(ctx, freg) do { \
  4325 +#define CHECK_FR(ctx, freg) do { \
4329 4326 if (!((ctx)->CP0_Status & (1 << CP0St_FR)) && ((freg) & 1)) { \
4330   - generate_exception (ctx, EXCP_RI); \
4331   - return; \
4332   - } \
  4327 + MIPS_INVAL("FPU mode"); \
  4328 + generate_exception (ctx, EXCP_RI); \
  4329 + return; \
  4330 + } \
4333 4331 } while(0)
4334 4332  
4335 4333 #define FOP(func, fmt) (((fmt) << 21) | (func))
4336 4334  
4337 4335 static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
4338 4336 {
4339   - const char *opn = "unk";
  4337 + const char *opn = "cp1 move";
4340 4338  
4341 4339 switch (opc) {
4342 4340 case OPC_MFC1:
... ... @@ -4390,11 +4388,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
4390 4388 opn = "mthc1";
4391 4389 break;
4392 4390 default:
4393   - if (loglevel & CPU_LOG_TB_IN_ASM) {
4394   - fprintf(logfile, "Invalid CP1 opcode: %08x %03x %03x %03x\n",
4395   - ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
4396   - ((ctx->opcode >> 16) & 0x1F));
4397   - }
  4391 + MIPS_INVAL(opn);
4398 4392 generate_exception (ctx, EXCP_RI);
4399 4393 return;
4400 4394 }
... ... @@ -4440,7 +4434,7 @@ GEN_MOVCF(ps);
4440 4434 static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
4441 4435 int fs, int fd, int cc)
4442 4436 {
4443   - const char *opn = "unk";
  4437 + const char *opn = "farith";
4444 4438 const char *condnames[] = {
4445 4439 "c.f",
4446 4440 "c.un",
... ... @@ -5041,11 +5035,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
5041 5035 opn = condnames[func-48];
5042 5036 break;
5043 5037 default:
5044   - if (loglevel & CPU_LOG_TB_IN_ASM) {
5045   - fprintf(logfile, "Invalid FP arith function: %08x %03x %03x %03x\n",
5046   - ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
5047   - ((ctx->opcode >> 16) & 0x1F));
5048   - }
  5038 + MIPS_INVAL(opn);
5049 5039 generate_exception (ctx, EXCP_RI);
5050 5040 return;
5051 5041 }
... ... @@ -5059,7 +5049,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
5059 5049 static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, int fd,
5060 5050 int base, int index)
5061 5051 {
5062   - const char *opn = "unk";
  5052 + const char *opn = "extended float load/store";
5063 5053  
5064 5054 GEN_LOAD_REG_TN(T0, base);
5065 5055 GEN_LOAD_REG_TN(T1, index);
... ... @@ -5098,7 +5088,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, int fd,
5098 5088 opn = "suxc1";
5099 5089 break;
5100 5090 default:
5101   - MIPS_INVAL("extended float load/store");
  5091 + MIPS_INVAL(opn);
5102 5092 generate_exception(ctx, EXCP_RI);
5103 5093 return;
5104 5094 }
... ... @@ -5108,7 +5098,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, int fd,
5108 5098 static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, int fd,
5109 5099 int fr, int fs, int ft)
5110 5100 {
5111   - const char *opn = "unk";
  5101 + const char *opn = "flt3_arith";
5112 5102  
5113 5103 /* All of those work only on 64bit FPUs. */
5114 5104 CHECK_FR(ctx, fd | fr | fs | ft);
... ... @@ -5173,11 +5163,8 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, int fd,
5173 5163 generate_exception (ctx, EXCP_RI);
5174 5164 opn = "nmsub.ps";
5175 5165 break;
5176   - default:
5177   - if (loglevel & CPU_LOG_TB_IN_ASM) {
5178   - fprintf(logfile, "Invalid extended FP arith function: %08x %03x %03x\n",
5179   - ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F);
5180   - }
  5166 + default:
  5167 + MIPS_INVAL(opn);
5181 5168 generate_exception (ctx, EXCP_RI);
5182 5169 return;
5183 5170 }
... ... @@ -5459,7 +5446,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
5459 5446 /* treat as noop */
5460 5447 break;
5461 5448 default: /* Invalid */
5462   - MIPS_INVAL("REGIMM");
  5449 + MIPS_INVAL("regimm");
5463 5450 generate_exception(ctx, EXCP_RI);
5464 5451 break;
5465 5452 }
... ... @@ -5494,7 +5481,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
5494 5481 ctx->bstate = BS_STOP;
5495 5482 break;
5496 5483 default: /* Invalid */
5497   - MIPS_INVAL("MFMC0");
  5484 + MIPS_INVAL("mfmc0");
5498 5485 generate_exception(ctx, EXCP_RI);
5499 5486 break;
5500 5487 }
... ... @@ -5506,10 +5493,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
5506 5493 /* Shadow registers not implemented. */
5507 5494 GEN_LOAD_REG_TN(T0, rt);
5508 5495 GEN_STORE_TN_REG(rd, T0);
5509   - } else
  5496 + } else {
  5497 + MIPS_INVAL("shadow register move");
5510 5498 generate_exception(ctx, EXCP_RI);
  5499 + }
5511 5500 break;
5512 5501 default:
  5502 + MIPS_INVAL("cp0");
5513 5503 generate_exception(ctx, EXCP_RI);
5514 5504 break;
5515 5505 }
... ... @@ -5539,7 +5529,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
5539 5529 /* Treat as a noop */
5540 5530 break;
5541 5531  
5542   - /* Floating point. */
  5532 + /* Floating point (COP1). */
5543 5533 case OPC_LWC1:
5544 5534 case OPC_LDC1:
5545 5535 case OPC_SWC1:
... ... @@ -5584,6 +5574,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
5584 5574 (imm >> 8) & 0x7);
5585 5575 break;
5586 5576 default:
  5577 + MIPS_INVAL("cp1");
5587 5578 generate_exception (ctx, EXCP_RI);
5588 5579 break;
5589 5580 }
... ... @@ -5635,6 +5626,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
5635 5626 gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
5636 5627 break;
5637 5628 default:
  5629 + MIPS_INVAL("cp3");
5638 5630 generate_exception (ctx, EXCP_RI);
5639 5631 break;
5640 5632 }
... ... @@ -5667,7 +5659,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
5667 5659 /* MDMX: Not implemented. */
5668 5660 #endif
5669 5661 default: /* Invalid */
5670   - MIPS_INVAL("");
  5662 + MIPS_INVAL("major opcode");
5671 5663 generate_exception(ctx, EXCP_RI);
5672 5664 break;
5673 5665 }
... ... @@ -5764,7 +5756,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
5764 5756 cpu_dump_state(env, logfile, fprintf, 0);
5765 5757 }
5766 5758 #endif
5767   -#if defined MIPS_DEBUG_DISAS
  5759 +#ifdef MIPS_DEBUG_DISAS
5768 5760 if (loglevel & CPU_LOG_TB_IN_ASM)
5769 5761 fprintf(logfile, "\ntb %p super %d cond %04x\n",
5770 5762 tb, ctx.mem_idx, ctx.hflags);
... ...