gwj / at91sam9263 · Commits

Commit 9230e66e5c711bd077705465d34161d6b1e7fee7

Authored by bellard
1 parent 0523c6b7

CR8 support 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1237 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 21 additions and 11 deletions
hw/apic.c
  View file @9230e66
@@ -100,6 +100,18 @@ uint64_t cpu_get_apic_base(CPUState *env) @@ -100,6 +100,18 @@ uint64_t cpu_get_apic_base(CPUState *env)
100 return s->apicbase; 100 return s->apicbase;
101 } 101 }
102 102
  103 +void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
  104 +{
  105 + APICState *s = env->apic_state;
  106 + s->tpr = (val & 0x0f) << 4;
  107 +}
  108 +
  109 +uint8_t cpu_get_apic_tpr(CPUX86State *env)
  110 +{
  111 + APICState *s = env->apic_state;
  112 + return s->tpr >> 4;
  113 +}
  114 +
103 /* return -1 if no bit is set */ 115 /* return -1 if no bit is set */
104 static int get_highest_priority_int(uint32_t *tab) 116 static int get_highest_priority_int(uint32_t *tab)
105 { 117 {
target-i386/cpu.h
  View file @9230e66
@@ -509,15 +509,6 @@ typedef struct CPUX86State { @@ -509,15 +509,6 @@ typedef struct CPUX86State {
509 void *opaque; 509 void *opaque;
510 } CPUX86State; 510 } CPUX86State;
511 511
512 -#ifndef IN_OP_I386  
513 -void cpu_x86_outb(CPUX86State *env, int addr, int val);  
514 -void cpu_x86_outw(CPUX86State *env, int addr, int val);  
515 -void cpu_x86_outl(CPUX86State *env, int addr, int val);  
516 -int cpu_x86_inb(CPUX86State *env, int addr);  
517 -int cpu_x86_inw(CPUX86State *env, int addr);  
518 -int cpu_x86_inl(CPUX86State *env, int addr);  
519 -#endif  
520 -  
521 CPUX86State *cpu_x86_init(void); 512 CPUX86State *cpu_x86_init(void);
522 int cpu_x86_exec(CPUX86State *s); 513 int cpu_x86_exec(CPUX86State *s);
523 void cpu_x86_close(CPUX86State *s); 514 void cpu_x86_close(CPUX86State *s);
@@ -615,6 +606,10 @@ uint64_t cpu_get_tsc(CPUX86State *env); @@ -615,6 +606,10 @@ uint64_t cpu_get_tsc(CPUX86State *env);
615 606
616 void cpu_set_apic_base(CPUX86State *env, uint64_t val); 607 void cpu_set_apic_base(CPUX86State *env, uint64_t val);
617 uint64_t cpu_get_apic_base(CPUX86State *env); 608 uint64_t cpu_get_apic_base(CPUX86State *env);
  609 +void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
  610 +#ifndef NO_CPU_IO_DEFS
  611 +uint8_t cpu_get_apic_tpr(CPUX86State *env);
  612 +#endif
618 613
619 /* will be suppressed */ 614 /* will be suppressed */
620 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 615 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
target-i386/translate.c
  View file @9230e66
@@ -5631,17 +5631,20 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) @@ -5631,17 +5631,20 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
5631 case 2: 5631 case 2:
5632 case 3: 5632 case 3:
5633 case 4: 5633 case 4:
  5634 + case 8:
5634 if (b & 2) { 5635 if (b & 2) {
5635 gen_op_mov_TN_reg[ot][0][rm](); 5636 gen_op_mov_TN_reg[ot][0][rm]();
5636 gen_op_movl_crN_T0(reg); 5637 gen_op_movl_crN_T0(reg);
5637 gen_jmp_im(s->pc - s->cs_base); 5638 gen_jmp_im(s->pc - s->cs_base);
5638 gen_eob(s); 5639 gen_eob(s);
5639 } else { 5640 } else {
5640 - gen_op_movtl_T0_env(offsetof(CPUX86State,cr[reg])); 5641 + if (reg == 8)
  5642 + gen_op_movtl_T0_cr8();
  5643 + else
  5644 + gen_op_movtl_T0_env(offsetof(CPUX86State,cr[reg]));
5641 gen_op_mov_reg_T0[ot][rm](); 5645 gen_op_mov_reg_T0[ot][rm]();
5642 } 5646 }
5643 break; 5647 break;
5644 - /* XXX: add CR8 for x86_64 */  
5645 default: 5648 default:
5646 goto illegal_op; 5649 goto illegal_op;
5647 } 5650 }