gwj / at91sam9263 · Commits

Commit 91d848ebf3bc7fd73fb1a4fc11bdb04225b3f37d

Authored by bellard
1 parent e2733d20

disable PCI device for PMAC 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@966 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 34 additions and 27 deletions
hw/openpic.c
  View file @91d848e
... ... @@ -164,6 +164,7 @@ typedef struct IRQ_dst_t {
164 164  
165 165 struct openpic_t {
166 166 PCIDevice pci_dev;
  167 + int mem_index;
167 168 /* Global registers */
168 169 uint32_t frep; /* Feature reporting register */
169 170 uint32_t glbc; /* Global configuration register */
... ... @@ -937,7 +938,6 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
937 938 uint32_t addr, uint32_t size, int type)
938 939 {
939 940 openpic_t *opp;
940   - int opp_io_memory;
941 941  
942 942 DPRINTF("Map OpenPIC\n");
943 943 opp = (openpic_t *)pci_dev;
... ... @@ -953,9 +953,7 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
953 953 /* Per CPU registers */
954 954 DPRINTF("Register OPENPIC dst %08x => %08x\n",
955 955 addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU);
956   - opp_io_memory = cpu_register_io_memory(0, openpic_read,
957   - openpic_write, opp);
958   - cpu_register_physical_memory(addr, 0x40000, opp_io_memory);
  956 + cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
959 957 #if 0 // Don't implement ISU for now
960 958 opp_io_memory = cpu_register_io_memory(0, openpic_src_read,
961 959 openpic_src_write);
... ... @@ -964,8 +962,7 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
964 962 #endif
965 963 }
966 964  
967   -openpic_t *openpic_init (PCIBus *bus,
968   - uint32_t isu_base, uint32_t idu_base, int nb_cpus)
  965 +openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus)
969 966 {
970 967 openpic_t *opp;
971 968 uint8_t *pci_conf;
... ... @@ -974,25 +971,32 @@ openpic_t *openpic_init (PCIBus *bus,
974 971 /* XXX: for now, only one CPU is supported */
975 972 if (nb_cpus != 1)
976 973 return NULL;
977   - opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
978   - -1, NULL, NULL);
979   - if (opp == NULL)
980   - return NULL;
981   - pci_conf = opp->pci_dev.config;
982   - pci_conf[0x00] = 0x14; // IBM MPIC2
983   - pci_conf[0x01] = 0x10;
984   - pci_conf[0x02] = 0xFF;
985   - pci_conf[0x03] = 0xFF;
986   - pci_conf[0x0a] = 0x80; // PIC
987   - pci_conf[0x0b] = 0x08;
988   - pci_conf[0x0e] = 0x00; // header_type
989   - pci_conf[0x3d] = 0x00; // no interrupt pin
990   -
991   - /* Register I/O spaces */
992   - pci_register_io_region((PCIDevice *)opp, 0, 0x40000,
993   - PCI_ADDRESS_SPACE_MEM, &openpic_map);
994   -
995   - isu_base &= 0xFFFC0000;
  974 + if (bus) {
  975 + opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
  976 + -1, NULL, NULL);
  977 + if (opp == NULL)
  978 + return NULL;
  979 + pci_conf = opp->pci_dev.config;
  980 + pci_conf[0x00] = 0x14; // IBM MPIC2
  981 + pci_conf[0x01] = 0x10;
  982 + pci_conf[0x02] = 0xFF;
  983 + pci_conf[0x03] = 0xFF;
  984 + pci_conf[0x0a] = 0x80; // PIC
  985 + pci_conf[0x0b] = 0x08;
  986 + pci_conf[0x0e] = 0x00; // header_type
  987 + pci_conf[0x3d] = 0x00; // no interrupt pin
  988 +
  989 + /* Register I/O spaces */
  990 + pci_register_io_region((PCIDevice *)opp, 0, 0x40000,
  991 + PCI_ADDRESS_SPACE_MEM, &openpic_map);
  992 + } else {
  993 + opp = qemu_mallocz(sizeof(openpic_t));
  994 + }
  995 +
  996 + opp->mem_index = cpu_register_io_memory(0, openpic_read,
  997 + openpic_write, opp);
  998 +
  999 + // isu_base &= 0xFFFC0000;
996 1000 opp->nb_cpus = nb_cpus;
997 1001 /* Set IRQ types */
998 1002 for (i = 0; i < EXT_IRQ; i++) {
... ... @@ -1013,6 +1017,7 @@ openpic_t *openpic_init (PCIBus *bus,
1013 1017 opp->src[i].type = IRQ_INTERNAL;
1014 1018 }
1015 1019 openpic_reset(opp);
1016   -
  1020 + if (pmem_index)
  1021 + *pmem_index = opp->mem_index;
1017 1022 return opp;
1018 1023 }
... ...
hw/ppc_chrp.c
  View file @91d848e
... ... @@ -36,6 +36,7 @@ static int dbdma_mem_index;
36 36 static int cuda_mem_index;
37 37 static int ide0_mem_index;
38 38 static int ide1_mem_index;
  39 +static int openpic_mem_index;
39 40  
40 41 /* DBDMA: currently no op - should suffice right now */
41 42  
... ... @@ -87,6 +88,7 @@ static void macio_map(PCIDevice *pci_dev, int region_num,
87 88 cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
88 89 cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
89 90 cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
  91 + cpu_register_physical_memory(addr + 0x40000, 0x40000, openpic_mem_index);
90 92 }
91 93  
92 94 static void macio_init(PCIBus *bus)
... ... @@ -191,7 +193,7 @@ void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
191 193 /* init basic PC hardware */
192 194 vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
193 195 vga_ram_size);
194   - openpic = openpic_init(pci_bus, 0x00000000, 0xF0000000, 1);
  196 + openpic = openpic_init(NULL, &openpic_mem_index, 1);
195 197 pci_pmac_set_openpic(pci_bus, openpic);
196 198  
197 199 /* XXX: suppress that */
... ...