gwj / at91sam9263 · Commits

Commit 905fdcb5264c7b0ed2896dc042e6fe3dd0e25952

Authored by blueswir1
1 parent 084a197a

Add common keys to firmware configuration 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5260 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 5 changed files with 77 additions and 19 deletions
hw/fw_cfg.c
  View file @905fdcb
... ... @@ -259,6 +259,7 @@ void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
259 259 {
260 260 FWCfgState *s;
261 261 int io_ctl_memory, io_data_memory;
  262 + extern int nographic;
262 263  
263 264 s = qemu_mallocz(sizeof(FWCfgState));
264 265 if (!s)
... ... @@ -283,6 +284,9 @@ void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
283 284 }
284 285 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (uint8_t *)"QEMU", 4);
285 286 fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16);
  287 + fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)nographic);
  288 + fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
  289 +
286 290 register_savevm("fw_cfg", -1, 1, fw_cfg_save, fw_cfg_load, s);
287 291 qemu_register_reset(fw_cfg_reset, s);
288 292 fw_cfg_reset(s);
... ...
hw/fw_cfg.h
  View file @905fdcb
... ... @@ -4,6 +4,10 @@
4 4 #define FW_CFG_SIGNATURE 0x00
5 5 #define FW_CFG_ID 0x01
6 6 #define FW_CFG_UUID 0x02
  7 +#define FW_CFG_RAM_SIZE 0x03
  8 +#define FW_CFG_NOGRAPHIC 0x04
  9 +#define FW_CFG_NB_CPUS 0x05
  10 +#define FW_CFG_MACHINE_ID 0x06
7 11 #define FW_CFG_MAX_ENTRY 0x10
8 12  
9 13 #define FW_CFG_WRITE_CHANNEL 0x4000
... ...
... ... @@ -433,6 +433,7 @@ static void bochs_bios_init(void)
433 433  
434 434 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
435 435 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
  436 + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
436 437 }
437 438  
438 439 /* Generate an initial boot sector which sets state and jump to
... ...
hw/sun4m.c
  View file @905fdcb
... ... @@ -101,7 +101,8 @@ struct hwdef {
101 101 // register bit numbers
102 102 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
103 103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104   - int machine_id; // For NVRAM
  104 + uint8_t nvram_machine_id;
  105 + uint16_t machine_id;
105 106 uint32_t iommu_version;
106 107 uint32_t intbit_to_level[32];
107 108 uint64_t max_mem;
... ... @@ -122,7 +123,8 @@ struct sun4d_hwdef {
122 123 // IRQ numbers are not PIL ones, but SBI register bit numbers
123 124 int esp_irq, le_irq, clock_irq, clock1_irq;
124 125 int ser_irq, ms_kb_irq, me_irq;
125   - int machine_id; // For NVRAM
  126 + uint8_t nvram_machine_id;
  127 + uint16_t machine_id;
126 128 uint32_t iounit_version;
127 129 uint64_t max_mem;
128 130 const char * const default_cpu_model;
... ... @@ -178,7 +180,7 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
178 180 const char *boot_devices, ram_addr_t RAM_size,
179 181 uint32_t kernel_size,
180 182 int width, int height, int depth,
181   - int machine_id, const char *arch)
  183 + int nvram_machine_id, const char *arch)
182 184 {
183 185 unsigned int i;
184 186 uint32_t start, end;
... ... @@ -251,7 +253,8 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
251 253 end = 0x1fd0;
252 254 OpenBIOS_finish_partition(part_header, end - start);
253 255  
254   - Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
  256 + Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
  257 + nvram_machine_id);
255 258  
256 259 for (i = 0; i < sizeof(image); i++)
257 260 m48t59_write(nvram, i, image[i]);
... ... @@ -568,7 +571,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
568 571  
569 572 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
570 573 boot_device, RAM_size, kernel_size, graphic_width,
571   - graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
  574 + graphic_height, graphic_depth, hwdef->nvram_machine_id,
  575 + "Sun4m");
572 576  
573 577 if (hwdef->ecc_base != (target_phys_addr_t)-1)
574 578 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
... ... @@ -576,6 +580,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
576 580  
577 581 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
578 582 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
  583 + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
  584 + fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
579 585 }
580 586  
581 587 static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
... ... @@ -721,12 +727,30 @@ static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
721 727  
722 728 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
723 729 boot_device, RAM_size, kernel_size, graphic_width,
724   - graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
  730 + graphic_height, graphic_depth, hwdef->nvram_machine_id,
  731 + "Sun4c");
725 732  
726 733 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
727 734 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
  735 + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
  736 + fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
728 737 }
729 738  
  739 +enum {
  740 + ss2_id = 0,
  741 + ss5_id = 32,
  742 + vger_id,
  743 + lx_id,
  744 + ss4_id,
  745 + scls_id,
  746 + sbook_id,
  747 + ss10_id = 64,
  748 + ss20_id,
  749 + ss600mp_id,
  750 + ss1000_id = 96,
  751 + ss2000_id,
  752 +};
  753 +
730 754 static const struct hwdef hwdefs[] = {
731 755 /* SS-5 */
732 756 {
... ... @@ -761,7 +785,8 @@ static const struct hwdef hwdefs[] = {
761 785 .fd_irq = 22,
762 786 .me_irq = 30,
763 787 .cs_irq = 5,
764   - .machine_id = 0x80,
  788 + .nvram_machine_id = 0x80,
  789 + .machine_id = ss5_id,
765 790 .iommu_version = 0x05000000,
766 791 .intbit_to_level = {
767 792 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
... ... @@ -805,7 +830,8 @@ static const struct hwdef hwdefs[] = {
805 830 .me_irq = 30,
806 831 .cs_irq = -1,
807 832 .ecc_irq = 28,
808   - .machine_id = 0x72,
  833 + .nvram_machine_id = 0x72,
  834 + .machine_id = ss10_id,
809 835 .iommu_version = 0x03000000,
810 836 .intbit_to_level = {
811 837 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
... ... @@ -849,7 +875,8 @@ static const struct hwdef hwdefs[] = {
849 875 .me_irq = 30,
850 876 .cs_irq = -1,
851 877 .ecc_irq = 28,
852   - .machine_id = 0x71,
  878 + .nvram_machine_id = 0x71,
  879 + .machine_id = ss600mp_id,
853 880 .iommu_version = 0x01000000,
854 881 .intbit_to_level = {
855 882 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
... ... @@ -893,7 +920,8 @@ static const struct hwdef hwdefs[] = {
893 920 .me_irq = 30,
894 921 .cs_irq = -1,
895 922 .ecc_irq = 28,
896   - .machine_id = 0x72,
  923 + .nvram_machine_id = 0x72,
  924 + .machine_id = ss20_id,
897 925 .iommu_version = 0x13000000,
898 926 .intbit_to_level = {
899 927 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
... ... @@ -933,7 +961,8 @@ static const struct hwdef hwdefs[] = {
933 961 .fd_irq = 1,
934 962 .me_irq = 1,
935 963 .cs_irq = -1,
936   - .machine_id = 0x55,
  964 + .nvram_machine_id = 0x55,
  965 + .machine_id = ss2_id,
937 966 .max_mem = 0x10000000,
938 967 .default_cpu_model = "Cypress CY7C601",
939 968 },
... ... @@ -970,7 +999,8 @@ static const struct hwdef hwdefs[] = {
970 999 .fd_irq = 22,
971 1000 .me_irq = 30,
972 1001 .cs_irq = -1,
973   - .machine_id = 0x80,
  1002 + .nvram_machine_id = 0x80,
  1003 + .machine_id = vger_id,
974 1004 .iommu_version = 0x05000000,
975 1005 .intbit_to_level = {
976 1006 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
... ... @@ -1012,7 +1042,8 @@ static const struct hwdef hwdefs[] = {
1012 1042 .fd_irq = 22,
1013 1043 .me_irq = 30,
1014 1044 .cs_irq = -1,
1015   - .machine_id = 0x80,
  1045 + .nvram_machine_id = 0x80,
  1046 + .machine_id = lx_id,
1016 1047 .iommu_version = 0x04000000,
1017 1048 .intbit_to_level = {
1018 1049 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
... ... @@ -1054,7 +1085,8 @@ static const struct hwdef hwdefs[] = {
1054 1085 .fd_irq = 22,
1055 1086 .me_irq = 30,
1056 1087 .cs_irq = 5,
1057   - .machine_id = 0x80,
  1088 + .nvram_machine_id = 0x80,
  1089 + .machine_id = ss4_id,
1058 1090 .iommu_version = 0x05000000,
1059 1091 .intbit_to_level = {
1060 1092 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
... ... @@ -1096,7 +1128,8 @@ static const struct hwdef hwdefs[] = {
1096 1128 .fd_irq = 22,
1097 1129 .me_irq = 30,
1098 1130 .cs_irq = -1,
1099   - .machine_id = 0x80,
  1131 + .nvram_machine_id = 0x80,
  1132 + .machine_id = scls_id,
1100 1133 .iommu_version = 0x05000000,
1101 1134 .intbit_to_level = {
1102 1135 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
... ... @@ -1138,7 +1171,8 @@ static const struct hwdef hwdefs[] = {
1138 1171 .fd_irq = 22,
1139 1172 .me_irq = 30,
1140 1173 .cs_irq = -1,
1141   - .machine_id = 0x80,
  1174 + .nvram_machine_id = 0x80,
  1175 + .machine_id = sbook_id,
1142 1176 .iommu_version = 0x05000000,
1143 1177 .intbit_to_level = {
1144 1178 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
... ... @@ -1359,7 +1393,8 @@ static const struct sun4d_hwdef sun4d_hwdefs[] = {
1359 1393 .clock1_irq = 10,
1360 1394 .ms_kb_irq = 12,
1361 1395 .ser_irq = 12,
1362   - .machine_id = 0x80,
  1396 + .nvram_machine_id = 0x80,
  1397 + .machine_id = ss1000_id,
1363 1398 .iounit_version = 0x03000000,
1364 1399 .max_mem = 0xf00000000ULL,
1365 1400 .default_cpu_model = "TI SuperSparc II",
... ... @@ -1392,7 +1427,8 @@ static const struct sun4d_hwdef sun4d_hwdefs[] = {
1392 1427 .clock1_irq = 10,
1393 1428 .ms_kb_irq = 12,
1394 1429 .ser_irq = 12,
1395   - .machine_id = 0x80,
  1430 + .nvram_machine_id = 0x80,
  1431 + .machine_id = ss2000_id,
1396 1432 .iounit_version = 0x03000000,
1397 1433 .max_mem = 0xf00000000ULL,
1398 1434 .default_cpu_model = "TI SuperSparc II",
... ... @@ -1538,10 +1574,13 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1538 1574  
1539 1575 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1540 1576 boot_device, RAM_size, kernel_size, graphic_width,
1541   - graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
  1577 + graphic_height, graphic_depth, hwdef->nvram_machine_id,
  1578 + "Sun4d");
1542 1579  
1543 1580 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1544 1581 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
  1582 + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
  1583 + fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1545 1584 }
1546 1585  
1547 1586 /* SPARCserver 1000 hardware initialisation */
... ...
hw/sun4u.c
  View file @905fdcb
... ... @@ -49,6 +49,7 @@
49 49  
50 50 struct hwdef {
51 51 const char * const default_cpu_model;
  52 + uint16_t machine_id;
52 53 };
53 54  
54 55 int DMA_get_channel_mode (int nchan)
... ... @@ -420,16 +421,25 @@ static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
420 421  
421 422 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
422 423 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
  424 + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
  425 + fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
423 426 }
424 427  
  428 +enum {
  429 + sun4u_id = 0,
  430 + sun4v_id = 64,
  431 +};
  432 +
425 433 static const struct hwdef hwdefs[] = {
426 434 /* Sun4u generic PC-like machine */
427 435 {
428 436 .default_cpu_model = "TI UltraSparc II",
  437 + .machine_id = sun4u_id,
429 438 },
430 439 /* Sun4v generic PC-like machine */
431 440 {
432 441 .default_cpu_model = "Sun UltraSparc T1",
  442 + .machine_id = sun4v_id,
433 443 },
434 444 };
435 445  
... ...