gwj / at91sam9263 · Commits

Commit 8f99cc6c3e4e8945f837dc11d0d6c8b108bc46f7

Authored by aurel32
1 parent a73d39ba

SH4: Convert register moves to TCG 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5100 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 209 additions and 261 deletions
target-sh4/op.c
  View file @8f99cc6
@@ -401,12 +401,6 @@ void OPPROTO op_jmp_T0(void) @@ -401,12 +401,6 @@ void OPPROTO op_jmp_T0(void)
401 RETURN(); 401 RETURN();
402 } 402 }
403 403
404 -void OPPROTO op_movl_rN_rN(void)  
405 -{  
406 - env->gregs[PARAM2] = env->gregs[PARAM1];  
407 - RETURN();  
408 -}  
409 -  
410 void OPPROTO op_ldcl_rMplus_rN_bank(void) 404 void OPPROTO op_ldcl_rMplus_rN_bank(void)
411 { 405 {
412 env->gregs[PARAM2] = env->gregs[PARAM1]; 406 env->gregs[PARAM2] = env->gregs[PARAM1];
@@ -550,84 +544,6 @@ void OPPROTO op_shlr16_Rn(void) @@ -550,84 +544,6 @@ void OPPROTO op_shlr16_Rn(void)
550 RETURN(); 544 RETURN();
551 } 545 }
552 546
553 -void OPPROTO op_movl_T0_rN(void)  
554 -{  
555 - env->gregs[PARAM1] = T0;  
556 - RETURN();  
557 -}  
558 -  
559 -void OPPROTO op_movl_T1_rN(void)  
560 -{  
561 - env->gregs[PARAM1] = T1;  
562 - RETURN();  
563 -}  
564 -  
565 -void OPPROTO op_movb_rN_T0(void)  
566 -{  
567 - T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);  
568 - RETURN();  
569 -}  
570 -  
571 -void OPPROTO op_movub_rN_T0(void)  
572 -{  
573 - T0 = env->gregs[PARAM1] & 0xff;  
574 - RETURN();  
575 -}  
576 -  
577 -void OPPROTO op_movw_rN_T0(void)  
578 -{  
579 - T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);  
580 - RETURN();  
581 -}  
582 -  
583 -void OPPROTO op_movuw_rN_T0(void)  
584 -{  
585 - T0 = env->gregs[PARAM1] & 0xffff;  
586 - RETURN();  
587 -}  
588 -  
589 -void OPPROTO op_movl_rN_T0(void)  
590 -{  
591 - T0 = env->gregs[PARAM1];  
592 - RETURN();  
593 -}  
594 -  
595 -void OPPROTO op_movb_rN_T1(void)  
596 -{  
597 - T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);  
598 - RETURN();  
599 -}  
600 -  
601 -void OPPROTO op_movub_rN_T1(void)  
602 -{  
603 - T1 = env->gregs[PARAM1] & 0xff;  
604 - RETURN();  
605 -}  
606 -  
607 -void OPPROTO op_movw_rN_T1(void)  
608 -{  
609 - T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);  
610 - RETURN();  
611 -}  
612 -  
613 -void OPPROTO op_movuw_rN_T1(void)  
614 -{  
615 - T1 = env->gregs[PARAM1] & 0xffff;  
616 - RETURN();  
617 -}  
618 -  
619 -void OPPROTO op_movl_rN_T1(void)  
620 -{  
621 - T1 = env->gregs[PARAM1];  
622 - RETURN();  
623 -}  
624 -  
625 -void OPPROTO op_movl_imm_rN(void)  
626 -{  
627 - env->gregs[PARAM2] = PARAM1;  
628 - RETURN();  
629 -}  
630 -  
631 void OPPROTO op_fmov_frN_FT0(void) 547 void OPPROTO op_fmov_frN_FT0(void)
632 { 548 {
633 FT0 = env->fregs[PARAM1]; 549 FT0 = env->fregs[PARAM1];
target-sh4/translate.c
  View file @8f99cc6
@@ -78,6 +78,24 @@ static void sh4_translate_init(void) @@ -78,6 +78,24 @@ static void sh4_translate_init(void)
78 done_init = 1; 78 done_init = 1;
79 } 79 }
80 80
  81 +/* General purpose registers moves. */
  82 +static inline void gen_movl_imm_rN(target_ulong arg, int reg)
  83 +{
  84 + TCGv tmp = tcg_const_tl(arg);
  85 + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUState, gregs[reg]));
  86 + tcg_temp_free(tmp);
  87 +}
  88 +
  89 +static always_inline void gen_movl_T_rN (TCGv t, int reg)
  90 +{
  91 + tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, gregs[reg]));
  92 +}
  93 +
  94 +static always_inline void gen_movl_rN_T (TCGv t, int reg)
  95 +{
  96 + tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, gregs[reg]));
  97 +}
  98 +
81 #ifdef CONFIG_USER_ONLY 99 #ifdef CONFIG_USER_ONLY
82 100
83 #define GEN_OP_LD(width, reg) \ 101 #define GEN_OP_LD(width, reg) \
@@ -322,29 +340,29 @@ void _decode_opc(DisasContext * ctx) @@ -322,29 +340,29 @@ void _decode_opc(DisasContext * ctx)
322 340
323 switch (ctx->opcode & 0xf000) { 341 switch (ctx->opcode & 0xf000) {
324 case 0x1000: /* mov.l Rm,@(disp,Rn) */ 342 case 0x1000: /* mov.l Rm,@(disp,Rn) */
325 - gen_op_movl_rN_T0(REG(B7_4));  
326 - gen_op_movl_rN_T1(REG(B11_8)); 343 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  344 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
327 gen_op_addl_imm_T1(B3_0 * 4); 345 gen_op_addl_imm_T1(B3_0 * 4);
328 gen_op_stl_T0_T1(ctx); 346 gen_op_stl_T0_T1(ctx);
329 return; 347 return;
330 case 0x5000: /* mov.l @(disp,Rm),Rn */ 348 case 0x5000: /* mov.l @(disp,Rm),Rn */
331 - gen_op_movl_rN_T0(REG(B7_4)); 349 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
332 gen_op_addl_imm_T0(B3_0 * 4); 350 gen_op_addl_imm_T0(B3_0 * 4);
333 gen_op_ldl_T0_T0(ctx); 351 gen_op_ldl_T0_T0(ctx);
334 - gen_op_movl_T0_rN(REG(B11_8)); 352 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
335 return; 353 return;
336 case 0xe000: /* mov #imm,Rn */ 354 case 0xe000: /* mov #imm,Rn */
337 - gen_op_movl_imm_rN(B7_0s, REG(B11_8)); 355 + gen_movl_imm_rN(B7_0s, REG(B11_8));
338 return; 356 return;
339 case 0x9000: /* mov.w @(disp,PC),Rn */ 357 case 0x9000: /* mov.w @(disp,PC),Rn */
340 tcg_gen_movi_tl(cpu_T[0], ctx->pc + 4 + B7_0 * 2); 358 tcg_gen_movi_tl(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
341 gen_op_ldw_T0_T0(ctx); 359 gen_op_ldw_T0_T0(ctx);
342 - gen_op_movl_T0_rN(REG(B11_8)); 360 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
343 return; 361 return;
344 case 0xd000: /* mov.l @(disp,PC),Rn */ 362 case 0xd000: /* mov.l @(disp,PC),Rn */
345 tcg_gen_movi_tl(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3); 363 tcg_gen_movi_tl(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
346 gen_op_ldl_T0_T0(ctx); 364 gen_op_ldl_T0_T0(ctx);
347 - gen_op_movl_T0_rN(REG(B11_8)); 365 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
348 return; 366 return;
349 case 0x7000: /* add #imm,Rn */ 367 case 0x7000: /* add #imm,Rn */
350 gen_op_add_imm_rN(B7_0s, REG(B11_8)); 368 gen_op_add_imm_rN(B7_0s, REG(B11_8));
@@ -364,312 +382,324 @@ void _decode_opc(DisasContext * ctx) @@ -364,312 +382,324 @@ void _decode_opc(DisasContext * ctx)
364 382
365 switch (ctx->opcode & 0xf00f) { 383 switch (ctx->opcode & 0xf00f) {
366 case 0x6003: /* mov Rm,Rn */ 384 case 0x6003: /* mov Rm,Rn */
367 - gen_op_movl_rN_T0(REG(B7_4));  
368 - gen_op_movl_T0_rN(REG(B11_8)); 385 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  386 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
369 return; 387 return;
370 case 0x2000: /* mov.b Rm,@Rn */ 388 case 0x2000: /* mov.b Rm,@Rn */
371 - gen_op_movl_rN_T0(REG(B7_4));  
372 - gen_op_movl_rN_T1(REG(B11_8)); 389 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  390 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
373 gen_op_stb_T0_T1(ctx); 391 gen_op_stb_T0_T1(ctx);
374 return; 392 return;
375 case 0x2001: /* mov.w Rm,@Rn */ 393 case 0x2001: /* mov.w Rm,@Rn */
376 - gen_op_movl_rN_T0(REG(B7_4));  
377 - gen_op_movl_rN_T1(REG(B11_8)); 394 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  395 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
378 gen_op_stw_T0_T1(ctx); 396 gen_op_stw_T0_T1(ctx);
379 return; 397 return;
380 case 0x2002: /* mov.l Rm,@Rn */ 398 case 0x2002: /* mov.l Rm,@Rn */
381 - gen_op_movl_rN_T0(REG(B7_4));  
382 - gen_op_movl_rN_T1(REG(B11_8)); 399 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  400 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
383 gen_op_stl_T0_T1(ctx); 401 gen_op_stl_T0_T1(ctx);
384 return; 402 return;
385 case 0x6000: /* mov.b @Rm,Rn */ 403 case 0x6000: /* mov.b @Rm,Rn */
386 - gen_op_movl_rN_T0(REG(B7_4)); 404 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
387 gen_op_ldb_T0_T0(ctx); 405 gen_op_ldb_T0_T0(ctx);
388 - gen_op_movl_T0_rN(REG(B11_8)); 406 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
389 return; 407 return;
390 case 0x6001: /* mov.w @Rm,Rn */ 408 case 0x6001: /* mov.w @Rm,Rn */
391 - gen_op_movl_rN_T0(REG(B7_4)); 409 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
392 gen_op_ldw_T0_T0(ctx); 410 gen_op_ldw_T0_T0(ctx);
393 - gen_op_movl_T0_rN(REG(B11_8)); 411 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
394 return; 412 return;
395 case 0x6002: /* mov.l @Rm,Rn */ 413 case 0x6002: /* mov.l @Rm,Rn */
396 - gen_op_movl_rN_T0(REG(B7_4)); 414 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
397 gen_op_ldl_T0_T0(ctx); 415 gen_op_ldl_T0_T0(ctx);
398 - gen_op_movl_T0_rN(REG(B11_8)); 416 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
399 return; 417 return;
400 case 0x2004: /* mov.b Rm,@-Rn */ 418 case 0x2004: /* mov.b Rm,@-Rn */
401 - gen_op_movl_rN_T0(REG(B7_4)); 419 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
402 gen_op_dec1_rN(REG(B11_8)); /* modify register status */ 420 gen_op_dec1_rN(REG(B11_8)); /* modify register status */
403 - gen_op_movl_rN_T1(REG(B11_8)); 421 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
404 gen_op_inc1_rN(REG(B11_8)); /* recover register status */ 422 gen_op_inc1_rN(REG(B11_8)); /* recover register status */
405 gen_op_stb_T0_T1(ctx); /* might cause re-execution */ 423 gen_op_stb_T0_T1(ctx); /* might cause re-execution */
406 gen_op_dec1_rN(REG(B11_8)); /* modify register status */ 424 gen_op_dec1_rN(REG(B11_8)); /* modify register status */
407 return; 425 return;
408 case 0x2005: /* mov.w Rm,@-Rn */ 426 case 0x2005: /* mov.w Rm,@-Rn */
409 - gen_op_movl_rN_T0(REG(B7_4)); 427 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
410 gen_op_dec2_rN(REG(B11_8)); 428 gen_op_dec2_rN(REG(B11_8));
411 - gen_op_movl_rN_T1(REG(B11_8)); 429 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
412 gen_op_inc2_rN(REG(B11_8)); 430 gen_op_inc2_rN(REG(B11_8));
413 gen_op_stw_T0_T1(ctx); 431 gen_op_stw_T0_T1(ctx);
414 gen_op_dec2_rN(REG(B11_8)); 432 gen_op_dec2_rN(REG(B11_8));
415 return; 433 return;
416 case 0x2006: /* mov.l Rm,@-Rn */ 434 case 0x2006: /* mov.l Rm,@-Rn */
417 - gen_op_movl_rN_T0(REG(B7_4)); 435 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
418 gen_op_dec4_rN(REG(B11_8)); 436 gen_op_dec4_rN(REG(B11_8));
419 - gen_op_movl_rN_T1(REG(B11_8)); 437 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
420 gen_op_inc4_rN(REG(B11_8)); 438 gen_op_inc4_rN(REG(B11_8));
421 gen_op_stl_T0_T1(ctx); 439 gen_op_stl_T0_T1(ctx);
422 gen_op_dec4_rN(REG(B11_8)); 440 gen_op_dec4_rN(REG(B11_8));
423 return; 441 return;
424 case 0x6004: /* mov.b @Rm+,Rn */ 442 case 0x6004: /* mov.b @Rm+,Rn */
425 - gen_op_movl_rN_T0(REG(B7_4)); 443 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
426 gen_op_ldb_T0_T0(ctx); 444 gen_op_ldb_T0_T0(ctx);
427 - gen_op_movl_T0_rN(REG(B11_8)); 445 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
428 if ( B11_8 != B7_4 ) 446 if ( B11_8 != B7_4 )
429 gen_op_inc1_rN(REG(B7_4)); 447 gen_op_inc1_rN(REG(B7_4));
430 return; 448 return;
431 case 0x6005: /* mov.w @Rm+,Rn */ 449 case 0x6005: /* mov.w @Rm+,Rn */
432 - gen_op_movl_rN_T0(REG(B7_4)); 450 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
433 gen_op_ldw_T0_T0(ctx); 451 gen_op_ldw_T0_T0(ctx);
434 - gen_op_movl_T0_rN(REG(B11_8)); 452 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
435 if ( B11_8 != B7_4 ) 453 if ( B11_8 != B7_4 )
436 gen_op_inc2_rN(REG(B7_4)); 454 gen_op_inc2_rN(REG(B7_4));
437 return; 455 return;
438 case 0x6006: /* mov.l @Rm+,Rn */ 456 case 0x6006: /* mov.l @Rm+,Rn */
439 - gen_op_movl_rN_T0(REG(B7_4)); 457 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
440 gen_op_ldl_T0_T0(ctx); 458 gen_op_ldl_T0_T0(ctx);
441 - gen_op_movl_T0_rN(REG(B11_8)); 459 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
442 if ( B11_8 != B7_4 ) 460 if ( B11_8 != B7_4 )
443 gen_op_inc4_rN(REG(B7_4)); 461 gen_op_inc4_rN(REG(B7_4));
444 return; 462 return;
445 case 0x0004: /* mov.b Rm,@(R0,Rn) */ 463 case 0x0004: /* mov.b Rm,@(R0,Rn) */
446 - gen_op_movl_rN_T0(REG(B7_4));  
447 - gen_op_movl_rN_T1(REG(B11_8)); 464 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  465 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
448 gen_op_add_rN_T1(REG(0)); 466 gen_op_add_rN_T1(REG(0));
449 gen_op_stb_T0_T1(ctx); 467 gen_op_stb_T0_T1(ctx);
450 return; 468 return;
451 case 0x0005: /* mov.w Rm,@(R0,Rn) */ 469 case 0x0005: /* mov.w Rm,@(R0,Rn) */
452 - gen_op_movl_rN_T0(REG(B7_4));  
453 - gen_op_movl_rN_T1(REG(B11_8)); 470 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  471 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
454 gen_op_add_rN_T1(REG(0)); 472 gen_op_add_rN_T1(REG(0));
455 gen_op_stw_T0_T1(ctx); 473 gen_op_stw_T0_T1(ctx);
456 return; 474 return;
457 case 0x0006: /* mov.l Rm,@(R0,Rn) */ 475 case 0x0006: /* mov.l Rm,@(R0,Rn) */
458 - gen_op_movl_rN_T0(REG(B7_4));  
459 - gen_op_movl_rN_T1(REG(B11_8)); 476 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  477 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
460 gen_op_add_rN_T1(REG(0)); 478 gen_op_add_rN_T1(REG(0));
461 gen_op_stl_T0_T1(ctx); 479 gen_op_stl_T0_T1(ctx);
462 return; 480 return;
463 case 0x000c: /* mov.b @(R0,Rm),Rn */ 481 case 0x000c: /* mov.b @(R0,Rm),Rn */
464 - gen_op_movl_rN_T0(REG(B7_4)); 482 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
465 gen_op_add_rN_T0(REG(0)); 483 gen_op_add_rN_T0(REG(0));
466 gen_op_ldb_T0_T0(ctx); 484 gen_op_ldb_T0_T0(ctx);
467 - gen_op_movl_T0_rN(REG(B11_8)); 485 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
468 return; 486 return;
469 case 0x000d: /* mov.w @(R0,Rm),Rn */ 487 case 0x000d: /* mov.w @(R0,Rm),Rn */
470 - gen_op_movl_rN_T0(REG(B7_4)); 488 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
471 gen_op_add_rN_T0(REG(0)); 489 gen_op_add_rN_T0(REG(0));
472 gen_op_ldw_T0_T0(ctx); 490 gen_op_ldw_T0_T0(ctx);
473 - gen_op_movl_T0_rN(REG(B11_8)); 491 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
474 return; 492 return;
475 case 0x000e: /* mov.l @(R0,Rm),Rn */ 493 case 0x000e: /* mov.l @(R0,Rm),Rn */
476 - gen_op_movl_rN_T0(REG(B7_4)); 494 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
477 gen_op_add_rN_T0(REG(0)); 495 gen_op_add_rN_T0(REG(0));
478 gen_op_ldl_T0_T0(ctx); 496 gen_op_ldl_T0_T0(ctx);
479 - gen_op_movl_T0_rN(REG(B11_8)); 497 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
480 return; 498 return;
481 case 0x6008: /* swap.b Rm,Rn */ 499 case 0x6008: /* swap.b Rm,Rn */
482 - gen_op_movl_rN_T0(REG(B7_4)); 500 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
483 gen_op_swapb_T0(); 501 gen_op_swapb_T0();
484 - gen_op_movl_T0_rN(REG(B11_8)); 502 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
485 return; 503 return;
486 case 0x6009: /* swap.w Rm,Rn */ 504 case 0x6009: /* swap.w Rm,Rn */
487 - gen_op_movl_rN_T0(REG(B7_4)); 505 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
488 gen_op_swapw_T0(); 506 gen_op_swapw_T0();
489 - gen_op_movl_T0_rN(REG(B11_8)); 507 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
490 return; 508 return;
491 case 0x200d: /* xtrct Rm,Rn */ 509 case 0x200d: /* xtrct Rm,Rn */
492 - gen_op_movl_rN_T0(REG(B7_4));  
493 - gen_op_movl_rN_T1(REG(B11_8)); 510 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  511 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
494 gen_op_xtrct_T0_T1(); 512 gen_op_xtrct_T0_T1();
495 - gen_op_movl_T1_rN(REG(B11_8)); 513 + gen_movl_T_rN(cpu_T[1], REG(B11_8));
496 return; 514 return;
497 case 0x300c: /* add Rm,Rn */ 515 case 0x300c: /* add Rm,Rn */
498 - gen_op_movl_rN_T0(REG(B7_4)); 516 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
499 gen_op_add_T0_rN(REG(B11_8)); 517 gen_op_add_T0_rN(REG(B11_8));
500 return; 518 return;
501 case 0x300e: /* addc Rm,Rn */ 519 case 0x300e: /* addc Rm,Rn */
502 - gen_op_movl_rN_T0(REG(B7_4));  
503 - gen_op_movl_rN_T1(REG(B11_8)); 520 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  521 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
504 gen_op_addc_T0_T1(); 522 gen_op_addc_T0_T1();
505 - gen_op_movl_T1_rN(REG(B11_8)); 523 + gen_movl_T_rN(cpu_T[1], REG(B11_8));
506 return; 524 return;
507 case 0x300f: /* addv Rm,Rn */ 525 case 0x300f: /* addv Rm,Rn */
508 - gen_op_movl_rN_T0(REG(B7_4));  
509 - gen_op_movl_rN_T1(REG(B11_8)); 526 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  527 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
510 gen_op_addv_T0_T1(); 528 gen_op_addv_T0_T1();
511 - gen_op_movl_T1_rN(REG(B11_8)); 529 + gen_movl_T_rN(cpu_T[1], REG(B11_8));
512 return; 530 return;
513 case 0x2009: /* and Rm,Rn */ 531 case 0x2009: /* and Rm,Rn */
514 - gen_op_movl_rN_T0(REG(B7_4)); 532 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
515 gen_op_and_T0_rN(REG(B11_8)); 533 gen_op_and_T0_rN(REG(B11_8));
516 return; 534 return;
517 case 0x3000: /* cmp/eq Rm,Rn */ 535 case 0x3000: /* cmp/eq Rm,Rn */
518 - gen_op_movl_rN_T0(REG(B7_4));  
519 - gen_op_movl_rN_T1(REG(B11_8)); 536 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  537 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
520 gen_op_cmp_eq_T0_T1(); 538 gen_op_cmp_eq_T0_T1();
521 return; 539 return;
522 case 0x3003: /* cmp/ge Rm,Rn */ 540 case 0x3003: /* cmp/ge Rm,Rn */
523 - gen_op_movl_rN_T0(REG(B7_4));  
524 - gen_op_movl_rN_T1(REG(B11_8)); 541 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  542 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
525 gen_op_cmp_ge_T0_T1(); 543 gen_op_cmp_ge_T0_T1();
526 return; 544 return;
527 case 0x3007: /* cmp/gt Rm,Rn */ 545 case 0x3007: /* cmp/gt Rm,Rn */
528 - gen_op_movl_rN_T0(REG(B7_4));  
529 - gen_op_movl_rN_T1(REG(B11_8)); 546 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  547 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
530 gen_op_cmp_gt_T0_T1(); 548 gen_op_cmp_gt_T0_T1();
531 return; 549 return;
532 case 0x3006: /* cmp/hi Rm,Rn */ 550 case 0x3006: /* cmp/hi Rm,Rn */
533 - gen_op_movl_rN_T0(REG(B7_4));  
534 - gen_op_movl_rN_T1(REG(B11_8)); 551 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  552 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
535 gen_op_cmp_hi_T0_T1(); 553 gen_op_cmp_hi_T0_T1();
536 return; 554 return;
537 case 0x3002: /* cmp/hs Rm,Rn */ 555 case 0x3002: /* cmp/hs Rm,Rn */
538 - gen_op_movl_rN_T0(REG(B7_4));  
539 - gen_op_movl_rN_T1(REG(B11_8)); 556 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  557 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
540 gen_op_cmp_hs_T0_T1(); 558 gen_op_cmp_hs_T0_T1();
541 return; 559 return;
542 case 0x200c: /* cmp/str Rm,Rn */ 560 case 0x200c: /* cmp/str Rm,Rn */
543 - gen_op_movl_rN_T0(REG(B7_4));  
544 - gen_op_movl_rN_T1(REG(B11_8)); 561 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  562 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
545 gen_op_cmp_str_T0_T1(); 563 gen_op_cmp_str_T0_T1();
546 return; 564 return;
547 case 0x2007: /* div0s Rm,Rn */ 565 case 0x2007: /* div0s Rm,Rn */
548 - gen_op_movl_rN_T0(REG(B7_4));  
549 - gen_op_movl_rN_T1(REG(B11_8)); 566 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  567 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
550 gen_op_div0s_T0_T1(); 568 gen_op_div0s_T0_T1();
551 return; 569 return;
552 case 0x3004: /* div1 Rm,Rn */ 570 case 0x3004: /* div1 Rm,Rn */
553 - gen_op_movl_rN_T0(REG(B7_4));  
554 - gen_op_movl_rN_T1(REG(B11_8)); 571 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  572 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
555 gen_op_div1_T0_T1(); 573 gen_op_div1_T0_T1();
556 - gen_op_movl_T1_rN(REG(B11_8)); 574 + gen_movl_T_rN(cpu_T[1], REG(B11_8));
557 return; 575 return;
558 case 0x300d: /* dmuls.l Rm,Rn */ 576 case 0x300d: /* dmuls.l Rm,Rn */
559 - gen_op_movl_rN_T0(REG(B7_4));  
560 - gen_op_movl_rN_T1(REG(B11_8)); 577 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  578 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
561 gen_op_dmulsl_T0_T1(); 579 gen_op_dmulsl_T0_T1();
562 return; 580 return;
563 case 0x3005: /* dmulu.l Rm,Rn */ 581 case 0x3005: /* dmulu.l Rm,Rn */
564 - gen_op_movl_rN_T0(REG(B7_4));  
565 - gen_op_movl_rN_T1(REG(B11_8)); 582 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  583 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
566 gen_op_dmulul_T0_T1(); 584 gen_op_dmulul_T0_T1();
567 return; 585 return;
568 case 0x600e: /* exts.b Rm,Rn */ 586 case 0x600e: /* exts.b Rm,Rn */
569 - gen_op_movb_rN_T0(REG(B7_4));  
570 - gen_op_movl_T0_rN(REG(B11_8)); 587 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  588 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
  589 + tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
  590 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
571 return; 591 return;
572 case 0x600f: /* exts.w Rm,Rn */ 592 case 0x600f: /* exts.w Rm,Rn */
573 - gen_op_movw_rN_T0(REG(B7_4));  
574 - gen_op_movl_T0_rN(REG(B11_8)); 593 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  594 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
  595 + tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
  596 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
575 return; 597 return;
576 case 0x600c: /* extu.b Rm,Rn */ 598 case 0x600c: /* extu.b Rm,Rn */
577 - gen_op_movub_rN_T0(REG(B7_4));  
578 - gen_op_movl_T0_rN(REG(B11_8)); 599 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  600 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
  601 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
579 return; 602 return;
580 case 0x600d: /* extu.w Rm,Rn */ 603 case 0x600d: /* extu.w Rm,Rn */
581 - gen_op_movuw_rN_T0(REG(B7_4));  
582 - gen_op_movl_T0_rN(REG(B11_8)); 604 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  605 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
  606 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
583 return; 607 return;
584 case 0x000f: /* mac.l @Rm+,@Rn+ */ 608 case 0x000f: /* mac.l @Rm+,@Rn+ */
585 - gen_op_movl_rN_T0(REG(B11_8)); 609 + gen_movl_rN_T(cpu_T[0], REG(B11_8));
586 gen_op_ldl_T0_T0(ctx); 610 gen_op_ldl_T0_T0(ctx);
587 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 611 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
588 - gen_op_movl_rN_T0(REG(B7_4)); 612 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
589 gen_op_ldl_T0_T0(ctx); 613 gen_op_ldl_T0_T0(ctx);
590 gen_op_macl_T0_T1(); 614 gen_op_macl_T0_T1();
591 gen_op_inc4_rN(REG(B11_8)); 615 gen_op_inc4_rN(REG(B11_8));
592 gen_op_inc4_rN(REG(B7_4)); 616 gen_op_inc4_rN(REG(B7_4));
593 return; 617 return;
594 case 0x400f: /* mac.w @Rm+,@Rn+ */ 618 case 0x400f: /* mac.w @Rm+,@Rn+ */
595 - gen_op_movl_rN_T0(REG(B11_8)); 619 + gen_movl_rN_T(cpu_T[0], REG(B11_8));
596 gen_op_ldl_T0_T0(ctx); 620 gen_op_ldl_T0_T0(ctx);
597 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 621 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
598 - gen_op_movl_rN_T0(REG(B7_4)); 622 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
599 gen_op_ldl_T0_T0(ctx); 623 gen_op_ldl_T0_T0(ctx);
600 gen_op_macw_T0_T1(); 624 gen_op_macw_T0_T1();
601 gen_op_inc2_rN(REG(B11_8)); 625 gen_op_inc2_rN(REG(B11_8));
602 gen_op_inc2_rN(REG(B7_4)); 626 gen_op_inc2_rN(REG(B7_4));
603 return; 627 return;
604 case 0x0007: /* mul.l Rm,Rn */ 628 case 0x0007: /* mul.l Rm,Rn */
605 - gen_op_movl_rN_T0(REG(B7_4));  
606 - gen_op_movl_rN_T1(REG(B11_8)); 629 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  630 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
607 gen_op_mull_T0_T1(); 631 gen_op_mull_T0_T1();
608 return; 632 return;
609 case 0x200f: /* muls.w Rm,Rn */ 633 case 0x200f: /* muls.w Rm,Rn */
610 - gen_op_movw_rN_T0(REG(B7_4));  
611 - gen_op_movw_rN_T1(REG(B11_8)); 634 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  635 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
  636 + tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
  637 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
  638 + tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffff);
  639 + tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
612 gen_op_mulsw_T0_T1(); 640 gen_op_mulsw_T0_T1();
613 return; 641 return;
614 case 0x200e: /* mulu.w Rm,Rn */ 642 case 0x200e: /* mulu.w Rm,Rn */
615 - gen_op_movuw_rN_T0(REG(B7_4));  
616 - gen_op_movuw_rN_T1(REG(B11_8)); 643 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  644 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
  645 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
  646 + tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffff);
617 gen_op_muluw_T0_T1(); 647 gen_op_muluw_T0_T1();
618 return; 648 return;
619 case 0x600b: /* neg Rm,Rn */ 649 case 0x600b: /* neg Rm,Rn */
620 - gen_op_movl_rN_T0(REG(B7_4)); 650 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
621 gen_op_neg_T0(); 651 gen_op_neg_T0();
622 - gen_op_movl_T0_rN(REG(B11_8)); 652 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
623 return; 653 return;
624 case 0x600a: /* negc Rm,Rn */ 654 case 0x600a: /* negc Rm,Rn */
625 - gen_op_movl_rN_T0(REG(B7_4)); 655 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
626 gen_op_negc_T0(); 656 gen_op_negc_T0();
627 - gen_op_movl_T0_rN(REG(B11_8)); 657 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
628 return; 658 return;
629 case 0x6007: /* not Rm,Rn */ 659 case 0x6007: /* not Rm,Rn */
630 - gen_op_movl_rN_T0(REG(B7_4)); 660 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
631 gen_op_not_T0(); 661 gen_op_not_T0();
632 - gen_op_movl_T0_rN(REG(B11_8)); 662 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
633 return; 663 return;
634 case 0x200b: /* or Rm,Rn */ 664 case 0x200b: /* or Rm,Rn */
635 - gen_op_movl_rN_T0(REG(B7_4)); 665 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
636 gen_op_or_T0_rN(REG(B11_8)); 666 gen_op_or_T0_rN(REG(B11_8));
637 return; 667 return;
638 case 0x400c: /* shad Rm,Rn */ 668 case 0x400c: /* shad Rm,Rn */
639 - gen_op_movl_rN_T0(REG(B7_4));  
640 - gen_op_movl_rN_T1(REG(B11_8)); 669 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  670 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
641 gen_op_shad_T0_T1(); 671 gen_op_shad_T0_T1();
642 - gen_op_movl_T1_rN(REG(B11_8)); 672 + gen_movl_T_rN(cpu_T[1], REG(B11_8));
643 return; 673 return;
644 case 0x400d: /* shld Rm,Rn */ 674 case 0x400d: /* shld Rm,Rn */
645 - gen_op_movl_rN_T0(REG(B7_4));  
646 - gen_op_movl_rN_T1(REG(B11_8)); 675 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  676 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
647 gen_op_shld_T0_T1(); 677 gen_op_shld_T0_T1();
648 - gen_op_movl_T1_rN(REG(B11_8)); 678 + gen_movl_T_rN(cpu_T[1], REG(B11_8));
649 return; 679 return;
650 case 0x3008: /* sub Rm,Rn */ 680 case 0x3008: /* sub Rm,Rn */
651 - gen_op_movl_rN_T0(REG(B7_4)); 681 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
652 gen_op_sub_T0_rN(REG(B11_8)); 682 gen_op_sub_T0_rN(REG(B11_8));
653 return; 683 return;
654 case 0x300a: /* subc Rm,Rn */ 684 case 0x300a: /* subc Rm,Rn */
655 - gen_op_movl_rN_T0(REG(B7_4));  
656 - gen_op_movl_rN_T1(REG(B11_8)); 685 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  686 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
657 gen_op_subc_T0_T1(); 687 gen_op_subc_T0_T1();
658 - gen_op_movl_T1_rN(REG(B11_8)); 688 + gen_movl_T_rN(cpu_T[1], REG(B11_8));
659 return; 689 return;
660 case 0x300b: /* subv Rm,Rn */ 690 case 0x300b: /* subv Rm,Rn */
661 - gen_op_movl_rN_T0(REG(B7_4));  
662 - gen_op_movl_rN_T1(REG(B11_8)); 691 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  692 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
663 gen_op_subv_T0_T1(); 693 gen_op_subv_T0_T1();
664 - gen_op_movl_T1_rN(REG(B11_8)); 694 + gen_movl_T_rN(cpu_T[1], REG(B11_8));
665 return; 695 return;
666 case 0x2008: /* tst Rm,Rn */ 696 case 0x2008: /* tst Rm,Rn */
667 - gen_op_movl_rN_T0(REG(B7_4));  
668 - gen_op_movl_rN_T1(REG(B11_8)); 697 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
  698 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
669 gen_op_tst_T0_T1(); 699 gen_op_tst_T0_T1();
670 return; 700 return;
671 case 0x200a: /* xor Rm,Rn */ 701 case 0x200a: /* xor Rm,Rn */
672 - gen_op_movl_rN_T0(REG(B7_4)); 702 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
673 gen_op_xor_T0_rN(REG(B11_8)); 703 gen_op_xor_T0_rN(REG(B11_8));
674 return; 704 return;
675 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ 705 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
@@ -684,33 +714,33 @@ void _decode_opc(DisasContext * ctx) @@ -684,33 +714,33 @@ void _decode_opc(DisasContext * ctx)
684 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ 714 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
685 if (ctx->fpscr & FPSCR_SZ) { 715 if (ctx->fpscr & FPSCR_SZ) {
686 gen_op_fmov_drN_DT0(XREG(B7_4)); 716 gen_op_fmov_drN_DT0(XREG(B7_4));
687 - gen_op_movl_rN_T1(REG(B11_8)); 717 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
688 gen_op_stfq_DT0_T1(ctx); 718 gen_op_stfq_DT0_T1(ctx);
689 } else { 719 } else {
690 gen_op_fmov_frN_FT0(FREG(B7_4)); 720 gen_op_fmov_frN_FT0(FREG(B7_4));
691 - gen_op_movl_rN_T1(REG(B11_8)); 721 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
692 gen_op_stfl_FT0_T1(ctx); 722 gen_op_stfl_FT0_T1(ctx);
693 } 723 }
694 return; 724 return;
695 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ 725 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
696 if (ctx->fpscr & FPSCR_SZ) { 726 if (ctx->fpscr & FPSCR_SZ) {
697 - gen_op_movl_rN_T0(REG(B7_4)); 727 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
698 gen_op_ldfq_T0_DT0(ctx); 728 gen_op_ldfq_T0_DT0(ctx);
699 gen_op_fmov_DT0_drN(XREG(B11_8)); 729 gen_op_fmov_DT0_drN(XREG(B11_8));
700 } else { 730 } else {
701 - gen_op_movl_rN_T0(REG(B7_4)); 731 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
702 gen_op_ldfl_T0_FT0(ctx); 732 gen_op_ldfl_T0_FT0(ctx);
703 gen_op_fmov_FT0_frN(FREG(B11_8)); 733 gen_op_fmov_FT0_frN(FREG(B11_8));
704 } 734 }
705 return; 735 return;
706 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ 736 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
707 if (ctx->fpscr & FPSCR_SZ) { 737 if (ctx->fpscr & FPSCR_SZ) {
708 - gen_op_movl_rN_T0(REG(B7_4)); 738 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
709 gen_op_ldfq_T0_DT0(ctx); 739 gen_op_ldfq_T0_DT0(ctx);
710 gen_op_fmov_DT0_drN(XREG(B11_8)); 740 gen_op_fmov_DT0_drN(XREG(B11_8));
711 gen_op_inc8_rN(REG(B7_4)); 741 gen_op_inc8_rN(REG(B7_4));
712 } else { 742 } else {
713 - gen_op_movl_rN_T0(REG(B7_4)); 743 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
714 gen_op_ldfl_T0_FT0(ctx); 744 gen_op_ldfl_T0_FT0(ctx);
715 gen_op_fmov_FT0_frN(FREG(B11_8)); 745 gen_op_fmov_FT0_frN(FREG(B11_8));
716 gen_op_inc4_rN(REG(B7_4)); 746 gen_op_inc4_rN(REG(B7_4));
@@ -720,14 +750,14 @@ void _decode_opc(DisasContext * ctx) @@ -720,14 +750,14 @@ void _decode_opc(DisasContext * ctx)
720 if (ctx->fpscr & FPSCR_SZ) { 750 if (ctx->fpscr & FPSCR_SZ) {
721 gen_op_dec8_rN(REG(B11_8)); 751 gen_op_dec8_rN(REG(B11_8));
722 gen_op_fmov_drN_DT0(XREG(B7_4)); 752 gen_op_fmov_drN_DT0(XREG(B7_4));
723 - gen_op_movl_rN_T1(REG(B11_8)); 753 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
724 gen_op_inc8_rN(REG(B11_8)); 754 gen_op_inc8_rN(REG(B11_8));
725 gen_op_stfq_DT0_T1(ctx); 755 gen_op_stfq_DT0_T1(ctx);
726 gen_op_dec8_rN(REG(B11_8)); 756 gen_op_dec8_rN(REG(B11_8));
727 } else { 757 } else {
728 gen_op_dec4_rN(REG(B11_8)); 758 gen_op_dec4_rN(REG(B11_8));
729 gen_op_fmov_frN_FT0(FREG(B7_4)); 759 gen_op_fmov_frN_FT0(FREG(B7_4));
730 - gen_op_movl_rN_T1(REG(B11_8)); 760 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
731 gen_op_inc4_rN(REG(B11_8)); 761 gen_op_inc4_rN(REG(B11_8));
732 gen_op_stfl_FT0_T1(ctx); 762 gen_op_stfl_FT0_T1(ctx);
733 gen_op_dec4_rN(REG(B11_8)); 763 gen_op_dec4_rN(REG(B11_8));
@@ -735,12 +765,12 @@ void _decode_opc(DisasContext * ctx) @@ -735,12 +765,12 @@ void _decode_opc(DisasContext * ctx)
735 return; 765 return;
736 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ 766 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
737 if (ctx->fpscr & FPSCR_SZ) { 767 if (ctx->fpscr & FPSCR_SZ) {
738 - gen_op_movl_rN_T0(REG(B7_4)); 768 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
739 gen_op_add_rN_T0(REG(0)); 769 gen_op_add_rN_T0(REG(0));
740 gen_op_ldfq_T0_DT0(ctx); 770 gen_op_ldfq_T0_DT0(ctx);
741 gen_op_fmov_DT0_drN(XREG(B11_8)); 771 gen_op_fmov_DT0_drN(XREG(B11_8));
742 } else { 772 } else {
743 - gen_op_movl_rN_T0(REG(B7_4)); 773 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
744 gen_op_add_rN_T0(REG(0)); 774 gen_op_add_rN_T0(REG(0));
745 gen_op_ldfl_T0_FT0(ctx); 775 gen_op_ldfl_T0_FT0(ctx);
746 gen_op_fmov_FT0_frN(FREG(B11_8)); 776 gen_op_fmov_FT0_frN(FREG(B11_8));
@@ -749,12 +779,12 @@ void _decode_opc(DisasContext * ctx) @@ -749,12 +779,12 @@ void _decode_opc(DisasContext * ctx)
749 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ 779 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
750 if (ctx->fpscr & FPSCR_SZ) { 780 if (ctx->fpscr & FPSCR_SZ) {
751 gen_op_fmov_drN_DT0(XREG(B7_4)); 781 gen_op_fmov_drN_DT0(XREG(B7_4));
752 - gen_op_movl_rN_T1(REG(B11_8)); 782 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
753 gen_op_add_rN_T1(REG(0)); 783 gen_op_add_rN_T1(REG(0));
754 gen_op_stfq_DT0_T1(ctx); 784 gen_op_stfq_DT0_T1(ctx);
755 } else { 785 } else {
756 gen_op_fmov_frN_FT0(FREG(B7_4)); 786 gen_op_fmov_frN_FT0(FREG(B7_4));
757 - gen_op_movl_rN_T1(REG(B11_8)); 787 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
758 gen_op_add_rN_T1(REG(0)); 788 gen_op_add_rN_T1(REG(0));
759 gen_op_stfl_FT0_T1(ctx); 789 gen_op_stfl_FT0_T1(ctx);
760 } 790 }
@@ -811,7 +841,7 @@ void _decode_opc(DisasContext * ctx) @@ -811,7 +841,7 @@ void _decode_opc(DisasContext * ctx)
811 gen_op_and_imm_rN(B7_0, REG(0)); 841 gen_op_and_imm_rN(B7_0, REG(0));
812 return; 842 return;
813 case 0xcd00: /* and.b #imm,@(R0,GBR) */ 843 case 0xcd00: /* and.b #imm,@(R0,GBR) */
814 - gen_op_movl_rN_T0(REG(0)); 844 + gen_movl_rN_T(cpu_T[0], REG(0));
815 gen_op_addl_GBR_T0(); 845 gen_op_addl_GBR_T0();
816 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 846 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
817 gen_op_ldub_T0_T0(ctx); 847 gen_op_ldub_T0_T0(ctx);
@@ -841,81 +871,81 @@ void _decode_opc(DisasContext * ctx) @@ -841,81 +871,81 @@ void _decode_opc(DisasContext * ctx)
841 ctx->flags |= DELAY_SLOT_CONDITIONAL; 871 ctx->flags |= DELAY_SLOT_CONDITIONAL;
842 return; 872 return;
843 case 0x8800: /* cmp/eq #imm,R0 */ 873 case 0x8800: /* cmp/eq #imm,R0 */
844 - gen_op_movl_rN_T0(REG(0)); 874 + gen_movl_rN_T(cpu_T[0], REG(0));
845 gen_op_cmp_eq_imm_T0(B7_0s); 875 gen_op_cmp_eq_imm_T0(B7_0s);
846 return; 876 return;
847 case 0xc400: /* mov.b @(disp,GBR),R0 */ 877 case 0xc400: /* mov.b @(disp,GBR),R0 */
848 gen_op_stc_gbr_T0(); 878 gen_op_stc_gbr_T0();
849 gen_op_addl_imm_T0(B7_0); 879 gen_op_addl_imm_T0(B7_0);
850 gen_op_ldb_T0_T0(ctx); 880 gen_op_ldb_T0_T0(ctx);
851 - gen_op_movl_T0_rN(REG(0)); 881 + gen_movl_T_rN(cpu_T[0], REG(0));
852 return; 882 return;
853 case 0xc500: /* mov.w @(disp,GBR),R0 */ 883 case 0xc500: /* mov.w @(disp,GBR),R0 */
854 gen_op_stc_gbr_T0(); 884 gen_op_stc_gbr_T0();
855 gen_op_addl_imm_T0(B7_0 * 2); 885 gen_op_addl_imm_T0(B7_0 * 2);
856 gen_op_ldw_T0_T0(ctx); 886 gen_op_ldw_T0_T0(ctx);
857 - gen_op_movl_T0_rN(REG(0)); 887 + gen_movl_T_rN(cpu_T[0], REG(0));
858 return; 888 return;
859 case 0xc600: /* mov.l @(disp,GBR),R0 */ 889 case 0xc600: /* mov.l @(disp,GBR),R0 */
860 gen_op_stc_gbr_T0(); 890 gen_op_stc_gbr_T0();
861 gen_op_addl_imm_T0(B7_0 * 4); 891 gen_op_addl_imm_T0(B7_0 * 4);
862 gen_op_ldl_T0_T0(ctx); 892 gen_op_ldl_T0_T0(ctx);
863 - gen_op_movl_T0_rN(REG(0)); 893 + gen_movl_T_rN(cpu_T[0], REG(0));
864 return; 894 return;
865 case 0xc000: /* mov.b R0,@(disp,GBR) */ 895 case 0xc000: /* mov.b R0,@(disp,GBR) */
866 gen_op_stc_gbr_T0(); 896 gen_op_stc_gbr_T0();
867 gen_op_addl_imm_T0(B7_0); 897 gen_op_addl_imm_T0(B7_0);
868 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 898 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
869 - gen_op_movl_rN_T0(REG(0)); 899 + gen_movl_rN_T(cpu_T[0], REG(0));
870 gen_op_stb_T0_T1(ctx); 900 gen_op_stb_T0_T1(ctx);
871 return; 901 return;
872 case 0xc100: /* mov.w R0,@(disp,GBR) */ 902 case 0xc100: /* mov.w R0,@(disp,GBR) */
873 gen_op_stc_gbr_T0(); 903 gen_op_stc_gbr_T0();
874 gen_op_addl_imm_T0(B7_0 * 2); 904 gen_op_addl_imm_T0(B7_0 * 2);
875 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 905 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
876 - gen_op_movl_rN_T0(REG(0)); 906 + gen_movl_rN_T(cpu_T[0], REG(0));
877 gen_op_stw_T0_T1(ctx); 907 gen_op_stw_T0_T1(ctx);
878 return; 908 return;
879 case 0xc200: /* mov.l R0,@(disp,GBR) */ 909 case 0xc200: /* mov.l R0,@(disp,GBR) */
880 gen_op_stc_gbr_T0(); 910 gen_op_stc_gbr_T0();
881 gen_op_addl_imm_T0(B7_0 * 4); 911 gen_op_addl_imm_T0(B7_0 * 4);
882 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 912 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
883 - gen_op_movl_rN_T0(REG(0)); 913 + gen_movl_rN_T(cpu_T[0], REG(0));
884 gen_op_stl_T0_T1(ctx); 914 gen_op_stl_T0_T1(ctx);
885 return; 915 return;
886 case 0x8000: /* mov.b R0,@(disp,Rn) */ 916 case 0x8000: /* mov.b R0,@(disp,Rn) */
887 - gen_op_movl_rN_T0(REG(0));  
888 - gen_op_movl_rN_T1(REG(B7_4)); 917 + gen_movl_rN_T(cpu_T[0], REG(0));
  918 + gen_movl_rN_T(cpu_T[1], REG(B7_4));
889 gen_op_addl_imm_T1(B3_0); 919 gen_op_addl_imm_T1(B3_0);
890 gen_op_stb_T0_T1(ctx); 920 gen_op_stb_T0_T1(ctx);
891 return; 921 return;
892 case 0x8100: /* mov.w R0,@(disp,Rn) */ 922 case 0x8100: /* mov.w R0,@(disp,Rn) */
893 - gen_op_movl_rN_T0(REG(0));  
894 - gen_op_movl_rN_T1(REG(B7_4)); 923 + gen_movl_rN_T(cpu_T[0], REG(0));
  924 + gen_movl_rN_T(cpu_T[1], REG(B7_4));
895 gen_op_addl_imm_T1(B3_0 * 2); 925 gen_op_addl_imm_T1(B3_0 * 2);
896 gen_op_stw_T0_T1(ctx); 926 gen_op_stw_T0_T1(ctx);
897 return; 927 return;
898 case 0x8400: /* mov.b @(disp,Rn),R0 */ 928 case 0x8400: /* mov.b @(disp,Rn),R0 */
899 - gen_op_movl_rN_T0(REG(B7_4)); 929 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
900 gen_op_addl_imm_T0(B3_0); 930 gen_op_addl_imm_T0(B3_0);
901 gen_op_ldb_T0_T0(ctx); 931 gen_op_ldb_T0_T0(ctx);
902 - gen_op_movl_T0_rN(REG(0)); 932 + gen_movl_T_rN(cpu_T[0], REG(0));
903 return; 933 return;
904 case 0x8500: /* mov.w @(disp,Rn),R0 */ 934 case 0x8500: /* mov.w @(disp,Rn),R0 */
905 - gen_op_movl_rN_T0(REG(B7_4)); 935 + gen_movl_rN_T(cpu_T[0], REG(B7_4));
906 gen_op_addl_imm_T0(B3_0 * 2); 936 gen_op_addl_imm_T0(B3_0 * 2);
907 gen_op_ldw_T0_T0(ctx); 937 gen_op_ldw_T0_T0(ctx);
908 - gen_op_movl_T0_rN(REG(0)); 938 + gen_movl_T_rN(cpu_T[0], REG(0));
909 return; 939 return;
910 case 0xc700: /* mova @(disp,PC),R0 */ 940 case 0xc700: /* mova @(disp,PC),R0 */
911 - gen_op_movl_imm_rN(((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3, 941 + gen_movl_imm_rN(((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3,
912 REG(0)); 942 REG(0));
913 return; 943 return;
914 case 0xcb00: /* or #imm,R0 */ 944 case 0xcb00: /* or #imm,R0 */
915 gen_op_or_imm_rN(B7_0, REG(0)); 945 gen_op_or_imm_rN(B7_0, REG(0));
916 return; 946 return;
917 case 0xcf00: /* or.b #imm,@(R0,GBR) */ 947 case 0xcf00: /* or.b #imm,@(R0,GBR) */
918 - gen_op_movl_rN_T0(REG(0)); 948 + gen_movl_rN_T(cpu_T[0], REG(0));
919 gen_op_addl_GBR_T0(); 949 gen_op_addl_GBR_T0();
920 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 950 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
921 gen_op_ldub_T0_T0(ctx); 951 gen_op_ldub_T0_T0(ctx);
@@ -931,7 +961,7 @@ void _decode_opc(DisasContext * ctx) @@ -931,7 +961,7 @@ void _decode_opc(DisasContext * ctx)
931 gen_op_tst_imm_rN(B7_0, REG(0)); 961 gen_op_tst_imm_rN(B7_0, REG(0));
932 return; 962 return;
933 case 0xcc00: /* tst.b #imm,@(R0,GBR) */ 963 case 0xcc00: /* tst.b #imm,@(R0,GBR) */
934 - gen_op_movl_rN_T0(REG(0)); 964 + gen_movl_rN_T(cpu_T[0], REG(0));
935 gen_op_addl_GBR_T0(); 965 gen_op_addl_GBR_T0();
936 gen_op_ldub_T0_T0(ctx); 966 gen_op_ldub_T0_T0(ctx);
937 gen_op_tst_imm_T0(B7_0); 967 gen_op_tst_imm_T0(B7_0);
@@ -940,7 +970,7 @@ void _decode_opc(DisasContext * ctx) @@ -940,7 +970,7 @@ void _decode_opc(DisasContext * ctx)
940 gen_op_xor_imm_rN(B7_0, REG(0)); 970 gen_op_xor_imm_rN(B7_0, REG(0));
941 return; 971 return;
942 case 0xce00: /* xor.b #imm,@(R0,GBR) */ 972 case 0xce00: /* xor.b #imm,@(R0,GBR) */
943 - gen_op_movl_rN_T0(REG(0)); 973 + gen_movl_rN_T(cpu_T[0], REG(0));
944 gen_op_addl_GBR_T0(); 974 gen_op_addl_GBR_T0();
945 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 975 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
946 gen_op_ldub_T0_T0(ctx); 976 gen_op_ldub_T0_T0(ctx);
@@ -951,21 +981,23 @@ void _decode_opc(DisasContext * ctx) @@ -951,21 +981,23 @@ void _decode_opc(DisasContext * ctx)
951 981
952 switch (ctx->opcode & 0xf08f) { 982 switch (ctx->opcode & 0xf08f) {
953 case 0x408e: /* ldc Rm,Rn_BANK */ 983 case 0x408e: /* ldc Rm,Rn_BANK */
954 - gen_op_movl_rN_rN(REG(B11_8), ALTREG(B6_4)); 984 + gen_movl_rN_T(cpu_T[0], REG(B11_8));
  985 + gen_movl_T_rN(cpu_T[0], ALTREG(B6_4));
955 return; 986 return;
956 case 0x4087: /* ldc.l @Rm+,Rn_BANK */ 987 case 0x4087: /* ldc.l @Rm+,Rn_BANK */
957 - gen_op_movl_rN_T0(REG(B11_8)); 988 + gen_movl_rN_T(cpu_T[0], REG(B11_8));
958 gen_op_ldl_T0_T0(ctx); 989 gen_op_ldl_T0_T0(ctx);
959 - gen_op_movl_T0_rN(ALTREG(B6_4)); 990 + gen_movl_T_rN(cpu_T[0], ALTREG(B6_4));
960 gen_op_inc4_rN(REG(B11_8)); 991 gen_op_inc4_rN(REG(B11_8));
961 return; 992 return;
962 case 0x0082: /* stc Rm_BANK,Rn */ 993 case 0x0082: /* stc Rm_BANK,Rn */
963 - gen_op_movl_rN_rN(ALTREG(B6_4), REG(B11_8)); 994 + gen_movl_rN_T(cpu_T[0], ALTREG(B6_4));
  995 + gen_movl_T_rN(cpu_T[0], REG(B11_8));
964 return; 996 return;
965 case 0x4083: /* stc.l Rm_BANK,@-Rn */ 997 case 0x4083: /* stc.l Rm_BANK,@-Rn */
966 gen_op_dec4_rN(REG(B11_8)); 998 gen_op_dec4_rN(REG(B11_8));
967 - gen_op_movl_rN_T1(REG(B11_8));  
968 - gen_op_movl_rN_T0(ALTREG(B6_4)); 999 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
  1000 + gen_movl_rN_T(cpu_T[0], ALTREG(B6_4));
969 gen_op_inc4_rN(REG(B11_8)); 1001 gen_op_inc4_rN(REG(B11_8));
970 gen_op_stl_T0_T1(ctx); 1002 gen_op_stl_T0_T1(ctx);
971 gen_op_dec4_rN(REG(B11_8)); 1003 gen_op_dec4_rN(REG(B11_8));
@@ -974,61 +1006,61 @@ void _decode_opc(DisasContext * ctx) @@ -974,61 +1006,61 @@ void _decode_opc(DisasContext * ctx)
974 1006
975 switch (ctx->opcode & 0xf0ff) { 1007 switch (ctx->opcode & 0xf0ff) {
976 case 0x0023: /* braf Rn */ 1008 case 0x0023: /* braf Rn */
977 - CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); 1009 + CHECK_NOT_DELAY_SLOT gen_movl_rN_T(cpu_T[0], REG(B11_8));
978 gen_op_braf_T0(ctx->pc + 4); 1010 gen_op_braf_T0(ctx->pc + 4);
979 ctx->flags |= DELAY_SLOT; 1011 ctx->flags |= DELAY_SLOT;
980 ctx->delayed_pc = (uint32_t) - 1; 1012 ctx->delayed_pc = (uint32_t) - 1;
981 return; 1013 return;
982 case 0x0003: /* bsrf Rn */ 1014 case 0x0003: /* bsrf Rn */
983 - CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); 1015 + CHECK_NOT_DELAY_SLOT gen_movl_rN_T(cpu_T[0], REG(B11_8));
984 gen_op_bsrf_T0(ctx->pc + 4); 1016 gen_op_bsrf_T0(ctx->pc + 4);
985 ctx->flags |= DELAY_SLOT; 1017 ctx->flags |= DELAY_SLOT;
986 ctx->delayed_pc = (uint32_t) - 1; 1018 ctx->delayed_pc = (uint32_t) - 1;
987 return; 1019 return;
988 case 0x4015: /* cmp/pl Rn */ 1020 case 0x4015: /* cmp/pl Rn */
989 - gen_op_movl_rN_T0(REG(B11_8)); 1021 + gen_movl_rN_T(cpu_T[0], REG(B11_8));
990 gen_op_cmp_pl_T0(); 1022 gen_op_cmp_pl_T0();
991 return; 1023 return;
992 case 0x4011: /* cmp/pz Rn */ 1024 case 0x4011: /* cmp/pz Rn */
993 - gen_op_movl_rN_T0(REG(B11_8)); 1025 + gen_movl_rN_T(cpu_T[0], REG(B11_8));
994 gen_op_cmp_pz_T0(); 1026 gen_op_cmp_pz_T0();
995 return; 1027 return;
996 case 0x4010: /* dt Rn */ 1028 case 0x4010: /* dt Rn */
997 gen_op_dt_rN(REG(B11_8)); 1029 gen_op_dt_rN(REG(B11_8));
998 return; 1030 return;
999 case 0x402b: /* jmp @Rn */ 1031 case 0x402b: /* jmp @Rn */
1000 - CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); 1032 + CHECK_NOT_DELAY_SLOT gen_movl_rN_T(cpu_T[0], REG(B11_8));
1001 gen_op_jmp_T0(); 1033 gen_op_jmp_T0();
1002 ctx->flags |= DELAY_SLOT; 1034 ctx->flags |= DELAY_SLOT;
1003 ctx->delayed_pc = (uint32_t) - 1; 1035 ctx->delayed_pc = (uint32_t) - 1;
1004 return; 1036 return;
1005 case 0x400b: /* jsr @Rn */ 1037 case 0x400b: /* jsr @Rn */
1006 - CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); 1038 + CHECK_NOT_DELAY_SLOT gen_movl_rN_T(cpu_T[0], REG(B11_8));
1007 gen_op_jsr_T0(ctx->pc + 4); 1039 gen_op_jsr_T0(ctx->pc + 4);
1008 ctx->flags |= DELAY_SLOT; 1040 ctx->flags |= DELAY_SLOT;
1009 ctx->delayed_pc = (uint32_t) - 1; 1041 ctx->delayed_pc = (uint32_t) - 1;
1010 return; 1042 return;
1011 #define LDST(reg,ldnum,ldpnum,ldop,stnum,stpnum,stop,extrald) \ 1043 #define LDST(reg,ldnum,ldpnum,ldop,stnum,stpnum,stop,extrald) \
1012 case ldnum: \ 1044 case ldnum: \
1013 - gen_op_movl_rN_T0 (REG(B11_8)); \ 1045 + gen_movl_rN_T (cpu_T[0], REG(B11_8)); \
1014 gen_op_##ldop##_T0_##reg (); \ 1046 gen_op_##ldop##_T0_##reg (); \
1015 extrald \ 1047 extrald \
1016 return; \ 1048 return; \
1017 case ldpnum: \ 1049 case ldpnum: \
1018 - gen_op_movl_rN_T0 (REG(B11_8)); \ 1050 + gen_movl_rN_T (cpu_T[0], REG(B11_8)); \
1019 gen_op_ldl_T0_T0 (ctx); \ 1051 gen_op_ldl_T0_T0 (ctx); \
1020 gen_op_inc4_rN (REG(B11_8)); \ 1052 gen_op_inc4_rN (REG(B11_8)); \
1021 gen_op_##ldop##_T0_##reg (); \ 1053 gen_op_##ldop##_T0_##reg (); \
1022 extrald \ 1054 extrald \
1023 return; \ 1055 return; \
1024 case stnum: \ 1056 case stnum: \
1025 - gen_op_##stop##_##reg##_T0 (); \  
1026 - gen_op_movl_T0_rN (REG(B11_8)); \ 1057 + gen_op_##stop##_##reg##_T0 (); \
  1058 + gen_movl_T_rN (cpu_T[0], REG(B11_8)); \
1027 return; \ 1059 return; \
1028 case stpnum: \ 1060 case stpnum: \
1029 gen_op_##stop##_##reg##_T0 (); \ 1061 gen_op_##stop##_##reg##_T0 (); \
1030 gen_op_dec4_rN (REG(B11_8)); \ 1062 gen_op_dec4_rN (REG(B11_8)); \
1031 - gen_op_movl_rN_T1 (REG(B11_8)); \ 1063 + gen_movl_rN_T (cpu_T[1], REG(B11_8)); \
1032 gen_op_inc4_rN (REG(B11_8)); \ 1064 gen_op_inc4_rN (REG(B11_8)); \
1033 gen_op_stl_T0_T1 (ctx); \ 1065 gen_op_stl_T0_T1 (ctx); \
1034 gen_op_dec4_rN (REG(B11_8)); \ 1066 gen_op_dec4_rN (REG(B11_8)); \
@@ -1047,23 +1079,23 @@ void _decode_opc(DisasContext * ctx) @@ -1047,23 +1079,23 @@ void _decode_opc(DisasContext * ctx)
1047 LDST(fpscr, 0x406a, 0x4066, lds, 0x006a, 0x4062, sts, ctx->bstate = 1079 LDST(fpscr, 0x406a, 0x4066, lds, 0x006a, 0x4062, sts, ctx->bstate =
1048 BS_STOP;) 1080 BS_STOP;)
1049 case 0x00c3: /* movca.l R0,@Rm */ 1081 case 0x00c3: /* movca.l R0,@Rm */
1050 - gen_op_movl_rN_T0(REG(0));  
1051 - gen_op_movl_rN_T1(REG(B11_8)); 1082 + gen_movl_rN_T(cpu_T[0], REG(0));
  1083 + gen_movl_rN_T(cpu_T[1], REG(B11_8));
1052 gen_op_stl_T0_T1(ctx); 1084 gen_op_stl_T0_T1(ctx);
1053 return; 1085 return;
1054 case 0x0029: /* movt Rn */ 1086 case 0x0029: /* movt Rn */
1055 gen_op_movt_rN(REG(B11_8)); 1087 gen_op_movt_rN(REG(B11_8));
1056 return; 1088 return;
1057 case 0x0093: /* ocbi @Rn */ 1089 case 0x0093: /* ocbi @Rn */
1058 - gen_op_movl_rN_T0(REG(B11_8)); 1090 + gen_movl_rN_T(cpu_T[0], REG(B11_8));
1059 gen_op_ldl_T0_T0(ctx); 1091 gen_op_ldl_T0_T0(ctx);
1060 return; 1092 return;
1061 case 0x00a3: /* ocbp @Rn */ 1093 case 0x00a3: /* ocbp @Rn */
1062 - gen_op_movl_rN_T0(REG(B11_8)); 1094 + gen_movl_rN_T(cpu_T[0], REG(B11_8));
1063 gen_op_ldl_T0_T0(ctx); 1095 gen_op_ldl_T0_T0(ctx);
1064 return; 1096 return;
1065 case 0x00b3: /* ocbwb @Rn */ 1097 case 0x00b3: /* ocbwb @Rn */
1066 - gen_op_movl_rN_T0(REG(B11_8)); 1098 + gen_movl_rN_T(cpu_T[0], REG(B11_8));
1067 gen_op_ldl_T0_T0(ctx); 1099 gen_op_ldl_T0_T0(ctx);
1068 return; 1100 return;
1069 case 0x0083: /* pref @Rn */ 1101 case 0x0083: /* pref @Rn */
@@ -1109,7 +1141,7 @@ void _decode_opc(DisasContext * ctx) @@ -1109,7 +1141,7 @@ void _decode_opc(DisasContext * ctx)
1109 gen_op_shlr16_Rn(REG(B11_8)); 1141 gen_op_shlr16_Rn(REG(B11_8));
1110 return; 1142 return;
1111 case 0x401b: /* tas.b @Rn */ 1143 case 0x401b: /* tas.b @Rn */
1112 - gen_op_movl_rN_T0(REG(B11_8)); 1144 + gen_movl_rN_T(cpu_T[0], REG(B11_8));
1113 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 1145 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
1114 gen_op_ldub_T0_T0(ctx); 1146 gen_op_ldub_T0_T0(ctx);
1115 gen_op_cmp_eq_imm_T0(0); 1147 gen_op_cmp_eq_imm_T0(0);