gwj / at91sam9263 · Commits

Commit 8f6f6026f14581fe09b65c2b31c0052577bf5b2f

Authored by ths
1 parent 406f82e8

Use FORCE_RET, scrap RETURN which was implemented in target-specific code. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3560 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 418 additions and 424 deletions
target-mips/exec.h
  View file @8f6f602
... ... @@ -43,12 +43,6 @@ register target_ulong T2 asm(AREG3);
43 43 #define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
44 44 #endif
45 45  
46   -#if defined (DEBUG_OP)
47   -# define RETURN() __asm__ __volatile__("nop" : : : "memory");
48   -#else
49   -# define RETURN() __asm__ __volatile__("" : : : "memory");
50   -#endif
51   -
52 46 #include "cpu.h"
53 47 #include "exec-all.h"
54 48  
... ...
target-mips/fop_template.c
  View file @8f6f602
... ... @@ -25,14 +25,14 @@
25 25 void glue(glue(op_load_fpr_,tregname), FREG) (void) \
26 26 { \
27 27 treg = env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX]; \
28   - RETURN(); \
  28 + FORCE_RET(); \
29 29 }
30 30  
31 31 #define OP_WSTORE_FREG(treg, tregname, FREG) \
32 32 void glue(glue(op_store_fpr_,tregname), FREG) (void) \
33 33 { \
34 34 env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX] = treg; \
35   - RETURN(); \
  35 + FORCE_RET(); \
36 36 }
37 37  
38 38 /* WT0 = FREG.w: op_load_fpr_WT0_fprFREG */
... ... @@ -54,7 +54,7 @@ OP_WSTORE_FREG(WT2, WT2_fpr, FREG)
54 54 else \
55 55 treg = (uint64_t)(env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX]) << 32 | \
56 56 env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX]; \
57   - RETURN(); \
  57 + FORCE_RET(); \
58 58 }
59 59  
60 60 #define OP_DSTORE_FREG(treg, tregname, FREG) \
... ... @@ -66,7 +66,7 @@ OP_WSTORE_FREG(WT2, WT2_fpr, FREG)
66 66 env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX] = treg >> 32; \
67 67 env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX] = treg; \
68 68 } \
69   - RETURN(); \
  69 + FORCE_RET(); \
70 70 }
71 71  
72 72 OP_DLOAD_FREG(DT0, DT0_fpr, FREG)
... ... @@ -82,14 +82,14 @@ OP_DSTORE_FREG(DT2, DT2_fpr, FREG)
82 82 void glue(glue(op_load_fpr_,tregname), FREG) (void) \
83 83 { \
84 84 treg = env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX]; \
85   - RETURN(); \
  85 + FORCE_RET(); \
86 86 }
87 87  
88 88 #define OP_PSSTORE_FREG(treg, tregname, FREG) \
89 89 void glue(glue(op_store_fpr_,tregname), FREG) (void) \
90 90 { \
91 91 env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX] = treg; \
92   - RETURN(); \
  92 + FORCE_RET(); \
93 93 }
94 94  
95 95 OP_PSLOAD_FREG(WTH0, WTH0_fpr, FREG)
... ... @@ -109,12 +109,12 @@ OP_PSSTORE_FREG(WTH2, WTH2_fpr, FREG)
109 109 void glue(op_set, tregname)(void) \
110 110 { \
111 111 treg = PARAM1; \
112   - RETURN(); \
  112 + FORCE_RET(); \
113 113 } \
114 114 void glue(op_reset, tregname)(void) \
115 115 { \
116 116 treg = 0; \
117   - RETURN(); \
  117 + FORCE_RET(); \
118 118 }
119 119  
120 120 SET_RESET(WT0, _WT0)
... ...
target-mips/op.c
  View file @8f6f602
... ... @@ -250,31 +250,31 @@
250 250 void op_dup_T0 (void)
251 251 {
252 252 T2 = T0;
253   - RETURN();
  253 + FORCE_RET();
254 254 }
255 255  
256 256 void op_load_HI (void)
257 257 {
258 258 T0 = env->HI[PARAM1][env->current_tc];
259   - RETURN();
  259 + FORCE_RET();
260 260 }
261 261  
262 262 void op_store_HI (void)
263 263 {
264 264 env->HI[PARAM1][env->current_tc] = T0;
265   - RETURN();
  265 + FORCE_RET();
266 266 }
267 267  
268 268 void op_load_LO (void)
269 269 {
270 270 T0 = env->LO[PARAM1][env->current_tc];
271   - RETURN();
  271 + FORCE_RET();
272 272 }
273 273  
274 274 void op_store_LO (void)
275 275 {
276 276 env->LO[PARAM1][env->current_tc] = T0;
277   - RETURN();
  277 + FORCE_RET();
278 278 }
279 279  
280 280 /* Load and store */
... ... @@ -308,14 +308,14 @@ void op_addr_add (void)
308 308 else
309 309 #endif
310 310 T0 += T1;
311   - RETURN();
  311 + FORCE_RET();
312 312 }
313 313  
314 314 /* Arithmetic */
315 315 void op_add (void)
316 316 {
317 317 T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
318   - RETURN();
  318 + FORCE_RET();
319 319 }
320 320  
321 321 void op_addo (void)
... ... @@ -329,13 +329,13 @@ void op_addo (void)
329 329 CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
330 330 }
331 331 T0 = (int32_t)T0;
332   - RETURN();
  332 + FORCE_RET();
333 333 }
334 334  
335 335 void op_sub (void)
336 336 {
337 337 T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
338   - RETURN();
  338 + FORCE_RET();
339 339 }
340 340  
341 341 void op_subo (void)
... ... @@ -349,20 +349,20 @@ void op_subo (void)
349 349 CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
350 350 }
351 351 T0 = (int32_t)T0;
352   - RETURN();
  352 + FORCE_RET();
353 353 }
354 354  
355 355 void op_mul (void)
356 356 {
357 357 T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
358   - RETURN();
  358 + FORCE_RET();
359 359 }
360 360  
361 361 #if HOST_LONG_BITS < 64
362 362 void op_div (void)
363 363 {
364 364 CALL_FROM_TB0(do_div);
365   - RETURN();
  365 + FORCE_RET();
366 366 }
367 367 #else
368 368 void op_div (void)
... ... @@ -371,7 +371,7 @@ void op_div (void)
371 371 env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
372 372 env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
373 373 }
374   - RETURN();
  374 + FORCE_RET();
375 375 }
376 376 #endif
377 377  
... ... @@ -381,7 +381,7 @@ void op_divu (void)
381 381 env->LO[0][env->current_tc] = (int32_t)((uint32_t)T0 / (uint32_t)T1);
382 382 env->HI[0][env->current_tc] = (int32_t)((uint32_t)T0 % (uint32_t)T1);
383 383 }
384   - RETURN();
  384 + FORCE_RET();
385 385 }
386 386  
387 387 #if defined(TARGET_MIPS64)
... ... @@ -389,7 +389,7 @@ void op_divu (void)
389 389 void op_dadd (void)
390 390 {
391 391 T0 += T1;
392   - RETURN();
  392 + FORCE_RET();
393 393 }
394 394  
395 395 void op_daddo (void)
... ... @@ -402,13 +402,13 @@ void op_daddo (void)
402 402 /* operands of same sign, result different sign */
403 403 CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
404 404 }
405   - RETURN();
  405 + FORCE_RET();
406 406 }
407 407  
408 408 void op_dsub (void)
409 409 {
410 410 T0 -= T1;
411   - RETURN();
  411 + FORCE_RET();
412 412 }
413 413  
414 414 void op_dsubo (void)
... ... @@ -421,27 +421,27 @@ void op_dsubo (void)
421 421 /* operands of different sign, first operand and result different sign */
422 422 CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
423 423 }
424   - RETURN();
  424 + FORCE_RET();
425 425 }
426 426  
427 427 void op_dmul (void)
428 428 {
429 429 T0 = (int64_t)T0 * (int64_t)T1;
430   - RETURN();
  430 + FORCE_RET();
431 431 }
432 432  
433 433 /* Those might call libgcc functions. */
434 434 void op_ddiv (void)
435 435 {
436 436 do_ddiv();
437   - RETURN();
  437 + FORCE_RET();
438 438 }
439 439  
440 440 #if TARGET_LONG_BITS > HOST_LONG_BITS
441 441 void op_ddivu (void)
442 442 {
443 443 do_ddivu();
444   - RETURN();
  444 + FORCE_RET();
445 445 }
446 446 #else
447 447 void op_ddivu (void)
... ... @@ -450,7 +450,7 @@ void op_ddivu (void)
450 450 env->LO[0][env->current_tc] = T0 / T1;
451 451 env->HI[0][env->current_tc] = T0 % T1;
452 452 }
453   - RETURN();
  453 + FORCE_RET();
454 454 }
455 455 #endif
456 456 #endif /* TARGET_MIPS64 */
... ... @@ -459,43 +459,43 @@ void op_ddivu (void)
459 459 void op_and (void)
460 460 {
461 461 T0 &= T1;
462   - RETURN();
  462 + FORCE_RET();
463 463 }
464 464  
465 465 void op_nor (void)
466 466 {
467 467 T0 = ~(T0 | T1);
468   - RETURN();
  468 + FORCE_RET();
469 469 }
470 470  
471 471 void op_or (void)
472 472 {
473 473 T0 |= T1;
474   - RETURN();
  474 + FORCE_RET();
475 475 }
476 476  
477 477 void op_xor (void)
478 478 {
479 479 T0 ^= T1;
480   - RETURN();
  480 + FORCE_RET();
481 481 }
482 482  
483 483 void op_sll (void)
484 484 {
485 485 T0 = (int32_t)((uint32_t)T0 << T1);
486   - RETURN();
  486 + FORCE_RET();
487 487 }
488 488  
489 489 void op_sra (void)
490 490 {
491 491 T0 = (int32_t)((int32_t)T0 >> T1);
492   - RETURN();
  492 + FORCE_RET();
493 493 }
494 494  
495 495 void op_srl (void)
496 496 {
497 497 T0 = (int32_t)((uint32_t)T0 >> T1);
498   - RETURN();
  498 + FORCE_RET();
499 499 }
500 500  
501 501 void op_rotr (void)
... ... @@ -506,25 +506,25 @@ void op_rotr (void)
506 506 tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
507 507 T0 = (int32_t)((uint32_t)T0 >> T1) | tmp;
508 508 }
509   - RETURN();
  509 + FORCE_RET();
510 510 }
511 511  
512 512 void op_sllv (void)
513 513 {
514 514 T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
515   - RETURN();
  515 + FORCE_RET();
516 516 }
517 517  
518 518 void op_srav (void)
519 519 {
520 520 T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
521   - RETURN();
  521 + FORCE_RET();
522 522 }
523 523  
524 524 void op_srlv (void)
525 525 {
526 526 T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
527   - RETURN();
  527 + FORCE_RET();
528 528 }
529 529  
530 530 void op_rotrv (void)
... ... @@ -537,19 +537,19 @@ void op_rotrv (void)
537 537 T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
538 538 } else
539 539 T0 = T1;
540   - RETURN();
  540 + FORCE_RET();
541 541 }
542 542  
543 543 void op_clo (void)
544 544 {
545 545 T0 = clo32(T0);
546   - RETURN();
  546 + FORCE_RET();
547 547 }
548 548  
549 549 void op_clz (void)
550 550 {
551 551 T0 = clz32(T0);
552   - RETURN();
  552 + FORCE_RET();
553 553 }
554 554  
555 555 #if defined(TARGET_MIPS64)
... ... @@ -559,85 +559,85 @@ void op_clz (void)
559 559 void op_dsll (void)
560 560 {
561 561 CALL_FROM_TB0(do_dsll);
562   - RETURN();
  562 + FORCE_RET();
563 563 }
564 564  
565 565 void op_dsll32 (void)
566 566 {
567 567 CALL_FROM_TB0(do_dsll32);
568   - RETURN();
  568 + FORCE_RET();
569 569 }
570 570  
571 571 void op_dsra (void)
572 572 {
573 573 CALL_FROM_TB0(do_dsra);
574   - RETURN();
  574 + FORCE_RET();
575 575 }
576 576  
577 577 void op_dsra32 (void)
578 578 {
579 579 CALL_FROM_TB0(do_dsra32);
580   - RETURN();
  580 + FORCE_RET();
581 581 }
582 582  
583 583 void op_dsrl (void)
584 584 {
585 585 CALL_FROM_TB0(do_dsrl);
586   - RETURN();
  586 + FORCE_RET();
587 587 }
588 588  
589 589 void op_dsrl32 (void)
590 590 {
591 591 CALL_FROM_TB0(do_dsrl32);
592   - RETURN();
  592 + FORCE_RET();
593 593 }
594 594  
595 595 void op_drotr (void)
596 596 {
597 597 CALL_FROM_TB0(do_drotr);
598   - RETURN();
  598 + FORCE_RET();
599 599 }
600 600  
601 601 void op_drotr32 (void)
602 602 {
603 603 CALL_FROM_TB0(do_drotr32);
604   - RETURN();
  604 + FORCE_RET();
605 605 }
606 606  
607 607 void op_dsllv (void)
608 608 {
609 609 CALL_FROM_TB0(do_dsllv);
610   - RETURN();
  610 + FORCE_RET();
611 611 }
612 612  
613 613 void op_dsrav (void)
614 614 {
615 615 CALL_FROM_TB0(do_dsrav);
616   - RETURN();
  616 + FORCE_RET();
617 617 }
618 618  
619 619 void op_dsrlv (void)
620 620 {
621 621 CALL_FROM_TB0(do_dsrlv);
622   - RETURN();
  622 + FORCE_RET();
623 623 }
624 624  
625 625 void op_drotrv (void)
626 626 {
627 627 CALL_FROM_TB0(do_drotrv);
628   - RETURN();
  628 + FORCE_RET();
629 629 }
630 630  
631 631 void op_dclo (void)
632 632 {
633 633 CALL_FROM_TB0(do_dclo);
634   - RETURN();
  634 + FORCE_RET();
635 635 }
636 636  
637 637 void op_dclz (void)
638 638 {
639 639 CALL_FROM_TB0(do_dclz);
640   - RETURN();
  640 + FORCE_RET();
641 641 }
642 642  
643 643 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
... ... @@ -645,37 +645,37 @@ void op_dclz (void)
645 645 void op_dsll (void)
646 646 {
647 647 T0 = T0 << T1;
648   - RETURN();
  648 + FORCE_RET();
649 649 }
650 650  
651 651 void op_dsll32 (void)
652 652 {
653 653 T0 = T0 << (T1 + 32);
654   - RETURN();
  654 + FORCE_RET();
655 655 }
656 656  
657 657 void op_dsra (void)
658 658 {
659 659 T0 = (int64_t)T0 >> T1;
660   - RETURN();
  660 + FORCE_RET();
661 661 }
662 662  
663 663 void op_dsra32 (void)
664 664 {
665 665 T0 = (int64_t)T0 >> (T1 + 32);
666   - RETURN();
  666 + FORCE_RET();
667 667 }
668 668  
669 669 void op_dsrl (void)
670 670 {
671 671 T0 = T0 >> T1;
672   - RETURN();
  672 + FORCE_RET();
673 673 }
674 674  
675 675 void op_dsrl32 (void)
676 676 {
677 677 T0 = T0 >> (T1 + 32);
678   - RETURN();
  678 + FORCE_RET();
679 679 }
680 680  
681 681 void op_drotr (void)
... ... @@ -686,7 +686,7 @@ void op_drotr (void)
686 686 tmp = T0 << (0x40 - T1);
687 687 T0 = (T0 >> T1) | tmp;
688 688 }
689   - RETURN();
  689 + FORCE_RET();
690 690 }
691 691  
692 692 void op_drotr32 (void)
... ... @@ -697,25 +697,25 @@ void op_drotr32 (void)
697 697 tmp = T0 << (0x40 - (32 + T1));
698 698 T0 = (T0 >> (32 + T1)) | tmp;
699 699 }
700   - RETURN();
  700 + FORCE_RET();
701 701 }
702 702  
703 703 void op_dsllv (void)
704 704 {
705 705 T0 = T1 << (T0 & 0x3F);
706   - RETURN();
  706 + FORCE_RET();
707 707 }
708 708  
709 709 void op_dsrav (void)
710 710 {
711 711 T0 = (int64_t)T1 >> (T0 & 0x3F);
712   - RETURN();
  712 + FORCE_RET();
713 713 }
714 714  
715 715 void op_dsrlv (void)
716 716 {
717 717 T0 = T1 >> (T0 & 0x3F);
718   - RETURN();
  718 + FORCE_RET();
719 719 }
720 720  
721 721 void op_drotrv (void)
... ... @@ -728,19 +728,19 @@ void op_drotrv (void)
728 728 T0 = (T1 >> T0) | tmp;
729 729 } else
730 730 T0 = T1;
731   - RETURN();
  731 + FORCE_RET();
732 732 }
733 733  
734 734 void op_dclo (void)
735 735 {
736 736 T0 = clo64(T0);
737   - RETURN();
  737 + FORCE_RET();
738 738 }
739 739  
740 740 void op_dclz (void)
741 741 {
742 742 T0 = clz64(T0);
743   - RETURN();
  743 + FORCE_RET();
744 744 }
745 745 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
746 746 #endif /* TARGET_MIPS64 */
... ... @@ -750,37 +750,37 @@ void op_dclz (void)
750 750 void op_mult (void)
751 751 {
752 752 CALL_FROM_TB0(do_mult);
753   - RETURN();
  753 + FORCE_RET();
754 754 }
755 755  
756 756 void op_multu (void)
757 757 {
758 758 CALL_FROM_TB0(do_multu);
759   - RETURN();
  759 + FORCE_RET();
760 760 }
761 761  
762 762 void op_madd (void)
763 763 {
764 764 CALL_FROM_TB0(do_madd);
765   - RETURN();
  765 + FORCE_RET();
766 766 }
767 767  
768 768 void op_maddu (void)
769 769 {
770 770 CALL_FROM_TB0(do_maddu);
771   - RETURN();
  771 + FORCE_RET();
772 772 }
773 773  
774 774 void op_msub (void)
775 775 {
776 776 CALL_FROM_TB0(do_msub);
777   - RETURN();
  777 + FORCE_RET();
778 778 }
779 779  
780 780 void op_msubu (void)
781 781 {
782 782 CALL_FROM_TB0(do_msubu);
783   - RETURN();
  783 + FORCE_RET();
784 784 }
785 785  
786 786 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
... ... @@ -800,13 +800,13 @@ static always_inline void set_HILO (uint64_t HILO)
800 800 void op_mult (void)
801 801 {
802 802 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
803   - RETURN();
  803 + FORCE_RET();
804 804 }
805 805  
806 806 void op_multu (void)
807 807 {
808 808 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
809   - RETURN();
  809 + FORCE_RET();
810 810 }
811 811  
812 812 void op_madd (void)
... ... @@ -815,7 +815,7 @@ void op_madd (void)
815 815  
816 816 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
817 817 set_HILO((int64_t)get_HILO() + tmp);
818   - RETURN();
  818 + FORCE_RET();
819 819 }
820 820  
821 821 void op_maddu (void)
... ... @@ -824,7 +824,7 @@ void op_maddu (void)
824 824  
825 825 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
826 826 set_HILO(get_HILO() + tmp);
827   - RETURN();
  827 + FORCE_RET();
828 828 }
829 829  
830 830 void op_msub (void)
... ... @@ -833,7 +833,7 @@ void op_msub (void)
833 833  
834 834 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
835 835 set_HILO((int64_t)get_HILO() - tmp);
836   - RETURN();
  836 + FORCE_RET();
837 837 }
838 838  
839 839 void op_msubu (void)
... ... @@ -842,7 +842,7 @@ void op_msubu (void)
842 842  
843 843 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
844 844 set_HILO(get_HILO() - tmp);
845   - RETURN();
  845 + FORCE_RET();
846 846 }
847 847 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
848 848  
... ... @@ -850,13 +850,13 @@ void op_msubu (void)
850 850 void op_dmult (void)
851 851 {
852 852 CALL_FROM_TB4(muls64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
853   - RETURN();
  853 + FORCE_RET();
854 854 }
855 855  
856 856 void op_dmultu (void)
857 857 {
858 858 CALL_FROM_TB4(mulu64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
859   - RETURN();
  859 + FORCE_RET();
860 860 }
861 861 #endif
862 862  
... ... @@ -865,28 +865,28 @@ void op_movn (void)
865 865 {
866 866 if (T1 != 0)
867 867 env->gpr[PARAM1][env->current_tc] = T0;
868   - RETURN();
  868 + FORCE_RET();
869 869 }
870 870  
871 871 void op_movz (void)
872 872 {
873 873 if (T1 == 0)
874 874 env->gpr[PARAM1][env->current_tc] = T0;
875   - RETURN();
  875 + FORCE_RET();
876 876 }
877 877  
878 878 void op_movf (void)
879 879 {
880 880 if (!(env->fpu->fcr31 & PARAM1))
881 881 T0 = T1;
882   - RETURN();
  882 + FORCE_RET();
883 883 }
884 884  
885 885 void op_movt (void)
886 886 {
887 887 if (env->fpu->fcr31 & PARAM1)
888 888 T0 = T1;
889   - RETURN();
  889 + FORCE_RET();
890 890 }
891 891  
892 892 /* Tests */
... ... @@ -898,7 +898,7 @@ void glue(op_, name) (void) \
898 898 } else { \
899 899 T0 = 0; \
900 900 } \
901   - RETURN(); \
  901 + FORCE_RET(); \
902 902 }
903 903  
904 904 OP_COND(eq, T0 == T1);
... ... @@ -916,45 +916,45 @@ OP_COND(ltz, (target_long)T0 &lt; 0);
916 916 void OPPROTO op_goto_tb0(void)
917 917 {
918 918 GOTO_TB(op_goto_tb0, PARAM1, 0);
919   - RETURN();
  919 + FORCE_RET();
920 920 }
921 921  
922 922 void OPPROTO op_goto_tb1(void)
923 923 {
924 924 GOTO_TB(op_goto_tb1, PARAM1, 1);
925   - RETURN();
  925 + FORCE_RET();
926 926 }
927 927  
928 928 /* Branch to register */
929 929 void op_save_breg_target (void)
930 930 {
931 931 env->btarget = T2;
932   - RETURN();
  932 + FORCE_RET();
933 933 }
934 934  
935 935 void op_restore_breg_target (void)
936 936 {
937 937 T2 = env->btarget;
938   - RETURN();
  938 + FORCE_RET();
939 939 }
940 940  
941 941 void op_breg (void)
942 942 {
943 943 env->PC[env->current_tc] = T2;
944   - RETURN();
  944 + FORCE_RET();
945 945 }
946 946  
947 947 void op_save_btarget (void)
948 948 {
949 949 env->btarget = PARAM1;
950   - RETURN();
  950 + FORCE_RET();
951 951 }
952 952  
953 953 #if defined(TARGET_MIPS64)
954 954 void op_save_btarget64 (void)
955 955 {
956 956 env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
957   - RETURN();
  957 + FORCE_RET();
958 958 }
959 959 #endif
960 960  
... ... @@ -962,111 +962,111 @@ void op_save_btarget64 (void)
962 962 void op_set_bcond (void)
963 963 {
964 964 T2 = T0;
965   - RETURN();
  965 + FORCE_RET();
966 966 }
967 967  
968 968 void op_save_bcond (void)
969 969 {
970 970 env->bcond = T2;
971   - RETURN();
  971 + FORCE_RET();
972 972 }
973 973  
974 974 void op_restore_bcond (void)
975 975 {
976 976 T2 = env->bcond;
977   - RETURN();
  977 + FORCE_RET();
978 978 }
979 979  
980 980 void op_jnz_T2 (void)
981 981 {
982 982 if (T2)
983 983 GOTO_LABEL_PARAM(1);
984   - RETURN();
  984 + FORCE_RET();
985 985 }
986 986  
987 987 /* CP0 functions */
988 988 void op_mfc0_index (void)
989 989 {
990 990 T0 = env->CP0_Index;
991   - RETURN();
  991 + FORCE_RET();
992 992 }
993 993  
994 994 void op_mfc0_mvpcontrol (void)
995 995 {
996 996 T0 = env->mvp->CP0_MVPControl;
997   - RETURN();
  997 + FORCE_RET();
998 998 }
999 999  
1000 1000 void op_mfc0_mvpconf0 (void)
1001 1001 {
1002 1002 T0 = env->mvp->CP0_MVPConf0;
1003   - RETURN();
  1003 + FORCE_RET();
1004 1004 }
1005 1005  
1006 1006 void op_mfc0_mvpconf1 (void)
1007 1007 {
1008 1008 T0 = env->mvp->CP0_MVPConf1;
1009   - RETURN();
  1009 + FORCE_RET();
1010 1010 }
1011 1011  
1012 1012 void op_mfc0_random (void)
1013 1013 {
1014 1014 CALL_FROM_TB0(do_mfc0_random);
1015   - RETURN();
  1015 + FORCE_RET();
1016 1016 }
1017 1017  
1018 1018 void op_mfc0_vpecontrol (void)
1019 1019 {
1020 1020 T0 = env->CP0_VPEControl;
1021   - RETURN();
  1021 + FORCE_RET();
1022 1022 }
1023 1023  
1024 1024 void op_mfc0_vpeconf0 (void)
1025 1025 {
1026 1026 T0 = env->CP0_VPEConf0;
1027   - RETURN();
  1027 + FORCE_RET();
1028 1028 }
1029 1029  
1030 1030 void op_mfc0_vpeconf1 (void)
1031 1031 {
1032 1032 T0 = env->CP0_VPEConf1;
1033   - RETURN();
  1033 + FORCE_RET();
1034 1034 }
1035 1035  
1036 1036 void op_mfc0_yqmask (void)
1037 1037 {
1038 1038 T0 = env->CP0_YQMask;
1039   - RETURN();
  1039 + FORCE_RET();
1040 1040 }
1041 1041  
1042 1042 void op_mfc0_vpeschedule (void)
1043 1043 {
1044 1044 T0 = env->CP0_VPESchedule;
1045   - RETURN();
  1045 + FORCE_RET();
1046 1046 }
1047 1047  
1048 1048 void op_mfc0_vpeschefback (void)
1049 1049 {
1050 1050 T0 = env->CP0_VPEScheFBack;
1051   - RETURN();
  1051 + FORCE_RET();
1052 1052 }
1053 1053  
1054 1054 void op_mfc0_vpeopt (void)
1055 1055 {
1056 1056 T0 = env->CP0_VPEOpt;
1057   - RETURN();
  1057 + FORCE_RET();
1058 1058 }
1059 1059  
1060 1060 void op_mfc0_entrylo0 (void)
1061 1061 {
1062 1062 T0 = (int32_t)env->CP0_EntryLo0;
1063   - RETURN();
  1063 + FORCE_RET();
1064 1064 }
1065 1065  
1066 1066 void op_mfc0_tcstatus (void)
1067 1067 {
1068 1068 T0 = env->CP0_TCStatus[env->current_tc];
1069   - RETURN();
  1069 + FORCE_RET();
1070 1070 }
1071 1071  
1072 1072 void op_mftc0_tcstatus(void)
... ... @@ -1074,13 +1074,13 @@ void op_mftc0_tcstatus(void)
1074 1074 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1075 1075  
1076 1076 T0 = env->CP0_TCStatus[other_tc];
1077   - RETURN();
  1077 + FORCE_RET();
1078 1078 }
1079 1079  
1080 1080 void op_mfc0_tcbind (void)
1081 1081 {
1082 1082 T0 = env->CP0_TCBind[env->current_tc];
1083   - RETURN();
  1083 + FORCE_RET();
1084 1084 }
1085 1085  
1086 1086 void op_mftc0_tcbind(void)
... ... @@ -1088,13 +1088,13 @@ void op_mftc0_tcbind(void)
1088 1088 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1089 1089  
1090 1090 T0 = env->CP0_TCBind[other_tc];
1091   - RETURN();
  1091 + FORCE_RET();
1092 1092 }
1093 1093  
1094 1094 void op_mfc0_tcrestart (void)
1095 1095 {
1096 1096 T0 = env->PC[env->current_tc];
1097   - RETURN();
  1097 + FORCE_RET();
1098 1098 }
1099 1099  
1100 1100 void op_mftc0_tcrestart(void)
... ... @@ -1102,13 +1102,13 @@ void op_mftc0_tcrestart(void)
1102 1102 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1103 1103  
1104 1104 T0 = env->PC[other_tc];
1105   - RETURN();
  1105 + FORCE_RET();
1106 1106 }
1107 1107  
1108 1108 void op_mfc0_tchalt (void)
1109 1109 {
1110 1110 T0 = env->CP0_TCHalt[env->current_tc];
1111   - RETURN();
  1111 + FORCE_RET();
1112 1112 }
1113 1113  
1114 1114 void op_mftc0_tchalt(void)
... ... @@ -1116,13 +1116,13 @@ void op_mftc0_tchalt(void)
1116 1116 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1117 1117  
1118 1118 T0 = env->CP0_TCHalt[other_tc];
1119   - RETURN();
  1119 + FORCE_RET();
1120 1120 }
1121 1121  
1122 1122 void op_mfc0_tccontext (void)
1123 1123 {
1124 1124 T0 = env->CP0_TCContext[env->current_tc];
1125   - RETURN();
  1125 + FORCE_RET();
1126 1126 }
1127 1127  
1128 1128 void op_mftc0_tccontext(void)
... ... @@ -1130,13 +1130,13 @@ void op_mftc0_tccontext(void)
1130 1130 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1131 1131  
1132 1132 T0 = env->CP0_TCContext[other_tc];
1133   - RETURN();
  1133 + FORCE_RET();
1134 1134 }
1135 1135  
1136 1136 void op_mfc0_tcschedule (void)
1137 1137 {
1138 1138 T0 = env->CP0_TCSchedule[env->current_tc];
1139   - RETURN();
  1139 + FORCE_RET();
1140 1140 }
1141 1141  
1142 1142 void op_mftc0_tcschedule(void)
... ... @@ -1144,13 +1144,13 @@ void op_mftc0_tcschedule(void)
1144 1144 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1145 1145  
1146 1146 T0 = env->CP0_TCSchedule[other_tc];
1147   - RETURN();
  1147 + FORCE_RET();
1148 1148 }
1149 1149  
1150 1150 void op_mfc0_tcschefback (void)
1151 1151 {
1152 1152 T0 = env->CP0_TCScheFBack[env->current_tc];
1153   - RETURN();
  1153 + FORCE_RET();
1154 1154 }
1155 1155  
1156 1156 void op_mftc0_tcschefback(void)
... ... @@ -1158,91 +1158,91 @@ void op_mftc0_tcschefback(void)
1158 1158 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1159 1159  
1160 1160 T0 = env->CP0_TCScheFBack[other_tc];
1161   - RETURN();
  1161 + FORCE_RET();
1162 1162 }
1163 1163  
1164 1164 void op_mfc0_entrylo1 (void)
1165 1165 {
1166 1166 T0 = (int32_t)env->CP0_EntryLo1;
1167   - RETURN();
  1167 + FORCE_RET();
1168 1168 }
1169 1169  
1170 1170 void op_mfc0_context (void)
1171 1171 {
1172 1172 T0 = (int32_t)env->CP0_Context;
1173   - RETURN();
  1173 + FORCE_RET();
1174 1174 }
1175 1175  
1176 1176 void op_mfc0_pagemask (void)
1177 1177 {
1178 1178 T0 = env->CP0_PageMask;
1179   - RETURN();
  1179 + FORCE_RET();
1180 1180 }
1181 1181  
1182 1182 void op_mfc0_pagegrain (void)
1183 1183 {
1184 1184 T0 = env->CP0_PageGrain;
1185   - RETURN();
  1185 + FORCE_RET();
1186 1186 }
1187 1187  
1188 1188 void op_mfc0_wired (void)
1189 1189 {
1190 1190 T0 = env->CP0_Wired;
1191   - RETURN();
  1191 + FORCE_RET();
1192 1192 }
1193 1193  
1194 1194 void op_mfc0_srsconf0 (void)
1195 1195 {
1196 1196 T0 = env->CP0_SRSConf0;
1197   - RETURN();
  1197 + FORCE_RET();
1198 1198 }
1199 1199  
1200 1200 void op_mfc0_srsconf1 (void)
1201 1201 {
1202 1202 T0 = env->CP0_SRSConf1;
1203   - RETURN();
  1203 + FORCE_RET();
1204 1204 }
1205 1205  
1206 1206 void op_mfc0_srsconf2 (void)
1207 1207 {
1208 1208 T0 = env->CP0_SRSConf2;
1209   - RETURN();
  1209 + FORCE_RET();
1210 1210 }
1211 1211  
1212 1212 void op_mfc0_srsconf3 (void)
1213 1213 {
1214 1214 T0 = env->CP0_SRSConf3;
1215   - RETURN();
  1215 + FORCE_RET();
1216 1216 }
1217 1217  
1218 1218 void op_mfc0_srsconf4 (void)
1219 1219 {
1220 1220 T0 = env->CP0_SRSConf4;
1221   - RETURN();
  1221 + FORCE_RET();
1222 1222 }
1223 1223  
1224 1224 void op_mfc0_hwrena (void)
1225 1225 {
1226 1226 T0 = env->CP0_HWREna;
1227   - RETURN();
  1227 + FORCE_RET();
1228 1228 }
1229 1229  
1230 1230 void op_mfc0_badvaddr (void)
1231 1231 {
1232 1232 T0 = (int32_t)env->CP0_BadVAddr;
1233   - RETURN();
  1233 + FORCE_RET();
1234 1234 }
1235 1235  
1236 1236 void op_mfc0_count (void)
1237 1237 {
1238 1238 CALL_FROM_TB0(do_mfc0_count);
1239   - RETURN();
  1239 + FORCE_RET();
1240 1240 }
1241 1241  
1242 1242 void op_mfc0_entryhi (void)
1243 1243 {
1244 1244 T0 = (int32_t)env->CP0_EntryHi;
1245   - RETURN();
  1245 + FORCE_RET();
1246 1246 }
1247 1247  
1248 1248 void op_mftc0_entryhi(void)
... ... @@ -1250,19 +1250,19 @@ void op_mftc0_entryhi(void)
1250 1250 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1251 1251  
1252 1252 T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
1253   - RETURN();
  1253 + FORCE_RET();
1254 1254 }
1255 1255  
1256 1256 void op_mfc0_compare (void)
1257 1257 {
1258 1258 T0 = env->CP0_Compare;
1259   - RETURN();
  1259 + FORCE_RET();
1260 1260 }
1261 1261  
1262 1262 void op_mfc0_status (void)
1263 1263 {
1264 1264 T0 = env->CP0_Status;
1265   - RETURN();
  1265 + FORCE_RET();
1266 1266 }
1267 1267  
1268 1268 void op_mftc0_status(void)
... ... @@ -1274,115 +1274,115 @@ void op_mftc0_status(void)
1274 1274 T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
1275 1275 T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
1276 1276 T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
1277   - RETURN();
  1277 + FORCE_RET();
1278 1278 }
1279 1279  
1280 1280 void op_mfc0_intctl (void)
1281 1281 {
1282 1282 T0 = env->CP0_IntCtl;
1283   - RETURN();
  1283 + FORCE_RET();
1284 1284 }
1285 1285  
1286 1286 void op_mfc0_srsctl (void)
1287 1287 {
1288 1288 T0 = env->CP0_SRSCtl;
1289   - RETURN();
  1289 + FORCE_RET();
1290 1290 }
1291 1291  
1292 1292 void op_mfc0_srsmap (void)
1293 1293 {
1294 1294 T0 = env->CP0_SRSMap;
1295   - RETURN();
  1295 + FORCE_RET();
1296 1296 }
1297 1297  
1298 1298 void op_mfc0_cause (void)
1299 1299 {
1300 1300 T0 = env->CP0_Cause;
1301   - RETURN();
  1301 + FORCE_RET();
1302 1302 }
1303 1303  
1304 1304 void op_mfc0_epc (void)
1305 1305 {
1306 1306 T0 = (int32_t)env->CP0_EPC;
1307   - RETURN();
  1307 + FORCE_RET();
1308 1308 }
1309 1309  
1310 1310 void op_mfc0_prid (void)
1311 1311 {
1312 1312 T0 = env->CP0_PRid;
1313   - RETURN();
  1313 + FORCE_RET();
1314 1314 }
1315 1315  
1316 1316 void op_mfc0_ebase (void)
1317 1317 {
1318 1318 T0 = env->CP0_EBase;
1319   - RETURN();
  1319 + FORCE_RET();
1320 1320 }
1321 1321  
1322 1322 void op_mfc0_config0 (void)
1323 1323 {
1324 1324 T0 = env->CP0_Config0;
1325   - RETURN();
  1325 + FORCE_RET();
1326 1326 }
1327 1327  
1328 1328 void op_mfc0_config1 (void)
1329 1329 {
1330 1330 T0 = env->CP0_Config1;
1331   - RETURN();
  1331 + FORCE_RET();
1332 1332 }
1333 1333  
1334 1334 void op_mfc0_config2 (void)
1335 1335 {
1336 1336 T0 = env->CP0_Config2;
1337   - RETURN();
  1337 + FORCE_RET();
1338 1338 }
1339 1339  
1340 1340 void op_mfc0_config3 (void)
1341 1341 {
1342 1342 T0 = env->CP0_Config3;
1343   - RETURN();
  1343 + FORCE_RET();
1344 1344 }
1345 1345  
1346 1346 void op_mfc0_config6 (void)
1347 1347 {
1348 1348 T0 = env->CP0_Config6;
1349   - RETURN();
  1349 + FORCE_RET();
1350 1350 }
1351 1351  
1352 1352 void op_mfc0_config7 (void)
1353 1353 {
1354 1354 T0 = env->CP0_Config7;
1355   - RETURN();
  1355 + FORCE_RET();
1356 1356 }
1357 1357  
1358 1358 void op_mfc0_lladdr (void)
1359 1359 {
1360 1360 T0 = (int32_t)env->CP0_LLAddr >> 4;
1361   - RETURN();
  1361 + FORCE_RET();
1362 1362 }
1363 1363  
1364 1364 void op_mfc0_watchlo (void)
1365 1365 {
1366 1366 T0 = (int32_t)env->CP0_WatchLo[PARAM1];
1367   - RETURN();
  1367 + FORCE_RET();
1368 1368 }
1369 1369  
1370 1370 void op_mfc0_watchhi (void)
1371 1371 {
1372 1372 T0 = env->CP0_WatchHi[PARAM1];
1373   - RETURN();
  1373 + FORCE_RET();
1374 1374 }
1375 1375  
1376 1376 void op_mfc0_xcontext (void)
1377 1377 {
1378 1378 T0 = (int32_t)env->CP0_XContext;
1379   - RETURN();
  1379 + FORCE_RET();
1380 1380 }
1381 1381  
1382 1382 void op_mfc0_framemask (void)
1383 1383 {
1384 1384 T0 = env->CP0_Framemask;
1385   - RETURN();
  1385 + FORCE_RET();
1386 1386 }
1387 1387  
1388 1388 void op_mfc0_debug (void)
... ... @@ -1390,7 +1390,7 @@ void op_mfc0_debug (void)
1390 1390 T0 = env->CP0_Debug;
1391 1391 if (env->hflags & MIPS_HFLAG_DM)
1392 1392 T0 |= 1 << CP0DB_DM;
1393   - RETURN();
  1393 + FORCE_RET();
1394 1394 }
1395 1395  
1396 1396 void op_mftc0_debug(void)
... ... @@ -1401,55 +1401,55 @@ void op_mftc0_debug(void)
1401 1401 T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1402 1402 (env->CP0_Debug_tcstatus[other_tc] &
1403 1403 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1404   - RETURN();
  1404 + FORCE_RET();
1405 1405 }
1406 1406  
1407 1407 void op_mfc0_depc (void)
1408 1408 {
1409 1409 T0 = (int32_t)env->CP0_DEPC;
1410   - RETURN();
  1410 + FORCE_RET();
1411 1411 }
1412 1412  
1413 1413 void op_mfc0_performance0 (void)
1414 1414 {
1415 1415 T0 = env->CP0_Performance0;
1416   - RETURN();
  1416 + FORCE_RET();
1417 1417 }
1418 1418  
1419 1419 void op_mfc0_taglo (void)
1420 1420 {
1421 1421 T0 = env->CP0_TagLo;
1422   - RETURN();
  1422 + FORCE_RET();
1423 1423 }
1424 1424  
1425 1425 void op_mfc0_datalo (void)
1426 1426 {
1427 1427 T0 = env->CP0_DataLo;
1428   - RETURN();
  1428 + FORCE_RET();
1429 1429 }
1430 1430  
1431 1431 void op_mfc0_taghi (void)
1432 1432 {
1433 1433 T0 = env->CP0_TagHi;
1434   - RETURN();
  1434 + FORCE_RET();
1435 1435 }
1436 1436  
1437 1437 void op_mfc0_datahi (void)
1438 1438 {
1439 1439 T0 = env->CP0_DataHi;
1440   - RETURN();
  1440 + FORCE_RET();
1441 1441 }
1442 1442  
1443 1443 void op_mfc0_errorepc (void)
1444 1444 {
1445 1445 T0 = (int32_t)env->CP0_ErrorEPC;
1446   - RETURN();
  1446 + FORCE_RET();
1447 1447 }
1448 1448  
1449 1449 void op_mfc0_desave (void)
1450 1450 {
1451 1451 T0 = env->CP0_DESAVE;
1452   - RETURN();
  1452 + FORCE_RET();
1453 1453 }
1454 1454  
1455 1455 void op_mtc0_index (void)
... ... @@ -1462,7 +1462,7 @@ void op_mtc0_index (void)
1462 1462 num <<= 1;
1463 1463 } while (tmp);
1464 1464 env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1));
1465   - RETURN();
  1465 + FORCE_RET();
1466 1466 }
1467 1467  
1468 1468 void op_mtc0_mvpcontrol (void)
... ... @@ -1480,7 +1480,7 @@ void op_mtc0_mvpcontrol (void)
1480 1480 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1481 1481  
1482 1482 env->mvp->CP0_MVPControl = newval;
1483   - RETURN();
  1483 + FORCE_RET();
1484 1484 }
1485 1485  
1486 1486 void op_mtc0_vpecontrol (void)
... ... @@ -1498,7 +1498,7 @@ void op_mtc0_vpecontrol (void)
1498 1498 // TODO: Enable/disable TCs.
1499 1499  
1500 1500 env->CP0_VPEControl = newval;
1501   - RETURN();
  1501 + FORCE_RET();
1502 1502 }
1503 1503  
1504 1504 void op_mtc0_vpeconf0 (void)
... ... @@ -1516,7 +1516,7 @@ void op_mtc0_vpeconf0 (void)
1516 1516 // TODO: TC exclusive handling due to ERL/EXL.
1517 1517  
1518 1518 env->CP0_VPEConf0 = newval;
1519   - RETURN();
  1519 + FORCE_RET();
1520 1520 }
1521 1521  
1522 1522 void op_mtc0_vpeconf1 (void)
... ... @@ -1535,32 +1535,32 @@ void op_mtc0_vpeconf1 (void)
1535 1535 // TODO: Handle FPU (CP1) binding.
1536 1536  
1537 1537 env->CP0_VPEConf1 = newval;
1538   - RETURN();
  1538 + FORCE_RET();
1539 1539 }
1540 1540  
1541 1541 void op_mtc0_yqmask (void)
1542 1542 {
1543 1543 /* Yield qualifier inputs not implemented. */
1544 1544 env->CP0_YQMask = 0x00000000;
1545   - RETURN();
  1545 + FORCE_RET();
1546 1546 }
1547 1547  
1548 1548 void op_mtc0_vpeschedule (void)
1549 1549 {
1550 1550 env->CP0_VPESchedule = T0;
1551   - RETURN();
  1551 + FORCE_RET();
1552 1552 }
1553 1553  
1554 1554 void op_mtc0_vpeschefback (void)
1555 1555 {
1556 1556 env->CP0_VPEScheFBack = T0;
1557   - RETURN();
  1557 + FORCE_RET();
1558 1558 }
1559 1559  
1560 1560 void op_mtc0_vpeopt (void)
1561 1561 {
1562 1562 env->CP0_VPEOpt = T0 & 0x0000ffff;
1563   - RETURN();
  1563 + FORCE_RET();
1564 1564 }
1565 1565  
1566 1566 void op_mtc0_entrylo0 (void)
... ... @@ -1568,7 +1568,7 @@ void op_mtc0_entrylo0 (void)
1568 1568 /* Large physaddr not implemented */
1569 1569 /* 1k pages not implemented */
1570 1570 env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1571   - RETURN();
  1571 + FORCE_RET();
1572 1572 }
1573 1573  
1574 1574 void op_mtc0_tcstatus (void)
... ... @@ -1581,7 +1581,7 @@ void op_mtc0_tcstatus (void)
1581 1581 // TODO: Sync with CP0_Status.
1582 1582  
1583 1583 env->CP0_TCStatus[env->current_tc] = newval;
1584   - RETURN();
  1584 + FORCE_RET();
1585 1585 }
1586 1586  
1587 1587 void op_mttc0_tcstatus (void)
... ... @@ -1591,7 +1591,7 @@ void op_mttc0_tcstatus (void)
1591 1591 // TODO: Sync with CP0_Status.
1592 1592  
1593 1593 env->CP0_TCStatus[other_tc] = T0;
1594   - RETURN();
  1594 + FORCE_RET();
1595 1595 }
1596 1596  
1597 1597 void op_mtc0_tcbind (void)
... ... @@ -1603,7 +1603,7 @@ void op_mtc0_tcbind (void)
1603 1603 mask |= (1 << CP0TCBd_CurVPE);
1604 1604 newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask);
1605 1605 env->CP0_TCBind[env->current_tc] = newval;
1606   - RETURN();
  1606 + FORCE_RET();
1607 1607 }
1608 1608  
1609 1609 void op_mttc0_tcbind (void)
... ... @@ -1616,7 +1616,7 @@ void op_mttc0_tcbind (void)
1616 1616 mask |= (1 << CP0TCBd_CurVPE);
1617 1617 newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask);
1618 1618 env->CP0_TCBind[other_tc] = newval;
1619   - RETURN();
  1619 + FORCE_RET();
1620 1620 }
1621 1621  
1622 1622 void op_mtc0_tcrestart (void)
... ... @@ -1625,7 +1625,7 @@ void op_mtc0_tcrestart (void)
1625 1625 env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
1626 1626 env->CP0_LLAddr = 0ULL;
1627 1627 /* MIPS16 not implemented. */
1628   - RETURN();
  1628 + FORCE_RET();
1629 1629 }
1630 1630  
1631 1631 void op_mttc0_tcrestart (void)
... ... @@ -1636,7 +1636,7 @@ void op_mttc0_tcrestart (void)
1636 1636 env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
1637 1637 env->CP0_LLAddr = 0ULL;
1638 1638 /* MIPS16 not implemented. */
1639   - RETURN();
  1639 + FORCE_RET();
1640 1640 }
1641 1641  
1642 1642 void op_mtc0_tchalt (void)
... ... @@ -1645,7 +1645,7 @@ void op_mtc0_tchalt (void)
1645 1645  
1646 1646 // TODO: Halt TC / Restart (if allocated+active) TC.
1647 1647  
1648   - RETURN();
  1648 + FORCE_RET();
1649 1649 }
1650 1650  
1651 1651 void op_mttc0_tchalt (void)
... ... @@ -1655,13 +1655,13 @@ void op_mttc0_tchalt (void)
1655 1655 // TODO: Halt TC / Restart (if allocated+active) TC.
1656 1656  
1657 1657 env->CP0_TCHalt[other_tc] = T0;
1658   - RETURN();
  1658 + FORCE_RET();
1659 1659 }
1660 1660  
1661 1661 void op_mtc0_tccontext (void)
1662 1662 {
1663 1663 env->CP0_TCContext[env->current_tc] = T0;
1664   - RETURN();
  1664 + FORCE_RET();
1665 1665 }
1666 1666  
1667 1667 void op_mttc0_tccontext (void)
... ... @@ -1669,13 +1669,13 @@ void op_mttc0_tccontext (void)
1669 1669 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1670 1670  
1671 1671 env->CP0_TCContext[other_tc] = T0;
1672   - RETURN();
  1672 + FORCE_RET();
1673 1673 }
1674 1674  
1675 1675 void op_mtc0_tcschedule (void)
1676 1676 {
1677 1677 env->CP0_TCSchedule[env->current_tc] = T0;
1678   - RETURN();
  1678 + FORCE_RET();
1679 1679 }
1680 1680  
1681 1681 void op_mttc0_tcschedule (void)
... ... @@ -1683,13 +1683,13 @@ void op_mttc0_tcschedule (void)
1683 1683 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1684 1684  
1685 1685 env->CP0_TCSchedule[other_tc] = T0;
1686   - RETURN();
  1686 + FORCE_RET();
1687 1687 }
1688 1688  
1689 1689 void op_mtc0_tcschefback (void)
1690 1690 {
1691 1691 env->CP0_TCScheFBack[env->current_tc] = T0;
1692   - RETURN();
  1692 + FORCE_RET();
1693 1693 }
1694 1694  
1695 1695 void op_mttc0_tcschefback (void)
... ... @@ -1697,7 +1697,7 @@ void op_mttc0_tcschefback (void)
1697 1697 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1698 1698  
1699 1699 env->CP0_TCScheFBack[other_tc] = T0;
1700   - RETURN();
  1700 + FORCE_RET();
1701 1701 }
1702 1702  
1703 1703 void op_mtc0_entrylo1 (void)
... ... @@ -1705,20 +1705,20 @@ void op_mtc0_entrylo1 (void)
1705 1705 /* Large physaddr not implemented */
1706 1706 /* 1k pages not implemented */
1707 1707 env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1708   - RETURN();
  1708 + FORCE_RET();
1709 1709 }
1710 1710  
1711 1711 void op_mtc0_context (void)
1712 1712 {
1713 1713 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
1714   - RETURN();
  1714 + FORCE_RET();
1715 1715 }
1716 1716  
1717 1717 void op_mtc0_pagemask (void)
1718 1718 {
1719 1719 /* 1k pages not implemented */
1720 1720 env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1721   - RETURN();
  1721 + FORCE_RET();
1722 1722 }
1723 1723  
1724 1724 void op_mtc0_pagegrain (void)
... ... @@ -1727,55 +1727,55 @@ void op_mtc0_pagegrain (void)
1727 1727 /* Large physaddr not implemented */
1728 1728 /* 1k pages not implemented */
1729 1729 env->CP0_PageGrain = 0;
1730   - RETURN();
  1730 + FORCE_RET();
1731 1731 }
1732 1732  
1733 1733 void op_mtc0_wired (void)
1734 1734 {
1735 1735 env->CP0_Wired = T0 % env->tlb->nb_tlb;
1736   - RETURN();
  1736 + FORCE_RET();
1737 1737 }
1738 1738  
1739 1739 void op_mtc0_srsconf0 (void)
1740 1740 {
1741 1741 env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask;
1742   - RETURN();
  1742 + FORCE_RET();
1743 1743 }
1744 1744  
1745 1745 void op_mtc0_srsconf1 (void)
1746 1746 {
1747 1747 env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask;
1748   - RETURN();
  1748 + FORCE_RET();
1749 1749 }
1750 1750  
1751 1751 void op_mtc0_srsconf2 (void)
1752 1752 {
1753 1753 env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask;
1754   - RETURN();
  1754 + FORCE_RET();
1755 1755 }
1756 1756  
1757 1757 void op_mtc0_srsconf3 (void)
1758 1758 {
1759 1759 env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask;
1760   - RETURN();
  1760 + FORCE_RET();
1761 1761 }
1762 1762  
1763 1763 void op_mtc0_srsconf4 (void)
1764 1764 {
1765 1765 env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask;
1766   - RETURN();
  1766 + FORCE_RET();
1767 1767 }
1768 1768  
1769 1769 void op_mtc0_hwrena (void)
1770 1770 {
1771 1771 env->CP0_HWREna = T0 & 0x0000000F;
1772   - RETURN();
  1772 + FORCE_RET();
1773 1773 }
1774 1774  
1775 1775 void op_mtc0_count (void)
1776 1776 {
1777 1777 CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1778   - RETURN();
  1778 + FORCE_RET();
1779 1779 }
1780 1780  
1781 1781 void op_mtc0_entryhi (void)
... ... @@ -1796,7 +1796,7 @@ void op_mtc0_entryhi (void)
1796 1796 /* If the ASID changes, flush qemu's TLB. */
1797 1797 if ((old & 0xFF) != (val & 0xFF))
1798 1798 CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1799   - RETURN();
  1799 + FORCE_RET();
1800 1800 }
1801 1801  
1802 1802 void op_mttc0_entryhi(void)
... ... @@ -1805,13 +1805,13 @@ void op_mttc0_entryhi(void)
1805 1805  
1806 1806 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff);
1807 1807 env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff);
1808   - RETURN();
  1808 + FORCE_RET();
1809 1809 }
1810 1810  
1811 1811 void op_mtc0_compare (void)
1812 1812 {
1813 1813 CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1814   - RETURN();
  1814 + FORCE_RET();
1815 1815 }
1816 1816  
1817 1817 void op_mtc0_status (void)
... ... @@ -1826,7 +1826,7 @@ void op_mtc0_status (void)
1826 1826 if (loglevel & CPU_LOG_EXEC)
1827 1827 CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1828 1828 CALL_FROM_TB1(cpu_mips_update_irq, env);
1829   - RETURN();
  1829 + FORCE_RET();
1830 1830 }
1831 1831  
1832 1832 void op_mttc0_status(void)
... ... @@ -1839,27 +1839,27 @@ void op_mttc0_status(void)
1839 1839 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1840 1840 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
1841 1841 env->CP0_TCStatus[other_tc] = tcstatus;
1842   - RETURN();
  1842 + FORCE_RET();
1843 1843 }
1844 1844  
1845 1845 void op_mtc0_intctl (void)
1846 1846 {
1847 1847 /* vectored interrupts not implemented, no performance counters. */
1848 1848 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0);
1849   - RETURN();
  1849 + FORCE_RET();
1850 1850 }
1851 1851  
1852 1852 void op_mtc0_srsctl (void)
1853 1853 {
1854 1854 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1855 1855 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask);
1856   - RETURN();
  1856 + FORCE_RET();
1857 1857 }
1858 1858  
1859 1859 void op_mtc0_srsmap (void)
1860 1860 {
1861 1861 env->CP0_SRSMap = T0;
1862   - RETURN();
  1862 + FORCE_RET();
1863 1863 }
1864 1864  
1865 1865 void op_mtc0_cause (void)
... ... @@ -1884,13 +1884,13 @@ void op_mtc0_cause (void)
1884 1884 if (T0 & CP0Ca_IP_mask) {
1885 1885 CALL_FROM_TB1(cpu_mips_update_irq, env);
1886 1886 }
1887   - RETURN();
  1887 + FORCE_RET();
1888 1888 }
1889 1889  
1890 1890 void op_mtc0_epc (void)
1891 1891 {
1892 1892 env->CP0_EPC = T0;
1893   - RETURN();
  1893 + FORCE_RET();
1894 1894 }
1895 1895  
1896 1896 void op_mtc0_ebase (void)
... ... @@ -1898,20 +1898,20 @@ void op_mtc0_ebase (void)
1898 1898 /* vectored interrupts not implemented */
1899 1899 /* Multi-CPU not implemented */
1900 1900 env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1901   - RETURN();
  1901 + FORCE_RET();
1902 1902 }
1903 1903  
1904 1904 void op_mtc0_config0 (void)
1905 1905 {
1906 1906 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007);
1907   - RETURN();
  1907 + FORCE_RET();
1908 1908 }
1909 1909  
1910 1910 void op_mtc0_config2 (void)
1911 1911 {
1912 1912 /* tertiary/secondary caches not implemented */
1913 1913 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1914   - RETURN();
  1914 + FORCE_RET();
1915 1915 }
1916 1916  
1917 1917 void op_mtc0_watchlo (void)
... ... @@ -1919,27 +1919,27 @@ void op_mtc0_watchlo (void)
1919 1919 /* Watch exceptions for instructions, data loads, data stores
1920 1920 not implemented. */
1921 1921 env->CP0_WatchLo[PARAM1] = (T0 & ~0x7);
1922   - RETURN();
  1922 + FORCE_RET();
1923 1923 }
1924 1924  
1925 1925 void op_mtc0_watchhi (void)
1926 1926 {
1927 1927 env->CP0_WatchHi[PARAM1] = (T0 & 0x40FF0FF8);
1928 1928 env->CP0_WatchHi[PARAM1] &= ~(env->CP0_WatchHi[PARAM1] & T0 & 0x7);
1929   - RETURN();
  1929 + FORCE_RET();
1930 1930 }
1931 1931  
1932 1932 void op_mtc0_xcontext (void)
1933 1933 {
1934 1934 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1935 1935 env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask);
1936   - RETURN();
  1936 + FORCE_RET();
1937 1937 }
1938 1938  
1939 1939 void op_mtc0_framemask (void)
1940 1940 {
1941 1941 env->CP0_Framemask = T0; /* XXX */
1942   - RETURN();
  1942 + FORCE_RET();
1943 1943 }
1944 1944  
1945 1945 void op_mtc0_debug (void)
... ... @@ -1949,7 +1949,7 @@ void op_mtc0_debug (void)
1949 1949 env->hflags |= MIPS_HFLAG_DM;
1950 1950 else
1951 1951 env->hflags &= ~MIPS_HFLAG_DM;
1952   - RETURN();
  1952 + FORCE_RET();
1953 1953 }
1954 1954  
1955 1955 void op_mttc0_debug(void)
... ... @@ -1960,170 +1960,170 @@ void op_mttc0_debug(void)
1960 1960 env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1961 1961 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1962 1962 (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1963   - RETURN();
  1963 + FORCE_RET();
1964 1964 }
1965 1965  
1966 1966 void op_mtc0_depc (void)
1967 1967 {
1968 1968 env->CP0_DEPC = T0;
1969   - RETURN();
  1969 + FORCE_RET();
1970 1970 }
1971 1971  
1972 1972 void op_mtc0_performance0 (void)
1973 1973 {
1974 1974 env->CP0_Performance0 = T0 & 0x000007ff;
1975   - RETURN();
  1975 + FORCE_RET();
1976 1976 }
1977 1977  
1978 1978 void op_mtc0_taglo (void)
1979 1979 {
1980 1980 env->CP0_TagLo = T0 & 0xFFFFFCF6;
1981   - RETURN();
  1981 + FORCE_RET();
1982 1982 }
1983 1983  
1984 1984 void op_mtc0_datalo (void)
1985 1985 {
1986 1986 env->CP0_DataLo = T0; /* XXX */
1987   - RETURN();
  1987 + FORCE_RET();
1988 1988 }
1989 1989  
1990 1990 void op_mtc0_taghi (void)
1991 1991 {
1992 1992 env->CP0_TagHi = T0; /* XXX */
1993   - RETURN();
  1993 + FORCE_RET();
1994 1994 }
1995 1995  
1996 1996 void op_mtc0_datahi (void)
1997 1997 {
1998 1998 env->CP0_DataHi = T0; /* XXX */
1999   - RETURN();
  1999 + FORCE_RET();
2000 2000 }
2001 2001  
2002 2002 void op_mtc0_errorepc (void)
2003 2003 {
2004 2004 env->CP0_ErrorEPC = T0;
2005   - RETURN();
  2005 + FORCE_RET();
2006 2006 }
2007 2007  
2008 2008 void op_mtc0_desave (void)
2009 2009 {
2010 2010 env->CP0_DESAVE = T0;
2011   - RETURN();
  2011 + FORCE_RET();
2012 2012 }
2013 2013  
2014 2014 #if defined(TARGET_MIPS64)
2015 2015 void op_dmfc0_yqmask (void)
2016 2016 {
2017 2017 T0 = env->CP0_YQMask;
2018   - RETURN();
  2018 + FORCE_RET();
2019 2019 }
2020 2020  
2021 2021 void op_dmfc0_vpeschedule (void)
2022 2022 {
2023 2023 T0 = env->CP0_VPESchedule;
2024   - RETURN();
  2024 + FORCE_RET();
2025 2025 }
2026 2026  
2027 2027 void op_dmfc0_vpeschefback (void)
2028 2028 {
2029 2029 T0 = env->CP0_VPEScheFBack;
2030   - RETURN();
  2030 + FORCE_RET();
2031 2031 }
2032 2032  
2033 2033 void op_dmfc0_entrylo0 (void)
2034 2034 {
2035 2035 T0 = env->CP0_EntryLo0;
2036   - RETURN();
  2036 + FORCE_RET();
2037 2037 }
2038 2038  
2039 2039 void op_dmfc0_tcrestart (void)
2040 2040 {
2041 2041 T0 = env->PC[env->current_tc];
2042   - RETURN();
  2042 + FORCE_RET();
2043 2043 }
2044 2044  
2045 2045 void op_dmfc0_tchalt (void)
2046 2046 {
2047 2047 T0 = env->CP0_TCHalt[env->current_tc];
2048   - RETURN();
  2048 + FORCE_RET();
2049 2049 }
2050 2050  
2051 2051 void op_dmfc0_tccontext (void)
2052 2052 {
2053 2053 T0 = env->CP0_TCContext[env->current_tc];
2054   - RETURN();
  2054 + FORCE_RET();
2055 2055 }
2056 2056  
2057 2057 void op_dmfc0_tcschedule (void)
2058 2058 {
2059 2059 T0 = env->CP0_TCSchedule[env->current_tc];
2060   - RETURN();
  2060 + FORCE_RET();
2061 2061 }
2062 2062  
2063 2063 void op_dmfc0_tcschefback (void)
2064 2064 {
2065 2065 T0 = env->CP0_TCScheFBack[env->current_tc];
2066   - RETURN();
  2066 + FORCE_RET();
2067 2067 }
2068 2068  
2069 2069 void op_dmfc0_entrylo1 (void)
2070 2070 {
2071 2071 T0 = env->CP0_EntryLo1;
2072   - RETURN();
  2072 + FORCE_RET();
2073 2073 }
2074 2074  
2075 2075 void op_dmfc0_context (void)
2076 2076 {
2077 2077 T0 = env->CP0_Context;
2078   - RETURN();
  2078 + FORCE_RET();
2079 2079 }
2080 2080  
2081 2081 void op_dmfc0_badvaddr (void)
2082 2082 {
2083 2083 T0 = env->CP0_BadVAddr;
2084   - RETURN();
  2084 + FORCE_RET();
2085 2085 }
2086 2086  
2087 2087 void op_dmfc0_entryhi (void)
2088 2088 {
2089 2089 T0 = env->CP0_EntryHi;
2090   - RETURN();
  2090 + FORCE_RET();
2091 2091 }
2092 2092  
2093 2093 void op_dmfc0_epc (void)
2094 2094 {
2095 2095 T0 = env->CP0_EPC;
2096   - RETURN();
  2096 + FORCE_RET();
2097 2097 }
2098 2098  
2099 2099 void op_dmfc0_lladdr (void)
2100 2100 {
2101 2101 T0 = env->CP0_LLAddr >> 4;
2102   - RETURN();
  2102 + FORCE_RET();
2103 2103 }
2104 2104  
2105 2105 void op_dmfc0_watchlo (void)
2106 2106 {
2107 2107 T0 = env->CP0_WatchLo[PARAM1];
2108   - RETURN();
  2108 + FORCE_RET();
2109 2109 }
2110 2110  
2111 2111 void op_dmfc0_xcontext (void)
2112 2112 {
2113 2113 T0 = env->CP0_XContext;
2114   - RETURN();
  2114 + FORCE_RET();
2115 2115 }
2116 2116  
2117 2117 void op_dmfc0_depc (void)
2118 2118 {
2119 2119 T0 = env->CP0_DEPC;
2120   - RETURN();
  2120 + FORCE_RET();
2121 2121 }
2122 2122  
2123 2123 void op_dmfc0_errorepc (void)
2124 2124 {
2125 2125 T0 = env->CP0_ErrorEPC;
2126   - RETURN();
  2126 + FORCE_RET();
2127 2127 }
2128 2128 #endif /* TARGET_MIPS64 */
2129 2129  
... ... @@ -2133,7 +2133,7 @@ void op_mftgpr(void)
2133 2133 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2134 2134  
2135 2135 T0 = env->gpr[PARAM1][other_tc];
2136   - RETURN();
  2136 + FORCE_RET();
2137 2137 }
2138 2138  
2139 2139 void op_mftlo(void)
... ... @@ -2141,7 +2141,7 @@ void op_mftlo(void)
2141 2141 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2142 2142  
2143 2143 T0 = env->LO[PARAM1][other_tc];
2144   - RETURN();
  2144 + FORCE_RET();
2145 2145 }
2146 2146  
2147 2147 void op_mfthi(void)
... ... @@ -2149,7 +2149,7 @@ void op_mfthi(void)
2149 2149 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2150 2150  
2151 2151 T0 = env->HI[PARAM1][other_tc];
2152   - RETURN();
  2152 + FORCE_RET();
2153 2153 }
2154 2154  
2155 2155 void op_mftacx(void)
... ... @@ -2157,7 +2157,7 @@ void op_mftacx(void)
2157 2157 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2158 2158  
2159 2159 T0 = env->ACX[PARAM1][other_tc];
2160   - RETURN();
  2160 + FORCE_RET();
2161 2161 }
2162 2162  
2163 2163 void op_mftdsp(void)
... ... @@ -2165,7 +2165,7 @@ void op_mftdsp(void)
2165 2165 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2166 2166  
2167 2167 T0 = env->DSPControl[other_tc];
2168   - RETURN();
  2168 + FORCE_RET();
2169 2169 }
2170 2170  
2171 2171 void op_mttgpr(void)
... ... @@ -2173,7 +2173,7 @@ void op_mttgpr(void)
2173 2173 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2174 2174  
2175 2175 T0 = env->gpr[PARAM1][other_tc];
2176   - RETURN();
  2176 + FORCE_RET();
2177 2177 }
2178 2178  
2179 2179 void op_mttlo(void)
... ... @@ -2181,7 +2181,7 @@ void op_mttlo(void)
2181 2181 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2182 2182  
2183 2183 T0 = env->LO[PARAM1][other_tc];
2184   - RETURN();
  2184 + FORCE_RET();
2185 2185 }
2186 2186  
2187 2187 void op_mtthi(void)
... ... @@ -2189,7 +2189,7 @@ void op_mtthi(void)
2189 2189 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2190 2190  
2191 2191 T0 = env->HI[PARAM1][other_tc];
2192   - RETURN();
  2192 + FORCE_RET();
2193 2193 }
2194 2194  
2195 2195 void op_mttacx(void)
... ... @@ -2197,7 +2197,7 @@ void op_mttacx(void)
2197 2197 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2198 2198  
2199 2199 T0 = env->ACX[PARAM1][other_tc];
2200   - RETURN();
  2200 + FORCE_RET();
2201 2201 }
2202 2202  
2203 2203 void op_mttdsp(void)
... ... @@ -2205,7 +2205,7 @@ void op_mttdsp(void)
2205 2205 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2206 2206  
2207 2207 T0 = env->DSPControl[other_tc];
2208   - RETURN();
  2208 + FORCE_RET();
2209 2209 }
2210 2210  
2211 2211  
... ... @@ -2214,7 +2214,7 @@ void op_dmt(void)
2214 2214 // TODO
2215 2215 T0 = 0;
2216 2216 // rt = T0
2217   - RETURN();
  2217 + FORCE_RET();
2218 2218 }
2219 2219  
2220 2220 void op_emt(void)
... ... @@ -2222,7 +2222,7 @@ void op_emt(void)
2222 2222 // TODO
2223 2223 T0 = 0;
2224 2224 // rt = T0
2225   - RETURN();
  2225 + FORCE_RET();
2226 2226 }
2227 2227  
2228 2228 void op_dvpe(void)
... ... @@ -2230,7 +2230,7 @@ void op_dvpe(void)
2230 2230 // TODO
2231 2231 T0 = 0;
2232 2232 // rt = T0
2233   - RETURN();
  2233 + FORCE_RET();
2234 2234 }
2235 2235  
2236 2236 void op_evpe(void)
... ... @@ -2238,7 +2238,7 @@ void op_evpe(void)
2238 2238 // TODO
2239 2239 T0 = 0;
2240 2240 // rt = T0
2241   - RETURN();
  2241 + FORCE_RET();
2242 2242 }
2243 2243  
2244 2244 void op_fork(void)
... ... @@ -2246,7 +2246,7 @@ void op_fork(void)
2246 2246 // T0 = rt, T1 = rs
2247 2247 T0 = 0;
2248 2248 // TODO: store to TC register
2249   - RETURN();
  2249 + FORCE_RET();
2250 2250 }
2251 2251  
2252 2252 void op_yield(void)
... ... @@ -2275,7 +2275,7 @@ void op_yield(void)
2275 2275 CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
2276 2276 }
2277 2277 T0 = env->CP0_YQMask;
2278   - RETURN();
  2278 + FORCE_RET();
2279 2279 }
2280 2280  
2281 2281 /* CP1 functions */
... ... @@ -2289,56 +2289,56 @@ void op_cfc1 (void)
2289 2289 {
2290 2290 CALL_FROM_TB1(do_cfc1, PARAM1);
2291 2291 DEBUG_FPU_STATE();
2292   - RETURN();
  2292 + FORCE_RET();
2293 2293 }
2294 2294  
2295 2295 void op_ctc1 (void)
2296 2296 {
2297 2297 CALL_FROM_TB1(do_ctc1, PARAM1);
2298 2298 DEBUG_FPU_STATE();
2299   - RETURN();
  2299 + FORCE_RET();
2300 2300 }
2301 2301  
2302 2302 void op_mfc1 (void)
2303 2303 {
2304 2304 T0 = (int32_t)WT0;
2305 2305 DEBUG_FPU_STATE();
2306   - RETURN();
  2306 + FORCE_RET();
2307 2307 }
2308 2308  
2309 2309 void op_mtc1 (void)
2310 2310 {
2311 2311 WT0 = T0;
2312 2312 DEBUG_FPU_STATE();
2313   - RETURN();
  2313 + FORCE_RET();
2314 2314 }
2315 2315  
2316 2316 void op_dmfc1 (void)
2317 2317 {
2318 2318 T0 = DT0;
2319 2319 DEBUG_FPU_STATE();
2320   - RETURN();
  2320 + FORCE_RET();
2321 2321 }
2322 2322  
2323 2323 void op_dmtc1 (void)
2324 2324 {
2325 2325 DT0 = T0;
2326 2326 DEBUG_FPU_STATE();
2327   - RETURN();
  2327 + FORCE_RET();
2328 2328 }
2329 2329  
2330 2330 void op_mfhc1 (void)
2331 2331 {
2332 2332 T0 = (int32_t)WTH0;
2333 2333 DEBUG_FPU_STATE();
2334   - RETURN();
  2334 + FORCE_RET();
2335 2335 }
2336 2336  
2337 2337 void op_mthc1 (void)
2338 2338 {
2339 2339 WTH0 = T0;
2340 2340 DEBUG_FPU_STATE();
2341   - RETURN();
  2341 + FORCE_RET();
2342 2342 }
2343 2343  
2344 2344 /* Float support.
... ... @@ -2352,117 +2352,117 @@ FLOAT_OP(cvtd, s)
2352 2352 {
2353 2353 CALL_FROM_TB0(do_float_cvtd_s);
2354 2354 DEBUG_FPU_STATE();
2355   - RETURN();
  2355 + FORCE_RET();
2356 2356 }
2357 2357 FLOAT_OP(cvtd, w)
2358 2358 {
2359 2359 CALL_FROM_TB0(do_float_cvtd_w);
2360 2360 DEBUG_FPU_STATE();
2361   - RETURN();
  2361 + FORCE_RET();
2362 2362 }
2363 2363 FLOAT_OP(cvtd, l)
2364 2364 {
2365 2365 CALL_FROM_TB0(do_float_cvtd_l);
2366 2366 DEBUG_FPU_STATE();
2367   - RETURN();
  2367 + FORCE_RET();
2368 2368 }
2369 2369 FLOAT_OP(cvtl, d)
2370 2370 {
2371 2371 CALL_FROM_TB0(do_float_cvtl_d);
2372 2372 DEBUG_FPU_STATE();
2373   - RETURN();
  2373 + FORCE_RET();
2374 2374 }
2375 2375 FLOAT_OP(cvtl, s)
2376 2376 {
2377 2377 CALL_FROM_TB0(do_float_cvtl_s);
2378 2378 DEBUG_FPU_STATE();
2379   - RETURN();
  2379 + FORCE_RET();
2380 2380 }
2381 2381 FLOAT_OP(cvtps, s)
2382 2382 {
2383 2383 WT2 = WT0;
2384 2384 WTH2 = WT1;
2385 2385 DEBUG_FPU_STATE();
2386   - RETURN();
  2386 + FORCE_RET();
2387 2387 }
2388 2388 FLOAT_OP(cvtps, pw)
2389 2389 {
2390 2390 CALL_FROM_TB0(do_float_cvtps_pw);
2391 2391 DEBUG_FPU_STATE();
2392   - RETURN();
  2392 + FORCE_RET();
2393 2393 }
2394 2394 FLOAT_OP(cvtpw, ps)
2395 2395 {
2396 2396 CALL_FROM_TB0(do_float_cvtpw_ps);
2397 2397 DEBUG_FPU_STATE();
2398   - RETURN();
  2398 + FORCE_RET();
2399 2399 }
2400 2400 FLOAT_OP(cvts, d)
2401 2401 {
2402 2402 CALL_FROM_TB0(do_float_cvts_d);
2403 2403 DEBUG_FPU_STATE();
2404   - RETURN();
  2404 + FORCE_RET();
2405 2405 }
2406 2406 FLOAT_OP(cvts, w)
2407 2407 {
2408 2408 CALL_FROM_TB0(do_float_cvts_w);
2409 2409 DEBUG_FPU_STATE();
2410   - RETURN();
  2410 + FORCE_RET();
2411 2411 }
2412 2412 FLOAT_OP(cvts, l)
2413 2413 {
2414 2414 CALL_FROM_TB0(do_float_cvts_l);
2415 2415 DEBUG_FPU_STATE();
2416   - RETURN();
  2416 + FORCE_RET();
2417 2417 }
2418 2418 FLOAT_OP(cvts, pl)
2419 2419 {
2420 2420 CALL_FROM_TB0(do_float_cvts_pl);
2421 2421 DEBUG_FPU_STATE();
2422   - RETURN();
  2422 + FORCE_RET();
2423 2423 }
2424 2424 FLOAT_OP(cvts, pu)
2425 2425 {
2426 2426 CALL_FROM_TB0(do_float_cvts_pu);
2427 2427 DEBUG_FPU_STATE();
2428   - RETURN();
  2428 + FORCE_RET();
2429 2429 }
2430 2430 FLOAT_OP(cvtw, s)
2431 2431 {
2432 2432 CALL_FROM_TB0(do_float_cvtw_s);
2433 2433 DEBUG_FPU_STATE();
2434   - RETURN();
  2434 + FORCE_RET();
2435 2435 }
2436 2436 FLOAT_OP(cvtw, d)
2437 2437 {
2438 2438 CALL_FROM_TB0(do_float_cvtw_d);
2439 2439 DEBUG_FPU_STATE();
2440   - RETURN();
  2440 + FORCE_RET();
2441 2441 }
2442 2442  
2443 2443 FLOAT_OP(pll, ps)
2444 2444 {
2445 2445 DT2 = ((uint64_t)WT0 << 32) | WT1;
2446 2446 DEBUG_FPU_STATE();
2447   - RETURN();
  2447 + FORCE_RET();
2448 2448 }
2449 2449 FLOAT_OP(plu, ps)
2450 2450 {
2451 2451 DT2 = ((uint64_t)WT0 << 32) | WTH1;
2452 2452 DEBUG_FPU_STATE();
2453   - RETURN();
  2453 + FORCE_RET();
2454 2454 }
2455 2455 FLOAT_OP(pul, ps)
2456 2456 {
2457 2457 DT2 = ((uint64_t)WTH0 << 32) | WT1;
2458 2458 DEBUG_FPU_STATE();
2459   - RETURN();
  2459 + FORCE_RET();
2460 2460 }
2461 2461 FLOAT_OP(puu, ps)
2462 2462 {
2463 2463 DT2 = ((uint64_t)WTH0 << 32) | WTH1;
2464 2464 DEBUG_FPU_STATE();
2465   - RETURN();
  2465 + FORCE_RET();
2466 2466 }
2467 2467  
2468 2468 #define FLOAT_ROUNDOP(op, ttype, stype) \
... ... @@ -2470,7 +2470,7 @@ FLOAT_OP(op ## ttype, stype) \
2470 2470 { \
2471 2471 CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \
2472 2472 DEBUG_FPU_STATE(); \
2473   - RETURN(); \
  2473 + FORCE_RET(); \
2474 2474 }
2475 2475  
2476 2476 FLOAT_ROUNDOP(round, l, d)
... ... @@ -2499,14 +2499,14 @@ FLOAT_OP(movf, d)
2499 2499 if (!(env->fpu->fcr31 & PARAM1))
2500 2500 DT2 = DT0;
2501 2501 DEBUG_FPU_STATE();
2502   - RETURN();
  2502 + FORCE_RET();
2503 2503 }
2504 2504 FLOAT_OP(movf, s)
2505 2505 {
2506 2506 if (!(env->fpu->fcr31 & PARAM1))
2507 2507 WT2 = WT0;
2508 2508 DEBUG_FPU_STATE();
2509   - RETURN();
  2509 + FORCE_RET();
2510 2510 }
2511 2511 FLOAT_OP(movf, ps)
2512 2512 {
... ... @@ -2515,21 +2515,21 @@ FLOAT_OP(movf, ps)
2515 2515 WTH2 = WTH0;
2516 2516 }
2517 2517 DEBUG_FPU_STATE();
2518   - RETURN();
  2518 + FORCE_RET();
2519 2519 }
2520 2520 FLOAT_OP(movt, d)
2521 2521 {
2522 2522 if (env->fpu->fcr31 & PARAM1)
2523 2523 DT2 = DT0;
2524 2524 DEBUG_FPU_STATE();
2525   - RETURN();
  2525 + FORCE_RET();
2526 2526 }
2527 2527 FLOAT_OP(movt, s)
2528 2528 {
2529 2529 if (env->fpu->fcr31 & PARAM1)
2530 2530 WT2 = WT0;
2531 2531 DEBUG_FPU_STATE();
2532   - RETURN();
  2532 + FORCE_RET();
2533 2533 }
2534 2534 FLOAT_OP(movt, ps)
2535 2535 {
... ... @@ -2538,21 +2538,21 @@ FLOAT_OP(movt, ps)
2538 2538 WTH2 = WTH0;
2539 2539 }
2540 2540 DEBUG_FPU_STATE();
2541   - RETURN();
  2541 + FORCE_RET();
2542 2542 }
2543 2543 FLOAT_OP(movz, d)
2544 2544 {
2545 2545 if (!T0)
2546 2546 DT2 = DT0;
2547 2547 DEBUG_FPU_STATE();
2548   - RETURN();
  2548 + FORCE_RET();
2549 2549 }
2550 2550 FLOAT_OP(movz, s)
2551 2551 {
2552 2552 if (!T0)
2553 2553 WT2 = WT0;
2554 2554 DEBUG_FPU_STATE();
2555   - RETURN();
  2555 + FORCE_RET();
2556 2556 }
2557 2557 FLOAT_OP(movz, ps)
2558 2558 {
... ... @@ -2561,21 +2561,21 @@ FLOAT_OP(movz, ps)
2561 2561 WTH2 = WTH0;
2562 2562 }
2563 2563 DEBUG_FPU_STATE();
2564   - RETURN();
  2564 + FORCE_RET();
2565 2565 }
2566 2566 FLOAT_OP(movn, d)
2567 2567 {
2568 2568 if (T0)
2569 2569 DT2 = DT0;
2570 2570 DEBUG_FPU_STATE();
2571   - RETURN();
  2571 + FORCE_RET();
2572 2572 }
2573 2573 FLOAT_OP(movn, s)
2574 2574 {
2575 2575 if (T0)
2576 2576 WT2 = WT0;
2577 2577 DEBUG_FPU_STATE();
2578   - RETURN();
  2578 + FORCE_RET();
2579 2579 }
2580 2580 FLOAT_OP(movn, ps)
2581 2581 {
... ... @@ -2584,28 +2584,28 @@ FLOAT_OP(movn, ps)
2584 2584 WTH2 = WTH0;
2585 2585 }
2586 2586 DEBUG_FPU_STATE();
2587   - RETURN();
  2587 + FORCE_RET();
2588 2588 }
2589 2589  
2590 2590 /* operations calling helpers, for s, d and ps */
2591   -#define FLOAT_HOP(name) \
  2591 +#define FLOAT_HOP(name) \
2592 2592 FLOAT_OP(name, d) \
2593 2593 { \
2594 2594 CALL_FROM_TB0(do_float_ ## name ## _d); \
2595 2595 DEBUG_FPU_STATE(); \
2596   - RETURN(); \
  2596 + FORCE_RET(); \
2597 2597 } \
2598 2598 FLOAT_OP(name, s) \
2599 2599 { \
2600 2600 CALL_FROM_TB0(do_float_ ## name ## _s); \
2601 2601 DEBUG_FPU_STATE(); \
2602   - RETURN(); \
  2602 + FORCE_RET(); \
2603 2603 } \
2604 2604 FLOAT_OP(name, ps) \
2605 2605 { \
2606 2606 CALL_FROM_TB0(do_float_ ## name ## _ps); \
2607 2607 DEBUG_FPU_STATE(); \
2608   - RETURN(); \
  2608 + FORCE_RET(); \
2609 2609 }
2610 2610 FLOAT_HOP(add)
2611 2611 FLOAT_HOP(sub)
... ... @@ -2623,13 +2623,13 @@ FLOAT_OP(name, d) \
2623 2623 { \
2624 2624 CALL_FROM_TB0(do_float_ ## name ## _d); \
2625 2625 DEBUG_FPU_STATE(); \
2626   - RETURN(); \
  2626 + FORCE_RET(); \
2627 2627 } \
2628 2628 FLOAT_OP(name, s) \
2629 2629 { \
2630 2630 CALL_FROM_TB0(do_float_ ## name ## _s); \
2631 2631 DEBUG_FPU_STATE(); \
2632   - RETURN(); \
  2632 + FORCE_RET(); \
2633 2633 }
2634 2634 FLOAT_HOP(rsqrt)
2635 2635 FLOAT_HOP(recip)
... ... @@ -2641,7 +2641,7 @@ FLOAT_OP(name, ps) \
2641 2641 { \
2642 2642 CALL_FROM_TB0(do_float_ ## name ## _ps); \
2643 2643 DEBUG_FPU_STATE(); \
2644   - RETURN(); \
  2644 + FORCE_RET(); \
2645 2645 }
2646 2646 FLOAT_HOP(addr)
2647 2647 FLOAT_HOP(mulr)
... ... @@ -2654,14 +2654,14 @@ FLOAT_OP(name1 ## name2, d) \
2654 2654 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
2655 2655 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
2656 2656 DEBUG_FPU_STATE(); \
2657   - RETURN(); \
  2657 + FORCE_RET(); \
2658 2658 } \
2659 2659 FLOAT_OP(name1 ## name2, s) \
2660 2660 { \
2661 2661 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2662 2662 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2663 2663 DEBUG_FPU_STATE(); \
2664   - RETURN(); \
  2664 + FORCE_RET(); \
2665 2665 } \
2666 2666 FLOAT_OP(name1 ## name2, ps) \
2667 2667 { \
... ... @@ -2670,7 +2670,7 @@ FLOAT_OP(name1 ## name2, ps) \
2670 2670 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2671 2671 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2672 2672 DEBUG_FPU_STATE(); \
2673   - RETURN(); \
  2673 + FORCE_RET(); \
2674 2674 }
2675 2675 FLOAT_TERNOP(mul, add)
2676 2676 FLOAT_TERNOP(mul, sub)
... ... @@ -2684,7 +2684,7 @@ FLOAT_OP(n ## name1 ## name2, d) \
2684 2684 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
2685 2685 FDT2 ^= 1ULL << 63; \
2686 2686 DEBUG_FPU_STATE(); \
2687   - RETURN(); \
  2687 + FORCE_RET(); \
2688 2688 } \
2689 2689 FLOAT_OP(n ## name1 ## name2, s) \
2690 2690 { \
... ... @@ -2692,7 +2692,7 @@ FLOAT_OP(n ## name1 ## name2, s) \
2692 2692 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2693 2693 FST2 ^= 1 << 31; \
2694 2694 DEBUG_FPU_STATE(); \
2695   - RETURN(); \
  2695 + FORCE_RET(); \
2696 2696 } \
2697 2697 FLOAT_OP(n ## name1 ## name2, ps) \
2698 2698 { \
... ... @@ -2703,7 +2703,7 @@ FLOAT_OP(n ## name1 ## name2, ps) \
2703 2703 FST2 ^= 1 << 31; \
2704 2704 FSTH2 ^= 1 << 31; \
2705 2705 DEBUG_FPU_STATE(); \
2706   - RETURN(); \
  2706 + FORCE_RET(); \
2707 2707 }
2708 2708 FLOAT_NTERNOP(mul, add)
2709 2709 FLOAT_NTERNOP(mul, sub)
... ... @@ -2713,15 +2713,15 @@ FLOAT_NTERNOP(mul, sub)
2713 2713 #define FLOAT_UNOP(name) \
2714 2714 FLOAT_OP(name, d) \
2715 2715 { \
2716   - FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status); \
  2716 + FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status); \
2717 2717 DEBUG_FPU_STATE(); \
2718   - RETURN(); \
  2718 + FORCE_RET(); \
2719 2719 } \
2720 2720 FLOAT_OP(name, s) \
2721 2721 { \
2722   - FST2 = float32_ ## name(FST0, &env->fpu->fp_status); \
  2722 + FST2 = float32_ ## name(FST0, &env->fpu->fp_status); \
2723 2723 DEBUG_FPU_STATE(); \
2724   - RETURN(); \
  2724 + FORCE_RET(); \
2725 2725 }
2726 2726 FLOAT_UNOP(sqrt)
2727 2727 #undef FLOAT_UNOP
... ... @@ -2732,20 +2732,20 @@ FLOAT_OP(name, d) \
2732 2732 { \
2733 2733 FDT2 = float64_ ## name(FDT0); \
2734 2734 DEBUG_FPU_STATE(); \
2735   - RETURN(); \
  2735 + FORCE_RET(); \
2736 2736 } \
2737 2737 FLOAT_OP(name, s) \
2738 2738 { \
2739 2739 FST2 = float32_ ## name(FST0); \
2740 2740 DEBUG_FPU_STATE(); \
2741   - RETURN(); \
  2741 + FORCE_RET(); \
2742 2742 } \
2743 2743 FLOAT_OP(name, ps) \
2744 2744 { \
2745 2745 FST2 = float32_ ## name(FST0); \
2746 2746 FSTH2 = float32_ ## name(FSTH0); \
2747 2747 DEBUG_FPU_STATE(); \
2748   - RETURN(); \
  2748 + FORCE_RET(); \
2749 2749 }
2750 2750 FLOAT_UNOP(abs)
2751 2751 FLOAT_UNOP(chs)
... ... @@ -2755,20 +2755,20 @@ FLOAT_OP(mov, d)
2755 2755 {
2756 2756 FDT2 = FDT0;
2757 2757 DEBUG_FPU_STATE();
2758   - RETURN();
  2758 + FORCE_RET();
2759 2759 }
2760 2760 FLOAT_OP(mov, s)
2761 2761 {
2762 2762 FST2 = FST0;
2763 2763 DEBUG_FPU_STATE();
2764   - RETURN();
  2764 + FORCE_RET();
2765 2765 }
2766 2766 FLOAT_OP(mov, ps)
2767 2767 {
2768 2768 FST2 = FST0;
2769 2769 FSTH2 = FSTH0;
2770 2770 DEBUG_FPU_STATE();
2771   - RETURN();
  2771 + FORCE_RET();
2772 2772 }
2773 2773 FLOAT_OP(alnv, ps)
2774 2774 {
... ... @@ -2790,14 +2790,14 @@ FLOAT_OP(alnv, ps)
2790 2790 break;
2791 2791 }
2792 2792 DEBUG_FPU_STATE();
2793   - RETURN();
  2793 + FORCE_RET();
2794 2794 }
2795 2795  
2796 2796 #ifdef CONFIG_SOFTFLOAT
2797 2797 #define clear_invalid() do { \
2798 2798 int flags = get_float_exception_flags(&env->fpu->fp_status); \
2799 2799 flags &= ~float_flag_invalid; \
2800   - set_float_exception_flags(flags, &env->fpu->fp_status); \
  2800 + set_float_exception_flags(flags, &env->fpu->fp_status); \
2801 2801 } while(0)
2802 2802 #else
2803 2803 #define clear_invalid() do { } while(0)
... ... @@ -2810,13 +2810,13 @@ void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void) \
2810 2810 { \
2811 2811 CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \
2812 2812 DEBUG_FPU_STATE(); \
2813   - RETURN(); \
  2813 + FORCE_RET(); \
2814 2814 } \
2815 2815 void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void) \
2816 2816 { \
2817 2817 CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \
2818 2818 DEBUG_FPU_STATE(); \
2819   - RETURN(); \
  2819 + FORCE_RET(); \
2820 2820 }
2821 2821 #define CMP_OPS(op) \
2822 2822 CMP_OP(d, op) \
... ... @@ -2846,62 +2846,62 @@ void op_bc1f (void)
2846 2846 {
2847 2847 T0 = !!(~GET_FP_COND(env->fpu) & (0x1 << PARAM1));
2848 2848 DEBUG_FPU_STATE();
2849   - RETURN();
  2849 + FORCE_RET();
2850 2850 }
2851 2851 void op_bc1any2f (void)
2852 2852 {
2853 2853 T0 = !!(~GET_FP_COND(env->fpu) & (0x3 << PARAM1));
2854 2854 DEBUG_FPU_STATE();
2855   - RETURN();
  2855 + FORCE_RET();
2856 2856 }
2857 2857 void op_bc1any4f (void)
2858 2858 {
2859 2859 T0 = !!(~GET_FP_COND(env->fpu) & (0xf << PARAM1));
2860 2860 DEBUG_FPU_STATE();
2861   - RETURN();
  2861 + FORCE_RET();
2862 2862 }
2863 2863  
2864 2864 void op_bc1t (void)
2865 2865 {
2866 2866 T0 = !!(GET_FP_COND(env->fpu) & (0x1 << PARAM1));
2867 2867 DEBUG_FPU_STATE();
2868   - RETURN();
  2868 + FORCE_RET();
2869 2869 }
2870 2870 void op_bc1any2t (void)
2871 2871 {
2872 2872 T0 = !!(GET_FP_COND(env->fpu) & (0x3 << PARAM1));
2873 2873 DEBUG_FPU_STATE();
2874   - RETURN();
  2874 + FORCE_RET();
2875 2875 }
2876 2876 void op_bc1any4t (void)
2877 2877 {
2878 2878 T0 = !!(GET_FP_COND(env->fpu) & (0xf << PARAM1));
2879 2879 DEBUG_FPU_STATE();
2880   - RETURN();
  2880 + FORCE_RET();
2881 2881 }
2882 2882  
2883 2883 void op_tlbwi (void)
2884 2884 {
2885 2885 CALL_FROM_TB0(env->tlb->do_tlbwi);
2886   - RETURN();
  2886 + FORCE_RET();
2887 2887 }
2888 2888  
2889 2889 void op_tlbwr (void)
2890 2890 {
2891 2891 CALL_FROM_TB0(env->tlb->do_tlbwr);
2892   - RETURN();
  2892 + FORCE_RET();
2893 2893 }
2894 2894  
2895 2895 void op_tlbp (void)
2896 2896 {
2897 2897 CALL_FROM_TB0(env->tlb->do_tlbp);
2898   - RETURN();
  2898 + FORCE_RET();
2899 2899 }
2900 2900  
2901 2901 void op_tlbr (void)
2902 2902 {
2903 2903 CALL_FROM_TB0(env->tlb->do_tlbr);
2904   - RETURN();
  2904 + FORCE_RET();
2905 2905 }
2906 2906  
2907 2907 /* Specials */
... ... @@ -2915,7 +2915,7 @@ void op_tls_value (void)
2915 2915 void op_pmon (void)
2916 2916 {
2917 2917 CALL_FROM_TB1(do_pmon, PARAM1);
2918   - RETURN();
  2918 + FORCE_RET();
2919 2919 }
2920 2920  
2921 2921 void op_di (void)
... ... @@ -2923,7 +2923,7 @@ void op_di (void)
2923 2923 T0 = env->CP0_Status;
2924 2924 env->CP0_Status = T0 & ~(1 << CP0St_IE);
2925 2925 CALL_FROM_TB1(cpu_mips_update_irq, env);
2926   - RETURN();
  2926 + FORCE_RET();
2927 2927 }
2928 2928  
2929 2929 void op_ei (void)
... ... @@ -2931,7 +2931,7 @@ void op_ei (void)
2931 2931 T0 = env->CP0_Status;
2932 2932 env->CP0_Status = T0 | (1 << CP0St_IE);
2933 2933 CALL_FROM_TB1(cpu_mips_update_irq, env);
2934   - RETURN();
  2934 + FORCE_RET();
2935 2935 }
2936 2936  
2937 2937 void op_trap (void)
... ... @@ -2939,19 +2939,19 @@ void op_trap (void)
2939 2939 if (T0) {
2940 2940 CALL_FROM_TB1(do_raise_exception, EXCP_TRAP);
2941 2941 }
2942   - RETURN();
  2942 + FORCE_RET();
2943 2943 }
2944 2944  
2945 2945 void op_debug (void)
2946 2946 {
2947 2947 CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
2948   - RETURN();
  2948 + FORCE_RET();
2949 2949 }
2950 2950  
2951 2951 void op_set_lladdr (void)
2952 2952 {
2953 2953 env->CP0_LLAddr = T2;
2954   - RETURN();
  2954 + FORCE_RET();
2955 2955 }
2956 2956  
2957 2957 void debug_pre_eret (void);
... ... @@ -2971,7 +2971,7 @@ void op_eret (void)
2971 2971 if (loglevel & CPU_LOG_EXEC)
2972 2972 CALL_FROM_TB0(debug_post_eret);
2973 2973 env->CP0_LLAddr = 1;
2974   - RETURN();
  2974 + FORCE_RET();
2975 2975 }
2976 2976  
2977 2977 void op_deret (void)
... ... @@ -2984,7 +2984,7 @@ void op_deret (void)
2984 2984 if (loglevel & CPU_LOG_EXEC)
2985 2985 CALL_FROM_TB0(debug_post_eret);
2986 2986 env->CP0_LLAddr = 1;
2987   - RETURN();
  2987 + FORCE_RET();
2988 2988 }
2989 2989  
2990 2990 void op_rdhwr_cpunum(void)
... ... @@ -2994,7 +2994,7 @@ void op_rdhwr_cpunum(void)
2994 2994 T0 = env->CP0_EBase & 0x3ff;
2995 2995 else
2996 2996 CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2997   - RETURN();
  2997 + FORCE_RET();
2998 2998 }
2999 2999  
3000 3000 void op_rdhwr_synci_step(void)
... ... @@ -3004,7 +3004,7 @@ void op_rdhwr_synci_step(void)
3004 3004 T0 = env->SYNCI_Step;
3005 3005 else
3006 3006 CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3007   - RETURN();
  3007 + FORCE_RET();
3008 3008 }
3009 3009  
3010 3010 void op_rdhwr_cc(void)
... ... @@ -3014,7 +3014,7 @@ void op_rdhwr_cc(void)
3014 3014 T0 = env->CP0_Count;
3015 3015 else
3016 3016 CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3017   - RETURN();
  3017 + FORCE_RET();
3018 3018 }
3019 3019  
3020 3020 void op_rdhwr_ccres(void)
... ... @@ -3024,26 +3024,26 @@ void op_rdhwr_ccres(void)
3024 3024 T0 = env->CCRes;
3025 3025 else
3026 3026 CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3027   - RETURN();
  3027 + FORCE_RET();
3028 3028 }
3029 3029  
3030 3030 void op_save_state (void)
3031 3031 {
3032 3032 env->hflags = PARAM1;
3033   - RETURN();
  3033 + FORCE_RET();
3034 3034 }
3035 3035  
3036 3036 void op_save_pc (void)
3037 3037 {
3038 3038 env->PC[env->current_tc] = PARAM1;
3039   - RETURN();
  3039 + FORCE_RET();
3040 3040 }
3041 3041  
3042 3042 #if defined(TARGET_MIPS64)
3043 3043 void op_save_pc64 (void)
3044 3044 {
3045 3045 env->PC[env->current_tc] = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
3046   - RETURN();
  3046 + FORCE_RET();
3047 3047 }
3048 3048 #endif
3049 3049  
... ... @@ -3057,32 +3057,32 @@ void op_interrupt_restart (void)
3057 3057 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
3058 3058 CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT);
3059 3059 }
3060   - RETURN();
  3060 + FORCE_RET();
3061 3061 }
3062 3062  
3063 3063 void op_raise_exception (void)
3064 3064 {
3065 3065 CALL_FROM_TB1(do_raise_exception, PARAM1);
3066   - RETURN();
  3066 + FORCE_RET();
3067 3067 }
3068 3068  
3069 3069 void op_raise_exception_err (void)
3070 3070 {
3071 3071 CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
3072   - RETURN();
  3072 + FORCE_RET();
3073 3073 }
3074 3074  
3075 3075 void op_exit_tb (void)
3076 3076 {
3077 3077 EXIT_TB();
3078   - RETURN();
  3078 + FORCE_RET();
3079 3079 }
3080 3080  
3081 3081 void op_wait (void)
3082 3082 {
3083 3083 env->halted = 1;
3084 3084 CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
3085   - RETURN();
  3085 + FORCE_RET();
3086 3086 }
3087 3087  
3088 3088 /* Bitfield operations. */
... ... @@ -3092,7 +3092,7 @@ void op_ext(void)
3092 3092 unsigned int size = PARAM2;
3093 3093  
3094 3094 T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
3095   - RETURN();
  3095 + FORCE_RET();
3096 3096 }
3097 3097  
3098 3098 void op_ins(void)
... ... @@ -3102,13 +3102,13 @@ void op_ins(void)
3102 3102 target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
3103 3103  
3104 3104 T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask);
3105   - RETURN();
  3105 + FORCE_RET();
3106 3106 }
3107 3107  
3108 3108 void op_wsbh(void)
3109 3109 {
3110 3110 T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
3111   - RETURN();
  3111 + FORCE_RET();
3112 3112 }
3113 3113  
3114 3114 #if defined(TARGET_MIPS64)
... ... @@ -3118,7 +3118,7 @@ void op_dext(void)
3118 3118 unsigned int size = PARAM2;
3119 3119  
3120 3120 T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
3121   - RETURN();
  3121 + FORCE_RET();
3122 3122 }
3123 3123  
3124 3124 void op_dins(void)
... ... @@ -3128,30 +3128,30 @@ void op_dins(void)
3128 3128 target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
3129 3129  
3130 3130 T0 = (T0 & ~mask) | ((T1 << pos) & mask);
3131   - RETURN();
  3131 + FORCE_RET();
3132 3132 }
3133 3133  
3134 3134 void op_dsbh(void)
3135 3135 {
3136 3136 T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
3137   - RETURN();
  3137 + FORCE_RET();
3138 3138 }
3139 3139  
3140 3140 void op_dshd(void)
3141 3141 {
3142 3142 T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
3143   - RETURN();
  3143 + FORCE_RET();
3144 3144 }
3145 3145 #endif
3146 3146  
3147 3147 void op_seb(void)
3148 3148 {
3149 3149 T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
3150   - RETURN();
  3150 + FORCE_RET();
3151 3151 }
3152 3152  
3153 3153 void op_seh(void)
3154 3154 {
3155 3155 T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
3156   - RETURN();
  3156 + FORCE_RET();
3157 3157 }
... ...
target-mips/op_mem.c
  View file @8f6f602
... ... @@ -22,55 +22,55 @@
22 22 void glue(op_lb, MEMSUFFIX) (void)
23 23 {
24 24 T0 = glue(ldsb, MEMSUFFIX)(T0);
25   - RETURN();
  25 + FORCE_RET();
26 26 }
27 27  
28 28 void glue(op_lbu, MEMSUFFIX) (void)
29 29 {
30 30 T0 = glue(ldub, MEMSUFFIX)(T0);
31   - RETURN();
  31 + FORCE_RET();
32 32 }
33 33  
34 34 void glue(op_sb, MEMSUFFIX) (void)
35 35 {
36 36 glue(stb, MEMSUFFIX)(T0, T1);
37   - RETURN();
  37 + FORCE_RET();
38 38 }
39 39  
40 40 void glue(op_lh, MEMSUFFIX) (void)
41 41 {
42 42 T0 = glue(ldsw, MEMSUFFIX)(T0);
43   - RETURN();
  43 + FORCE_RET();
44 44 }
45 45  
46 46 void glue(op_lhu, MEMSUFFIX) (void)
47 47 {
48 48 T0 = glue(lduw, MEMSUFFIX)(T0);
49   - RETURN();
  49 + FORCE_RET();
50 50 }
51 51  
52 52 void glue(op_sh, MEMSUFFIX) (void)
53 53 {
54 54 glue(stw, MEMSUFFIX)(T0, T1);
55   - RETURN();
  55 + FORCE_RET();
56 56 }
57 57  
58 58 void glue(op_lw, MEMSUFFIX) (void)
59 59 {
60 60 T0 = glue(ldl, MEMSUFFIX)(T0);
61   - RETURN();
  61 + FORCE_RET();
62 62 }
63 63  
64 64 void glue(op_lwu, MEMSUFFIX) (void)
65 65 {
66 66 T0 = (uint32_t)glue(ldl, MEMSUFFIX)(T0);
67   - RETURN();
  67 + FORCE_RET();
68 68 }
69 69  
70 70 void glue(op_sw, MEMSUFFIX) (void)
71 71 {
72 72 glue(stl, MEMSUFFIX)(T0, T1);
73   - RETURN();
  73 + FORCE_RET();
74 74 }
75 75  
76 76 /* "half" load and stores. We must do the memory access inline,
... ... @@ -106,7 +106,7 @@ void glue(op_lwl, MEMSUFFIX) (void)
106 106 T1 = (T1 & 0xFFFFFF00) | tmp;
107 107 }
108 108 T1 = (int32_t)T1;
109   - RETURN();
  109 + FORCE_RET();
110 110 }
111 111  
112 112 void glue(op_lwr, MEMSUFFIX) (void)
... ... @@ -131,7 +131,7 @@ void glue(op_lwr, MEMSUFFIX) (void)
131 131 T1 = (T1 & 0x00FFFFFF) | (tmp << 24);
132 132 }
133 133 T1 = (int32_t)T1;
134   - RETURN();
  134 + FORCE_RET();
135 135 }
136 136  
137 137 void glue(op_swl, MEMSUFFIX) (void)
... ... @@ -147,7 +147,7 @@ void glue(op_swl, MEMSUFFIX) (void)
147 147 if (GET_LMASK(T0) == 0)
148 148 glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 3), (uint8_t)T1);
149 149  
150   - RETURN();
  150 + FORCE_RET();
151 151 }
152 152  
153 153 void glue(op_swr, MEMSUFFIX) (void)
... ... @@ -163,7 +163,7 @@ void glue(op_swr, MEMSUFFIX) (void)
163 163 if (GET_LMASK(T0) == 3)
164 164 glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24));
165 165  
166   - RETURN();
  166 + FORCE_RET();
167 167 }
168 168  
169 169 void glue(op_ll, MEMSUFFIX) (void)
... ... @@ -171,7 +171,7 @@ void glue(op_ll, MEMSUFFIX) (void)
171 171 T1 = T0;
172 172 T0 = glue(ldl, MEMSUFFIX)(T0);
173 173 env->CP0_LLAddr = T1;
174   - RETURN();
  174 + FORCE_RET();
175 175 }
176 176  
177 177 void glue(op_sc, MEMSUFFIX) (void)
... ... @@ -187,20 +187,20 @@ void glue(op_sc, MEMSUFFIX) (void)
187 187 } else {
188 188 T0 = 0;
189 189 }
190   - RETURN();
  190 + FORCE_RET();
191 191 }
192 192  
193 193 #if defined(TARGET_MIPS64)
194 194 void glue(op_ld, MEMSUFFIX) (void)
195 195 {
196 196 T0 = glue(ldq, MEMSUFFIX)(T0);
197   - RETURN();
  197 + FORCE_RET();
198 198 }
199 199  
200 200 void glue(op_sd, MEMSUFFIX) (void)
201 201 {
202 202 glue(stq, MEMSUFFIX)(T0, T1);
203   - RETURN();
  203 + FORCE_RET();
204 204 }
205 205  
206 206 /* "half" load and stores. We must do the memory access inline,
... ... @@ -254,7 +254,7 @@ void glue(op_ldl, MEMSUFFIX) (void)
254 254 T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
255 255 }
256 256  
257   - RETURN();
  257 + FORCE_RET();
258 258 }
259 259  
260 260 void glue(op_ldr, MEMSUFFIX) (void)
... ... @@ -299,7 +299,7 @@ void glue(op_ldr, MEMSUFFIX) (void)
299 299 T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
300 300 }
301 301  
302   - RETURN();
  302 + FORCE_RET();
303 303 }
304 304  
305 305 void glue(op_sdl, MEMSUFFIX) (void)
... ... @@ -327,7 +327,7 @@ void glue(op_sdl, MEMSUFFIX) (void)
327 327 if (GET_LMASK64(T0) <= 0)
328 328 glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 7), (uint8_t)T1);
329 329  
330   - RETURN();
  330 + FORCE_RET();
331 331 }
332 332  
333 333 void glue(op_sdr, MEMSUFFIX) (void)
... ... @@ -355,7 +355,7 @@ void glue(op_sdr, MEMSUFFIX) (void)
355 355 if (GET_LMASK64(T0) == 7)
356 356 glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -7), (uint8_t)(T1 >> 56));
357 357  
358   - RETURN();
  358 + FORCE_RET();
359 359 }
360 360  
361 361 void glue(op_lld, MEMSUFFIX) (void)
... ... @@ -363,7 +363,7 @@ void glue(op_lld, MEMSUFFIX) (void)
363 363 T1 = T0;
364 364 T0 = glue(ldq, MEMSUFFIX)(T0);
365 365 env->CP0_LLAddr = T1;
366   - RETURN();
  366 + FORCE_RET();
367 367 }
368 368  
369 369 void glue(op_scd, MEMSUFFIX) (void)
... ... @@ -379,37 +379,37 @@ void glue(op_scd, MEMSUFFIX) (void)
379 379 } else {
380 380 T0 = 0;
381 381 }
382   - RETURN();
  382 + FORCE_RET();
383 383 }
384 384 #endif /* TARGET_MIPS64 */
385 385  
386 386 void glue(op_lwc1, MEMSUFFIX) (void)
387 387 {
388 388 WT0 = glue(ldl, MEMSUFFIX)(T0);
389   - RETURN();
  389 + FORCE_RET();
390 390 }
391 391 void glue(op_swc1, MEMSUFFIX) (void)
392 392 {
393 393 glue(stl, MEMSUFFIX)(T0, WT0);
394   - RETURN();
  394 + FORCE_RET();
395 395 }
396 396 void glue(op_ldc1, MEMSUFFIX) (void)
397 397 {
398 398 DT0 = glue(ldq, MEMSUFFIX)(T0);
399   - RETURN();
  399 + FORCE_RET();
400 400 }
401 401 void glue(op_sdc1, MEMSUFFIX) (void)
402 402 {
403 403 glue(stq, MEMSUFFIX)(T0, DT0);
404   - RETURN();
  404 + FORCE_RET();
405 405 }
406 406 void glue(op_luxc1, MEMSUFFIX) (void)
407 407 {
408 408 DT0 = glue(ldq, MEMSUFFIX)(T0 & ~0x7);
409   - RETURN();
  409 + FORCE_RET();
410 410 }
411 411 void glue(op_suxc1, MEMSUFFIX) (void)
412 412 {
413 413 glue(stq, MEMSUFFIX)(T0 & ~0x7, DT0);
414   - RETURN();
  414 + FORCE_RET();
415 415 }
... ...
target-mips/op_template.c
  View file @8f6f602
... ... @@ -22,44 +22,44 @@
22 22 void glue(op_load_gpr_T0_gpr, REG) (void)
23 23 {
24 24 T0 = env->gpr[REG][env->current_tc];
25   - RETURN();
  25 + FORCE_RET();
26 26 }
27 27  
28 28 void glue(op_store_T0_gpr_gpr, REG) (void)
29 29 {
30 30 env->gpr[REG][env->current_tc] = T0;
31   - RETURN();
  31 + FORCE_RET();
32 32 }
33 33  
34 34 void glue(op_load_gpr_T1_gpr, REG) (void)
35 35 {
36 36 T1 = env->gpr[REG][env->current_tc];
37   - RETURN();
  37 + FORCE_RET();
38 38 }
39 39  
40 40 void glue(op_store_T1_gpr_gpr, REG) (void)
41 41 {
42 42 env->gpr[REG][env->current_tc] = T1;
43   - RETURN();
  43 + FORCE_RET();
44 44 }
45 45  
46 46 void glue(op_load_gpr_T2_gpr, REG) (void)
47 47 {
48 48 T2 = env->gpr[REG][env->current_tc];
49   - RETURN();
  49 + FORCE_RET();
50 50 }
51 51  
52 52  
53 53 void glue(op_load_srsgpr_T0_gpr, REG) (void)
54 54 {
55 55 T0 = env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf];
56   - RETURN();
  56 + FORCE_RET();
57 57 }
58 58  
59 59 void glue(op_store_T0_srsgpr_gpr, REG) (void)
60 60 {
61 61 env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf] = T0;
62   - RETURN();
  62 + FORCE_RET();
63 63 }
64 64 #endif
65 65  
... ... @@ -68,12 +68,12 @@ void glue(op_store_T0_srsgpr_gpr, REG) (void)
68 68 void glue(op_set, tregname)(void) \
69 69 { \
70 70 treg = (int32_t)PARAM1; \
71   - RETURN(); \
  71 + FORCE_RET(); \
72 72 } \
73 73 void glue(op_reset, tregname)(void) \
74 74 { \
75 75 treg = 0; \
76   - RETURN(); \
  76 + FORCE_RET(); \
77 77 } \
78 78  
79 79 SET_RESET(T0, _T0)
... ... @@ -87,7 +87,7 @@ SET_RESET(T2, _T2)
87 87 void glue(op_set64, tregname)(void) \
88 88 { \
89 89 treg = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2; \
90   - RETURN(); \
  90 + FORCE_RET(); \
91 91 }
92 92  
93 93 SET64(T0, _T0)
... ...