Commit 8f46820d920b9cd149559b5d32e6b306ee2e24ba
1 parent
dbb2c921
update
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1124 c046a42c-6fe2-441c-8c8c-71466251a162
Showing
1 changed file
with
24 additions
and
4 deletions
TODO
| 1 | 1 | short term: |
| 2 | 2 | ---------- |
| 3 | +- debug option in 'configure' script + disable -fomit-frame-pointer | |
| 4 | +- VGA font change fix | |
| 5 | +- PIC spurious interrupt patch | |
| 6 | +- VNC keyboard patch | |
| 7 | +- merge Solaris patch | |
| 8 | +- merge ARM patches + self modifying code patch (Paul Brook) | |
| 9 | +- warning for OS/2: must not use 128 MB memory | |
| 10 | +- config file (at least for windows/Mac OS X) | |
| 11 | +- commit message if execution of code in IO memory | |
| 12 | +- update doc: PCI infos. | |
| 13 | +- VNC patch + Synaptic patch. | |
| 14 | +- basic VGA optimizations | |
| 15 | +- test sysenter/sysexit and fxsr for L4 pistachio 686 | |
| 3 | 16 | - physical memory cache (reduce qemu-fast address space size to about 32 MB) |
| 4 | 17 | - better code fetch (different exception handling + CS.limit support) |
| 5 | 18 | - do not resize vga if invalid size. |
| 6 | 19 | - avoid looping if only exceptions |
| 7 | -- handle fast timers + add explicit clocks | |
| 8 | 20 | - cycle counter for all archs |
| 9 | 21 | - TLB code protection support for PPC |
| 10 | -- add sysenter/sysexit and fxsr for L4 pistachio 686 | |
| 11 | -- basic VGA optimizations | |
| 22 | +- see openMosix Doc | |
| 12 | 23 | - disable SMC handling for ARM/SPARC/PPC (not finished) |
| 13 | 24 | - see undefined flags for BTx insn |
| 14 | 25 | - user/kernel PUSHL/POPL in helper.c |
| ... | ... | @@ -22,8 +33,17 @@ short term: |
| 22 | 33 | - fix arm fpu rounding (at least for float->integer conversions) |
| 23 | 34 | - SMP support |
| 24 | 35 | |
| 36 | +ppc specific: | |
| 37 | +------------ | |
| 38 | +- TLB invalidate not needed if msr_pr changes | |
| 39 | +- endianness bugs in do_load_fpscr and do_store_fpscr | |
| 40 | +- SPR_ENCODE() not useful | |
| 41 | +- enable shift optimizations ? | |
| 42 | + | |
| 25 | 43 | lower priority: |
| 26 | 44 | -------------- |
| 45 | +- more friendly BIOS (logo) | |
| 46 | +- int15 ah=86: use better timing | |
| 27 | 47 | - HDD geometry in CMOS (not used except for very old DOS programs) |
| 28 | 48 | - suppress shift_mem ops |
| 29 | 49 | - fix some 16 bit sp push/pop overflow (pusha/popa, lcall lret) |
| ... | ... | @@ -32,7 +52,7 @@ lower priority: |
| 32 | 52 | - add IPC syscalls |
| 33 | 53 | - use -msoft-float on ARM |
| 34 | 54 | - use kernel traps for unaligned accesses on ARM ? |
| 35 | -- handle rare page fault cases (in particular if page fault in heplers or | |
| 55 | +- handle rare page fault cases (in particular if page fault in helpers or | |
| 36 | 56 | in syscall emulation code). |
| 37 | 57 | - fix thread stack freeing (use kernel 2.5.x CLONE_CHILD_CLEARTID) |
| 38 | 58 | - more syscalls (in particular all 64 bit ones, IPCs, fix 64 bit | ... | ... |