gwj / at91sam9263 · Commits

Commit 8e9ade681b18a668d7e3a69b3c34a8a1696e8f79

Authored by ths
1 parent 70cff25e

Switch MIPS branch handling to TCG, and clean out pointless wrapper 

functions/macros.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4533 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 286 additions and 450 deletions
target-mips/op.c
  View file @8e9ade6
... ... @@ -479,48 +479,6 @@ void op_movt (void)
479 479 FORCE_RET();
480 480 }
481 481  
482   -/* Branches */
483   -/* Branch to register */
484   -void op_save_breg_target (void)
485   -{
486   - env->btarget = T1;
487   - FORCE_RET();
488   -}
489   -
490   -void op_breg (void)
491   -{
492   - env->PC[env->current_tc] = env->btarget;
493   - FORCE_RET();
494   -}
495   -
496   -void op_save_btarget (void)
497   -{
498   - env->btarget = PARAM1;
499   - FORCE_RET();
500   -}
501   -
502   -#if defined(TARGET_MIPS64)
503   -void op_save_btarget64 (void)
504   -{
505   - env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
506   - FORCE_RET();
507   -}
508   -#endif
509   -
510   -/* Conditional branch */
511   -void op_set_bcond (void)
512   -{
513   - env->bcond = T0;
514   - FORCE_RET();
515   -}
516   -
517   -void op_jnz_bcond (void)
518   -{
519   - if (env->bcond)
520   - GOTO_LABEL_PARAM(1);
521   - FORCE_RET();
522   -}
523   -
524 482 /* CP0 functions */
525 483 void op_mfc0_index (void)
526 484 {
... ... @@ -2564,20 +2522,6 @@ void op_save_state (void)
2564 2522 FORCE_RET();
2565 2523 }
2566 2524  
2567   -void op_save_pc (void)
2568   -{
2569   - env->PC[env->current_tc] = PARAM1;
2570   - FORCE_RET();
2571   -}
2572   -
2573   -#if defined(TARGET_MIPS64)
2574   -void op_save_pc64 (void)
2575   -{
2576   - env->PC[env->current_tc] = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
2577   - FORCE_RET();
2578   -}
2579   -#endif
2580   -
2581 2525 void op_wait (void)
2582 2526 {
2583 2527 env->halted = 1;
... ...
target-mips/translate.c
  View file @8e9ade6
... ... @@ -465,122 +465,108 @@ static void dead_tmp(TCGv tmp)
465 465 temps[i] = tmp;
466 466 }
467 467  
468   -/* General purpose registers moves */
469   -const unsigned char *regnames[] =
  468 +typedef struct DisasContext {
  469 + struct TranslationBlock *tb;
  470 + target_ulong pc, saved_pc;
  471 + uint32_t opcode;
  472 + uint32_t fp_status;
  473 + /* Routine used to access memory */
  474 + int mem_idx;
  475 + uint32_t hflags, saved_hflags;
  476 + int bstate;
  477 + target_ulong btarget;
  478 +} DisasContext;
  479 +
  480 +enum {
  481 + BS_NONE = 0, /* We go out of the TB without reaching a branch or an
  482 + * exception condition
  483 + */
  484 + BS_STOP = 1, /* We want to stop translation for any reason */
  485 + BS_BRANCH = 2, /* We reached a branch condition */
  486 + BS_EXCP = 3, /* We reached an exception condition */
  487 +};
  488 +
  489 +static const char *regnames[] =
470 490 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
471 491 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
472 492 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
473 493 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
474 494  
475   -static inline void gen_op_load_gpr_TN(int t_index, int reg)
476   -{
477   - tcg_gen_ld_tl(cpu_T[t_index], current_tc_gprs, sizeof(target_ulong) * reg);
478   -}
479   -
480   -static inline void gen_op_load_gpr_T0(int reg)
481   -{
482   - gen_op_load_gpr_TN(0, reg);
483   -}
484   -
485   -static inline void gen_op_load_gpr_T1(int reg)
486   -{
487   - gen_op_load_gpr_TN(1, reg);
488   -}
489   -
490   -static inline void gen_op_store_gpr_TN(int t_index, int reg)
491   -{
492   - tcg_gen_st_tl(cpu_T[t_index], current_tc_gprs, sizeof(target_ulong) * reg);
493   -}
494   -
495   -static inline void gen_op_store_gpr_T0(int reg)
496   -{
497   - gen_op_store_gpr_TN(0, reg);
498   -}
499   -
500   -static inline void gen_op_store_gpr_T1(int reg)
501   -{
502   - gen_op_store_gpr_TN(1, reg);
503   -}
504   -
505   -/* Moves to/from shadow registers */
506   -static inline void gen_op_load_srsgpr_T0(int reg)
507   -{
508   - TCGv r_tmp = new_tmp();
509   -
510   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
511   - tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
512   - tcg_gen_andi_i32(r_tmp, r_tmp, 0xf);
513   - tcg_gen_muli_i32(r_tmp, r_tmp, sizeof(target_ulong) * 32);
514   - tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);
515   -
516   - tcg_gen_ld_tl(cpu_T[0], r_tmp, sizeof(target_ulong) * reg);
517   - dead_tmp(r_tmp);
518   -}
519   -
520   -static inline void gen_op_store_srsgpr_T0(int reg)
521   -{
522   - TCGv r_tmp = new_tmp();
  495 +static const char *fregnames[] =
  496 + { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
  497 + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
  498 + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
  499 + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
523 500  
524   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
525   - tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
526   - tcg_gen_andi_i32(r_tmp, r_tmp, 0xf);
527   - tcg_gen_muli_i32(r_tmp, r_tmp, sizeof(target_ulong) * 32);
528   - tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);
  501 +#ifdef MIPS_DEBUG_DISAS
  502 +#define MIPS_DEBUG(fmt, args...) \
  503 +do { \
  504 + if (loglevel & CPU_LOG_TB_IN_ASM) { \
  505 + fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
  506 + ctx->pc, ctx->opcode , ##args); \
  507 + } \
  508 +} while (0)
  509 +#else
  510 +#define MIPS_DEBUG(fmt, args...) do { } while(0)
  511 +#endif
529 512  
530   - tcg_gen_st_tl(cpu_T[0], r_tmp, sizeof(target_ulong) * reg);
531   - dead_tmp(r_tmp);
532   -}
  513 +#define MIPS_INVAL(op) \
  514 +do { \
  515 + MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
  516 + ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
  517 +} while (0)
533 518  
534   -/* Load immediates, zero being a special case. */
535   -static inline void gen_op_set_T0(target_ulong arg)
  519 +/* General purpose registers moves. */
  520 +static inline void gen_load_gpr (TCGv t, int reg)
536 521 {
537   - tcg_gen_movi_tl(cpu_T[0], arg);
  522 + if (reg == 0)
  523 + tcg_gen_movi_tl(t, 0);
  524 + else
  525 + tcg_gen_ld_tl(t, current_tc_gprs, sizeof(target_ulong) * reg);
538 526 }
539 527  
540   -static inline void gen_op_set_T1(target_ulong arg)
  528 +static inline void gen_store_gpr (TCGv t, int reg)
541 529 {
542   - tcg_gen_movi_tl(cpu_T[1], arg);
  530 + if (reg != 0)
  531 + tcg_gen_st_tl(t, current_tc_gprs, sizeof(target_ulong) * reg);
543 532 }
544 533  
545   -static inline void gen_op_reset_T0(void)
  534 +/* Moves to/from shadow registers. */
  535 +static inline void gen_load_srsgpr (TCGv t, int reg)
546 536 {
547   - tcg_gen_movi_tl(cpu_T[0], 0);
548   -}
  537 + if (reg == 0)
  538 + tcg_gen_movi_tl(t, 0);
  539 + else {
  540 + TCGv r_tmp = new_tmp();
549 541  
550   -static inline void gen_op_reset_T1(void)
551   -{
552   - tcg_gen_movi_tl(cpu_T[1], 0);
553   -}
  542 + tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
  543 + tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
  544 + tcg_gen_andi_i32(r_tmp, r_tmp, 0xf);
  545 + tcg_gen_muli_i32(r_tmp, r_tmp, sizeof(target_ulong) * 32);
  546 + tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);
554 547  
555   -/* Moves to/from HI/LO registers. */
556   -static inline void gen_op_load_HI(int reg)
557   -{
558   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, HI[reg]));
  548 + tcg_gen_ld_tl(t, r_tmp, sizeof(target_ulong) * reg);
  549 + dead_tmp(r_tmp);
  550 + }
559 551 }
560 552  
561   -static inline void gen_op_store_HI(int reg)
  553 +static inline void gen_store_srsgpr (TCGv t, int reg)
562 554 {
563   - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, HI[reg]));
564   -}
  555 + if (reg != 0) {
  556 + TCGv r_tmp = new_tmp();
565 557  
566   -static inline void gen_op_load_LO(int reg)
567   -{
568   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, LO[reg]));
569   -}
  558 + tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
  559 + tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
  560 + tcg_gen_andi_i32(r_tmp, r_tmp, 0xf);
  561 + tcg_gen_muli_i32(r_tmp, r_tmp, sizeof(target_ulong) * 32);
  562 + tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);
570 563  
571   -static inline void gen_op_store_LO(int reg)
572   -{
573   - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, LO[reg]));
  564 + tcg_gen_st_tl(t, r_tmp, sizeof(target_ulong) * reg);
  565 + dead_tmp(r_tmp);
  566 + }
574 567 }
575 568  
576   -
577 569 /* Floating point register moves. */
578   -static const char *fregnames[] =
579   - { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
580   - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
581   - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
582   - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
583   -
584 570 #define FGEN32(func, NAME) \
585 571 static GenOpFunc *NAME ## _table [32] = { \
586 572 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
... ... @@ -624,6 +610,16 @@ FGEN32(gen_op_store_fpr_WTH1, gen_op_store_fpr_WTH1_fpr);
624 610 FGEN32(gen_op_load_fpr_WTH2, gen_op_load_fpr_WTH2_fpr);
625 611 FGEN32(gen_op_store_fpr_WTH2, gen_op_store_fpr_WTH2_fpr);
626 612  
  613 +#define GEN_LOAD_FREG_FTN(FTn, Fn) \
  614 +do { \
  615 + glue(gen_op_load_fpr_, FTn)(Fn); \
  616 +} while (0)
  617 +
  618 +#define GEN_STORE_FTN_FREG(Fn, FTn) \
  619 +do { \
  620 + glue(gen_op_store_fpr_, FTn)(Fn); \
  621 +} while (0)
  622 +
627 623 #define FOP_CONDS(type, fmt) \
628 624 static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \
629 625 gen_op_cmp ## type ## _ ## fmt ## _f, \
... ... @@ -663,10 +659,10 @@ void glue(gen_op_, name) (void) \
663 659 int l2 = gen_new_label(); \
664 660 \
665 661 tcg_gen_brcond_tl(cond, cpu_T[0], cpu_T[1], l1); \
666   - gen_op_set_T0(0); \
  662 + tcg_gen_movi_tl(cpu_T[0], 0); \
667 663 tcg_gen_br(l2); \
668 664 gen_set_label(l1); \
669   - gen_op_set_T0(1); \
  665 + tcg_gen_movi_tl(cpu_T[0], 1); \
670 666 gen_set_label(l2); \
671 667 }
672 668 OP_COND(eq, TCG_COND_EQ);
... ... @@ -684,10 +680,10 @@ void glue(gen_op_, name) (target_ulong val) \
684 680 int l2 = gen_new_label(); \
685 681 \
686 682 tcg_gen_brcond_tl(cond, cpu_T[0], tcg_const_tl(val), l1); \
687   - gen_op_set_T0(0); \
  683 + tcg_gen_movi_tl(cpu_T[0], 0); \
688 684 tcg_gen_br(l2); \
689 685 gen_set_label(l1); \
690   - gen_op_set_T0(1); \
  686 + tcg_gen_movi_tl(cpu_T[0], 1); \
691 687 gen_set_label(l2); \
692 688 }
693 689 OP_CONDI(lti, TCG_COND_LT);
... ... @@ -701,10 +697,10 @@ void glue(gen_op_, name) (void) \
701 697 int l2 = gen_new_label(); \
702 698 \
703 699 tcg_gen_brcond_tl(cond, cpu_T[0], tcg_const_tl(0), l1); \
704   - gen_op_set_T0(0); \
  700 + tcg_gen_movi_tl(cpu_T[0], 0); \
705 701 tcg_gen_br(l2); \
706 702 gen_set_label(l1); \
707   - gen_op_set_T0(1); \
  703 + tcg_gen_movi_tl(cpu_T[0], 1); \
708 704 gen_set_label(l2); \
709 705 }
710 706 OP_CONDZ(gez, TCG_COND_GE);
... ... @@ -713,142 +709,52 @@ OP_CONDZ(lez, TCG_COND_LE);
713 709 OP_CONDZ(ltz, TCG_COND_LT);
714 710 #undef OP_CONDZ
715 711  
  712 +static inline void gen_save_pc(target_ulong pc)
  713 +{
  714 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
  715 + TCGv r_tc_off = new_tmp();
  716 + TCGv r_tc_off_tl = tcg_temp_new(TCG_TYPE_TL);
  717 + TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
  718 +
  719 + tcg_gen_movi_tl(r_tmp, pc);
  720 + tcg_gen_ld_i32(r_tc_off, cpu_env, offsetof(CPUState, current_tc));
  721 + tcg_gen_muli_i32(r_tc_off, r_tc_off, sizeof(target_ulong));
  722 + tcg_gen_ext_i32_ptr(r_tc_off_tl, r_tc_off);
  723 + tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_tl);
  724 + tcg_gen_st_tl(r_tmp, r_ptr, offsetof(CPUState, PC));
  725 + dead_tmp(r_tc_off);
  726 +}
716 727  
717   -typedef struct DisasContext {
718   - struct TranslationBlock *tb;
719   - target_ulong pc, saved_pc;
720   - uint32_t opcode;
721   - uint32_t fp_status;
722   - /* Routine used to access memory */
723   - int mem_idx;
724   - uint32_t hflags, saved_hflags;
725   - int bstate;
726   - target_ulong btarget;
727   - void *last_T0_store;
728   - int last_T0_gpr;
729   -} DisasContext;
730   -
731   -enum {
732   - BS_NONE = 0, /* We go out of the TB without reaching a branch or an
733   - * exception condition
734   - */
735   - BS_STOP = 1, /* We want to stop translation for any reason */
736   - BS_BRANCH = 2, /* We reached a branch condition */
737   - BS_EXCP = 3, /* We reached an exception condition */
738   -};
739   -
740   -#ifdef MIPS_DEBUG_DISAS
741   -#define MIPS_DEBUG(fmt, args...) \
742   -do { \
743   - if (loglevel & CPU_LOG_TB_IN_ASM) { \
744   - fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
745   - ctx->pc, ctx->opcode , ##args); \
746   - } \
747   -} while (0)
748   -#else
749   -#define MIPS_DEBUG(fmt, args...) do { } while(0)
750   -#endif
751   -
752   -#define MIPS_INVAL(op) \
753   -do { \
754   - MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
755   - ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
756   -} while (0)
757   -
758   -#define GEN_LOAD_REG_T0(Rn) \
759   -do { \
760   - if (Rn == 0) { \
761   - gen_op_reset_T0(); \
762   - } else { \
763   - if (ctx->glue(last_T0, _store) != gen_opc_ptr \
764   - || ctx->glue(last_T0, _gpr) != Rn) { \
765   - gen_op_load_gpr_T0(Rn); \
766   - } \
767   - } \
768   -} while (0)
769   -
770   -#define GEN_LOAD_REG_T1(Rn) \
771   -do { \
772   - if (Rn == 0) { \
773   - gen_op_reset_T1(); \
774   - } else { \
775   - gen_op_load_gpr_T1(Rn); \
776   - } \
777   -} while (0)
778   -
779   -#define GEN_LOAD_SRSREG_TN(Tn, Rn) \
780   -do { \
781   - if (Rn == 0) { \
782   - glue(gen_op_reset_, Tn)(); \
783   - } else { \
784   - glue(gen_op_load_srsgpr_, Tn)(Rn); \
785   - } \
786   -} while (0)
787   -
788   -#define GEN_LOAD_IMM_TN(Tn, Imm) \
789   -do { \
790   - if (Imm == 0) { \
791   - glue(gen_op_reset_, Tn)(); \
792   - } else { \
793   - glue(gen_op_set_, Tn)(Imm); \
794   - } \
795   -} while (0)
796   -
797   -#define GEN_STORE_T0_REG(Rn) \
798   -do { \
799   - if (Rn != 0) { \
800   - gen_op_store_gpr_T0(Rn); \
801   - ctx->glue(last_T0,_store) = gen_opc_ptr; \
802   - ctx->glue(last_T0,_gpr) = Rn; \
803   - } \
804   -} while (0)
805   -
806   -#define GEN_STORE_T1_REG(Rn) \
807   -do { \
808   - if (Rn != 0) \
809   - gen_op_store_gpr_T1(Rn); \
810   -} while (0)
811   -
812   -#define GEN_STORE_TN_SRSREG(Rn, Tn) \
813   -do { \
814   - if (Rn != 0) \
815   - glue(gen_op_store_srsgpr_, Tn)(Rn); \
816   -} while (0)
817   -
818   -#define GEN_LOAD_FREG_FTN(FTn, Fn) \
819   -do { \
820   - glue(gen_op_load_fpr_, FTn)(Fn); \
821   -} while (0)
822   -
823   -#define GEN_STORE_FTN_FREG(Fn, FTn) \
824   -do { \
825   - glue(gen_op_store_fpr_, FTn)(Fn); \
826   -} while (0)
  728 +static inline void gen_breg_pc(void)
  729 +{
  730 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
  731 + TCGv r_tc_off = new_tmp();
  732 + TCGv r_tc_off_tl = tcg_temp_new(TCG_TYPE_TL);
  733 + TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
  734 +
  735 + tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, btarget));
  736 + tcg_gen_ld_i32(r_tc_off, cpu_env, offsetof(CPUState, current_tc));
  737 + tcg_gen_muli_i32(r_tc_off, r_tc_off, sizeof(target_ulong));
  738 + tcg_gen_ext_i32_ptr(r_tc_off_tl, r_tc_off);
  739 + tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_tl);
  740 + tcg_gen_st_tl(r_tmp, r_ptr, offsetof(CPUState, PC));
  741 + dead_tmp(r_tc_off);
  742 +}
827 743  
828   -static always_inline void gen_save_pc(target_ulong pc)
  744 +static inline void gen_save_btarget(target_ulong btarget)
829 745 {
830   -#if defined(TARGET_MIPS64)
831   - if (pc == (int32_t)pc) {
832   - gen_op_save_pc(pc);
833   - } else {
834   - gen_op_save_pc64(pc >> 32, (uint32_t)pc);
835   - }
836   -#else
837   - gen_op_save_pc(pc);
838   -#endif
  746 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
  747 +
  748 + tcg_gen_movi_tl(r_tmp, btarget);
  749 + tcg_gen_st_tl(r_tmp, cpu_env, offsetof(CPUState, btarget));
839 750 }
840 751  
841   -static always_inline void gen_save_btarget(target_ulong btarget)
  752 +static always_inline void gen_save_breg_target(int reg)
842 753 {
843   -#if defined(TARGET_MIPS64)
844   - if (btarget == (int32_t)btarget) {
845   - gen_op_save_btarget(btarget);
846   - } else {
847   - gen_op_save_btarget64(btarget >> 32, (uint32_t)btarget);
848   - }
849   -#else
850   - gen_op_save_btarget(btarget);
851   -#endif
  754 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
  755 +
  756 + gen_load_gpr(r_tmp, reg);
  757 + tcg_gen_st_tl(r_tmp, cpu_env, offsetof(CPUState, btarget));
852 758 }
853 759  
854 760 static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
... ... @@ -1135,12 +1041,12 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
1135 1041 const char *opn = "ldst";
1136 1042  
1137 1043 if (base == 0) {
1138   - GEN_LOAD_IMM_TN(T0, offset);
  1044 + tcg_gen_movi_tl(cpu_T[0], offset);
1139 1045 } else if (offset == 0) {
1140   - gen_op_load_gpr_T0(base);
  1046 + gen_load_gpr(cpu_T[0], base);
1141 1047 } else {
1142   - gen_op_load_gpr_T0(base);
1143   - gen_op_set_T1(offset);
  1048 + gen_load_gpr(cpu_T[0], base);
  1049 + tcg_gen_movi_tl(cpu_T[1], offset);
1144 1050 gen_op_addr_add();
1145 1051 }
1146 1052 /* Don't do NOP if destination is zero: we must perform the actual
... ... @@ -1149,126 +1055,126 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
1149 1055 #if defined(TARGET_MIPS64)
1150 1056 case OPC_LWU:
1151 1057 op_ldst_lwu(ctx);
1152   - GEN_STORE_T0_REG(rt);
  1058 + gen_store_gpr(cpu_T[0], rt);
1153 1059 opn = "lwu";
1154 1060 break;
1155 1061 case OPC_LD:
1156 1062 op_ldst_ld(ctx);
1157   - GEN_STORE_T0_REG(rt);
  1063 + gen_store_gpr(cpu_T[0], rt);
1158 1064 opn = "ld";
1159 1065 break;
1160 1066 case OPC_LLD:
1161 1067 op_ldst_lld(ctx);
1162   - GEN_STORE_T0_REG(rt);
  1068 + gen_store_gpr(cpu_T[0], rt);
1163 1069 opn = "lld";
1164 1070 break;
1165 1071 case OPC_SD:
1166   - GEN_LOAD_REG_T1(rt);
  1072 + gen_load_gpr(cpu_T[1], rt);
1167 1073 op_ldst_sd(ctx);
1168 1074 opn = "sd";
1169 1075 break;
1170 1076 case OPC_SCD:
1171 1077 save_cpu_state(ctx, 1);
1172   - GEN_LOAD_REG_T1(rt);
  1078 + gen_load_gpr(cpu_T[1], rt);
1173 1079 op_ldst_scd(ctx);
1174   - GEN_STORE_T0_REG(rt);
  1080 + gen_store_gpr(cpu_T[0], rt);
1175 1081 opn = "scd";
1176 1082 break;
1177 1083 case OPC_LDL:
1178   - GEN_LOAD_REG_T1(rt);
  1084 + gen_load_gpr(cpu_T[1], rt);
1179 1085 op_ldst(ldl);
1180   - GEN_STORE_T1_REG(rt);
  1086 + gen_store_gpr(cpu_T[1], rt);
1181 1087 opn = "ldl";
1182 1088 break;
1183 1089 case OPC_SDL:
1184   - GEN_LOAD_REG_T1(rt);
  1090 + gen_load_gpr(cpu_T[1], rt);
1185 1091 op_ldst(sdl);
1186 1092 opn = "sdl";
1187 1093 break;
1188 1094 case OPC_LDR:
1189   - GEN_LOAD_REG_T1(rt);
  1095 + gen_load_gpr(cpu_T[1], rt);
1190 1096 op_ldst(ldr);
1191   - GEN_STORE_T1_REG(rt);
  1097 + gen_store_gpr(cpu_T[1], rt);
1192 1098 opn = "ldr";
1193 1099 break;
1194 1100 case OPC_SDR:
1195   - GEN_LOAD_REG_T1(rt);
  1101 + gen_load_gpr(cpu_T[1], rt);
1196 1102 op_ldst(sdr);
1197 1103 opn = "sdr";
1198 1104 break;
1199 1105 #endif
1200 1106 case OPC_LW:
1201 1107 op_ldst_lw(ctx);
1202   - GEN_STORE_T0_REG(rt);
  1108 + gen_store_gpr(cpu_T[0], rt);
1203 1109 opn = "lw";
1204 1110 break;
1205 1111 case OPC_SW:
1206   - GEN_LOAD_REG_T1(rt);
  1112 + gen_load_gpr(cpu_T[1], rt);
1207 1113 op_ldst_sw(ctx);
1208 1114 opn = "sw";
1209 1115 break;
1210 1116 case OPC_LH:
1211 1117 op_ldst_lh(ctx);
1212   - GEN_STORE_T0_REG(rt);
  1118 + gen_store_gpr(cpu_T[0], rt);
1213 1119 opn = "lh";
1214 1120 break;
1215 1121 case OPC_SH:
1216   - GEN_LOAD_REG_T1(rt);
  1122 + gen_load_gpr(cpu_T[1], rt);
1217 1123 op_ldst_sh(ctx);
1218 1124 opn = "sh";
1219 1125 break;
1220 1126 case OPC_LHU:
1221 1127 op_ldst_lhu(ctx);
1222   - GEN_STORE_T0_REG(rt);
  1128 + gen_store_gpr(cpu_T[0], rt);
1223 1129 opn = "lhu";
1224 1130 break;
1225 1131 case OPC_LB:
1226 1132 op_ldst_lb(ctx);
1227   - GEN_STORE_T0_REG(rt);
  1133 + gen_store_gpr(cpu_T[0], rt);
1228 1134 opn = "lb";
1229 1135 break;
1230 1136 case OPC_SB:
1231   - GEN_LOAD_REG_T1(rt);
  1137 + gen_load_gpr(cpu_T[1], rt);
1232 1138 op_ldst_sb(ctx);
1233 1139 opn = "sb";
1234 1140 break;
1235 1141 case OPC_LBU:
1236 1142 op_ldst_lbu(ctx);
1237   - GEN_STORE_T0_REG(rt);
  1143 + gen_store_gpr(cpu_T[0], rt);
1238 1144 opn = "lbu";
1239 1145 break;
1240 1146 case OPC_LWL:
1241   - GEN_LOAD_REG_T1(rt);
  1147 + gen_load_gpr(cpu_T[1], rt);
1242 1148 op_ldst(lwl);
1243   - GEN_STORE_T1_REG(rt);
  1149 + gen_store_gpr(cpu_T[1], rt);
1244 1150 opn = "lwl";
1245 1151 break;
1246 1152 case OPC_SWL:
1247   - GEN_LOAD_REG_T1(rt);
  1153 + gen_load_gpr(cpu_T[1], rt);
1248 1154 op_ldst(swl);
1249 1155 opn = "swr";
1250 1156 break;
1251 1157 case OPC_LWR:
1252   - GEN_LOAD_REG_T1(rt);
  1158 + gen_load_gpr(cpu_T[1], rt);
1253 1159 op_ldst(lwr);
1254   - GEN_STORE_T1_REG(rt);
  1160 + gen_store_gpr(cpu_T[1], rt);
1255 1161 opn = "lwr";
1256 1162 break;
1257 1163 case OPC_SWR:
1258   - GEN_LOAD_REG_T1(rt);
  1164 + gen_load_gpr(cpu_T[1], rt);
1259 1165 op_ldst(swr);
1260 1166 opn = "swr";
1261 1167 break;
1262 1168 case OPC_LL:
1263 1169 op_ldst_ll(ctx);
1264   - GEN_STORE_T0_REG(rt);
  1170 + gen_store_gpr(cpu_T[0], rt);
1265 1171 opn = "ll";
1266 1172 break;
1267 1173 case OPC_SC:
1268 1174 save_cpu_state(ctx, 1);
1269   - GEN_LOAD_REG_T1(rt);
  1175 + gen_load_gpr(cpu_T[1], rt);
1270 1176 op_ldst_sc(ctx);
1271   - GEN_STORE_T0_REG(rt);
  1177 + gen_store_gpr(cpu_T[0], rt);
1272 1178 opn = "sc";
1273 1179 break;
1274 1180 default:
... ... @@ -1286,12 +1192,12 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
1286 1192 const char *opn = "flt_ldst";
1287 1193  
1288 1194 if (base == 0) {
1289   - GEN_LOAD_IMM_TN(T0, offset);
  1195 + tcg_gen_movi_tl(cpu_T[0], offset);
1290 1196 } else if (offset == 0) {
1291   - gen_op_load_gpr_T0(base);
  1197 + gen_load_gpr(cpu_T[0], base);
1292 1198 } else {
1293   - gen_op_load_gpr_T0(base);
1294   - gen_op_set_T1(offset);
  1199 + gen_load_gpr(cpu_T[0], base);
  1200 + tcg_gen_movi_tl(cpu_T[1], offset);
1295 1201 gen_op_addr_add();
1296 1202 }
1297 1203 /* Don't do NOP if destination is zero: we must perform the actual
... ... @@ -1349,15 +1255,15 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1349 1255 case OPC_SLTI:
1350 1256 case OPC_SLTIU:
1351 1257 uimm = (target_long)imm; /* Sign extend to 32/64 bits */
1352   - GEN_LOAD_IMM_TN(T1, uimm);
  1258 + tcg_gen_movi_tl(cpu_T[1], uimm);
1353 1259 /* Fall through. */
1354 1260 case OPC_ANDI:
1355 1261 case OPC_ORI:
1356 1262 case OPC_XORI:
1357   - GEN_LOAD_REG_T0(rs);
  1263 + gen_load_gpr(cpu_T[0], rs);
1358 1264 break;
1359 1265 case OPC_LUI:
1360   - GEN_LOAD_IMM_TN(T0, imm << 16);
  1266 + tcg_gen_movi_tl(cpu_T[0], imm << 16);
1361 1267 break;
1362 1268 case OPC_SLL:
1363 1269 case OPC_SRA:
... ... @@ -1371,7 +1277,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1371 1277 case OPC_DSRL32:
1372 1278 #endif
1373 1279 uimm &= 0x1f;
1374   - GEN_LOAD_REG_T0(rs);
  1280 + gen_load_gpr(cpu_T[0], rs);
1375 1281 break;
1376 1282 }
1377 1283 switch (opc) {
... ... @@ -1591,7 +1497,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1591 1497 generate_exception(ctx, EXCP_RI);
1592 1498 return;
1593 1499 }
1594   - GEN_STORE_T0_REG(rt);
  1500 + gen_store_gpr(cpu_T[0], rt);
1595 1501 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1596 1502 }
1597 1503  
... ... @@ -1608,14 +1514,14 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1608 1514 MIPS_DEBUG("NOP");
1609 1515 return;
1610 1516 }
1611   - GEN_LOAD_REG_T0(rs);
  1517 + gen_load_gpr(cpu_T[0], rs);
1612 1518 /* Specialcase the conventional move operation. */
1613 1519 if (rt == 0 && (opc == OPC_ADDU || opc == OPC_DADDU
1614 1520 || opc == OPC_SUBU || opc == OPC_DSUBU)) {
1615   - GEN_STORE_T0_REG(rd);
  1521 + gen_store_gpr(cpu_T[0], rd);
1616 1522 return;
1617 1523 }
1618   - GEN_LOAD_REG_T1(rt);
  1524 + gen_load_gpr(cpu_T[1], rt);
1619 1525 switch (opc) {
1620 1526 case OPC_ADD:
1621 1527 {
... ... @@ -1770,7 +1676,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1770 1676 int l1 = gen_new_label();
1771 1677  
1772 1678 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), l1);
1773   - gen_op_store_gpr_T0(rd);
  1679 + gen_store_gpr(cpu_T[0], rd);
1774 1680 gen_set_label(l1);
1775 1681 }
1776 1682 opn = "movn";
... ... @@ -1780,7 +1686,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1780 1686 int l1 = gen_new_label();
1781 1687  
1782 1688 tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[1], tcg_const_tl(0), l1);
1783   - gen_op_store_gpr_T0(rd);
  1689 + gen_store_gpr(cpu_T[0], rd);
1784 1690 gen_set_label(l1);
1785 1691 }
1786 1692 opn = "movz";
... ... @@ -1911,7 +1817,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1911 1817 generate_exception(ctx, EXCP_RI);
1912 1818 return;
1913 1819 }
1914   - GEN_STORE_T0_REG(rd);
  1820 + gen_store_gpr(cpu_T[0], rd);
1915 1821 print:
1916 1822 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1917 1823 }
... ... @@ -1928,23 +1834,23 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
1928 1834 }
1929 1835 switch (opc) {
1930 1836 case OPC_MFHI:
1931   - gen_op_load_HI(0);
1932   - GEN_STORE_T0_REG(reg);
  1837 + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, HI[0]));
  1838 + gen_store_gpr(cpu_T[0], reg);
1933 1839 opn = "mfhi";
1934 1840 break;
1935 1841 case OPC_MFLO:
1936   - gen_op_load_LO(0);
1937   - GEN_STORE_T0_REG(reg);
  1842 + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, LO[0]));
  1843 + gen_store_gpr(cpu_T[0], reg);
1938 1844 opn = "mflo";
1939 1845 break;
1940 1846 case OPC_MTHI:
1941   - GEN_LOAD_REG_T0(reg);
1942   - gen_op_store_HI(0);
  1847 + gen_load_gpr(cpu_T[0], reg);
  1848 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, HI[0]));
1943 1849 opn = "mthi";
1944 1850 break;
1945 1851 case OPC_MTLO:
1946   - GEN_LOAD_REG_T0(reg);
1947   - gen_op_store_LO(0);
  1852 + gen_load_gpr(cpu_T[0], reg);
  1853 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, LO[0]));
1948 1854 opn = "mtlo";
1949 1855 break;
1950 1856 default:
... ... @@ -1960,8 +1866,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1960 1866 {
1961 1867 const char *opn = "mul/div";
1962 1868  
1963   - GEN_LOAD_REG_T0(rs);
1964   - GEN_LOAD_REG_T1(rt);
  1869 + gen_load_gpr(cpu_T[0], rs);
  1870 + gen_load_gpr(cpu_T[1], rt);
1965 1871 switch (opc) {
1966 1872 case OPC_DIV:
1967 1873 {
... ... @@ -2138,8 +2044,8 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
2138 2044 {
2139 2045 const char *opn = "mul vr54xx";
2140 2046  
2141   - GEN_LOAD_REG_T0(rs);
2142   - GEN_LOAD_REG_T1(rt);
  2047 + gen_load_gpr(cpu_T[0], rs);
  2048 + gen_load_gpr(cpu_T[1], rt);
2143 2049  
2144 2050 switch (opc) {
2145 2051 case OPC_VR54XX_MULS:
... ... @@ -2203,7 +2109,7 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
2203 2109 generate_exception(ctx, EXCP_RI);
2204 2110 return;
2205 2111 }
2206   - GEN_STORE_T0_REG(rd);
  2112 + gen_store_gpr(cpu_T[0], rd);
2207 2113 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
2208 2114 }
2209 2115  
... ... @@ -2216,7 +2122,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
2216 2122 MIPS_DEBUG("NOP");
2217 2123 return;
2218 2124 }
2219   - GEN_LOAD_REG_T0(rs);
  2125 + gen_load_gpr(cpu_T[0], rs);
2220 2126 switch (opc) {
2221 2127 case OPC_CLO:
2222 2128 tcg_gen_helper_0_0(do_clo);
... ... @@ -2241,7 +2147,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
2241 2147 generate_exception(ctx, EXCP_RI);
2242 2148 return;
2243 2149 }
2244   - gen_op_store_gpr_T0(rd);
  2150 + gen_store_gpr(cpu_T[0], rd);
2245 2151 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
2246 2152 }
2247 2153  
... ... @@ -2262,8 +2168,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
2262 2168 case OPC_TNE:
2263 2169 /* Compare two registers */
2264 2170 if (rs != rt) {
2265   - GEN_LOAD_REG_T0(rs);
2266   - GEN_LOAD_REG_T1(rt);
  2171 + gen_load_gpr(cpu_T[0], rs);
  2172 + gen_load_gpr(cpu_T[1], rt);
2267 2173 cond = 1;
2268 2174 }
2269 2175 break;
... ... @@ -2275,8 +2181,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
2275 2181 case OPC_TNEI:
2276 2182 /* Compare register to immediate */
2277 2183 if (rs != 0 || imm != 0) {
2278   - GEN_LOAD_REG_T0(rs);
2279   - GEN_LOAD_IMM_TN(T1, (int32_t)imm);
  2184 + gen_load_gpr(cpu_T[0], rs);
  2185 + tcg_gen_movi_tl(cpu_T[1], (int32_t)imm);
2280 2186 cond = 1;
2281 2187 }
2282 2188 break;
... ... @@ -2290,7 +2196,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
2290 2196 case OPC_TGEU: /* rs >= rs unsigned */
2291 2197 case OPC_TGEIU: /* r0 >= 0 unsigned */
2292 2198 /* Always trap */
2293   - gen_op_set_T0(1);
  2199 + tcg_gen_movi_tl(cpu_T[0], 1);
2294 2200 break;
2295 2201 case OPC_TLT: /* rs < rs */
2296 2202 case OPC_TLTI: /* r0 < 0 */
... ... @@ -2356,19 +2262,6 @@ static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong des
2356 2262 }
2357 2263 }
2358 2264  
2359   -static inline void tcg_gen_set_bcond(void)
2360   -{
2361   - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
2362   -}
2363   -
2364   -static inline void tcg_gen_jnz_bcond(int label)
2365   -{
2366   - TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
2367   -
2368   - tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
2369   - tcg_gen_brcond_tl(TCG_COND_NE, r_tmp, tcg_const_tl(0), label);
2370   -}
2371   -
2372 2265 /* Branches (before delay slot) */
2373 2266 static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2374 2267 int rs, int rt, int32_t offset)
... ... @@ -2397,8 +2290,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2397 2290 case OPC_BNEL:
2398 2291 /* Compare two registers */
2399 2292 if (rs != rt) {
2400   - GEN_LOAD_REG_T0(rs);
2401   - GEN_LOAD_REG_T1(rt);
  2293 + gen_load_gpr(cpu_T[0], rs);
  2294 + gen_load_gpr(cpu_T[1], rt);
2402 2295 bcond = 1;
2403 2296 }
2404 2297 btarget = ctx->pc + 4 + offset;
... ... @@ -2417,7 +2310,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2417 2310 case OPC_BLTZL:
2418 2311 /* Compare to zero */
2419 2312 if (rs != 0) {
2420   - gen_op_load_gpr_T0(rs);
  2313 + gen_load_gpr(cpu_T[0], rs);
2421 2314 bcond = 1;
2422 2315 }
2423 2316 btarget = ctx->pc + 4 + offset;
... ... @@ -2437,8 +2330,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2437 2330 generate_exception(ctx, EXCP_RI);
2438 2331 return;
2439 2332 }
2440   - GEN_LOAD_REG_T1(rs);
2441   - gen_op_save_breg_target();
  2333 + gen_save_breg_target(rs);
2442 2334 break;
2443 2335 default:
2444 2336 MIPS_INVAL("branch/jump");
... ... @@ -2472,13 +2364,13 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2472 2364 MIPS_DEBUG("bnever (NOP)");
2473 2365 return;
2474 2366 case OPC_BLTZAL: /* 0 < 0 */
2475   - GEN_LOAD_IMM_TN(T0, ctx->pc + 8);
2476   - gen_op_store_gpr_T0(31);
  2367 + tcg_gen_movi_tl(cpu_T[0], ctx->pc + 8);
  2368 + gen_store_gpr(cpu_T[0], 31);
2477 2369 MIPS_DEBUG("bnever and link");
2478 2370 return;
2479 2371 case OPC_BLTZALL: /* 0 < 0 likely */
2480   - GEN_LOAD_IMM_TN(T0, ctx->pc + 8);
2481   - gen_op_store_gpr_T0(31);
  2372 + tcg_gen_movi_tl(cpu_T[0], ctx->pc + 8);
  2373 + gen_store_gpr(cpu_T[0], 31);
2482 2374 /* Skip the instruction in the delay slot */
2483 2375 MIPS_DEBUG("bnever, link and skip");
2484 2376 ctx->pc += 4;
... ... @@ -2583,7 +2475,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2583 2475 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget);
2584 2476 not_likely:
2585 2477 ctx->hflags |= MIPS_HFLAG_BC;
2586   - tcg_gen_set_bcond();
  2478 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
2587 2479 break;
2588 2480 case OPC_BLTZALL:
2589 2481 gen_op_ltz();
... ... @@ -2591,7 +2483,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2591 2483 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget);
2592 2484 likely:
2593 2485 ctx->hflags |= MIPS_HFLAG_BL;
2594   - tcg_gen_set_bcond();
  2486 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
2595 2487 break;
2596 2488 default:
2597 2489 MIPS_INVAL("conditional branch/jump");
... ... @@ -2604,8 +2496,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2604 2496  
2605 2497 ctx->btarget = btarget;
2606 2498 if (blink > 0) {
2607   - GEN_LOAD_IMM_TN(T0, ctx->pc + 8);
2608   - gen_op_store_gpr_T0(blink);
  2499 + tcg_gen_movi_tl(cpu_T[0], ctx->pc + 8);
  2500 + gen_store_gpr(cpu_T[0], blink);
2609 2501 }
2610 2502 }
2611 2503  
... ... @@ -2613,7 +2505,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2613 2505 static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
2614 2506 int rs, int lsb, int msb)
2615 2507 {
2616   - GEN_LOAD_REG_T1(rs);
  2508 + gen_load_gpr(cpu_T[1], rs);
2617 2509 switch (opc) {
2618 2510 case OPC_EXT:
2619 2511 if (lsb + msb > 31)
... ... @@ -2640,26 +2532,26 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
2640 2532 case OPC_INS:
2641 2533 if (lsb > msb)
2642 2534 goto fail;
2643   - GEN_LOAD_REG_T0(rt);
  2535 + gen_load_gpr(cpu_T[0], rt);
2644 2536 gen_op_ins(lsb, msb - lsb + 1);
2645 2537 break;
2646 2538 #if defined(TARGET_MIPS64)
2647 2539 case OPC_DINSM:
2648 2540 if (lsb > msb)
2649 2541 goto fail;
2650   - GEN_LOAD_REG_T0(rt);
  2542 + gen_load_gpr(cpu_T[0], rt);
2651 2543 gen_op_dins(lsb, msb - lsb + 1 + 32);
2652 2544 break;
2653 2545 case OPC_DINSU:
2654 2546 if (lsb > msb)
2655 2547 goto fail;
2656   - GEN_LOAD_REG_T0(rt);
  2548 + gen_load_gpr(cpu_T[0], rt);
2657 2549 gen_op_dins(lsb + 32, msb - lsb + 1);
2658 2550 break;
2659 2551 case OPC_DINS:
2660 2552 if (lsb > msb)
2661 2553 goto fail;
2662   - GEN_LOAD_REG_T0(rt);
  2554 + gen_load_gpr(cpu_T[0], rt);
2663 2555 gen_op_dins(lsb, msb - lsb + 1);
2664 2556 break;
2665 2557 #endif
... ... @@ -2669,7 +2561,7 @@ fail:
2669 2561 generate_exception(ctx, EXCP_RI);
2670 2562 return;
2671 2563 }
2672   - GEN_STORE_T0_REG(rt);
  2564 + gen_store_gpr(cpu_T[0], rt);
2673 2565 }
2674 2566  
2675 2567 /* CP0 (MMU and control) */
... ... @@ -4993,10 +4885,10 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
4993 4885 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
4994 4886 ((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) !=
4995 4887 (env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE))))
4996   - gen_op_set_T0(-1);
  4888 + tcg_gen_movi_tl(cpu_T[0], -1);
4997 4889 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
4998 4890 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
4999   - gen_op_set_T0(-1);
  4891 + tcg_gen_movi_tl(cpu_T[0], -1);
5000 4892 else if (u == 0) {
5001 4893 switch (rt) {
5002 4894 case 2:
... ... @@ -5324,11 +5216,11 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5324 5216 return;
5325 5217 }
5326 5218 gen_mfc0(env, ctx, rd, ctx->opcode & 0x7);
5327   - gen_op_store_gpr_T0(rt);
  5219 + gen_store_gpr(cpu_T[0], rt);
5328 5220 opn = "mfc0";
5329 5221 break;
5330 5222 case OPC_MTC0:
5331   - GEN_LOAD_REG_T0(rt);
  5223 + gen_load_gpr(cpu_T[0], rt);
5332 5224 save_cpu_state(ctx, 1);
5333 5225 gen_mtc0(env, ctx, rd, ctx->opcode & 0x7);
5334 5226 opn = "mtc0";
... ... @@ -5341,12 +5233,12 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5341 5233 return;
5342 5234 }
5343 5235 gen_dmfc0(env, ctx, rd, ctx->opcode & 0x7);
5344   - gen_op_store_gpr_T0(rt);
  5236 + gen_store_gpr(cpu_T[0], rt);
5345 5237 opn = "dmfc0";
5346 5238 break;
5347 5239 case OPC_DMTC0:
5348 5240 check_insn(env, ctx, ISA_MIPS3);
5349   - GEN_LOAD_REG_T0(rt);
  5241 + gen_load_gpr(cpu_T[0], rt);
5350 5242 save_cpu_state(ctx, 1);
5351 5243 gen_dmtc0(env, ctx, rd, ctx->opcode & 0x7);
5352 5244 opn = "dmtc0";
... ... @@ -5360,12 +5252,12 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5360 5252 }
5361 5253 gen_mftr(env, ctx, rt, (ctx->opcode >> 5) & 1,
5362 5254 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
5363   - gen_op_store_gpr_T0(rd);
  5255 + gen_store_gpr(cpu_T[0], rd);
5364 5256 opn = "mftr";
5365 5257 break;
5366 5258 case OPC_MTTR:
5367 5259 check_insn(env, ctx, ASE_MT);
5368   - GEN_LOAD_REG_T0(rt);
  5260 + gen_load_gpr(cpu_T[0], rt);
5369 5261 gen_mttr(env, ctx, rd, (ctx->opcode >> 5) & 1,
5370 5262 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
5371 5263 opn = "mttr";
... ... @@ -5462,7 +5354,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5462 5354 opn = "bc1tl";
5463 5355 likely:
5464 5356 ctx->hflags |= MIPS_HFLAG_BL;
5465   - tcg_gen_set_bcond();
  5357 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
5466 5358 break;
5467 5359 case OPC_BC1FANY2:
5468 5360 gen_op_bc1any2f(cc);
... ... @@ -5481,7 +5373,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5481 5373 opn = "bc1any4t";
5482 5374 not_likely:
5483 5375 ctx->hflags |= MIPS_HFLAG_BC;
5484   - tcg_gen_set_bcond();
  5376 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
5485 5377 break;
5486 5378 default:
5487 5379 MIPS_INVAL(opn);
... ... @@ -5505,33 +5397,33 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5505 5397 case OPC_MFC1:
5506 5398 GEN_LOAD_FREG_FTN(WT0, fs);
5507 5399 gen_op_mfc1();
5508   - GEN_STORE_T0_REG(rt);
  5400 + gen_store_gpr(cpu_T[0], rt);
5509 5401 opn = "mfc1";
5510 5402 break;
5511 5403 case OPC_MTC1:
5512   - GEN_LOAD_REG_T0(rt);
  5404 + gen_load_gpr(cpu_T[0], rt);
5513 5405 gen_op_mtc1();
5514 5406 GEN_STORE_FTN_FREG(fs, WT0);
5515 5407 opn = "mtc1";
5516 5408 break;
5517 5409 case OPC_CFC1:
5518 5410 gen_op_cfc1(fs);
5519   - GEN_STORE_T0_REG(rt);
  5411 + gen_store_gpr(cpu_T[0], rt);
5520 5412 opn = "cfc1";
5521 5413 break;
5522 5414 case OPC_CTC1:
5523   - GEN_LOAD_REG_T0(rt);
  5415 + gen_load_gpr(cpu_T[0], rt);
5524 5416 gen_op_ctc1(fs);
5525 5417 opn = "ctc1";
5526 5418 break;
5527 5419 case OPC_DMFC1:
5528 5420 GEN_LOAD_FREG_FTN(DT0, fs);
5529 5421 gen_op_dmfc1();
5530   - GEN_STORE_T0_REG(rt);
  5422 + gen_store_gpr(cpu_T[0], rt);
5531 5423 opn = "dmfc1";
5532 5424 break;
5533 5425 case OPC_DMTC1:
5534   - GEN_LOAD_REG_T0(rt);
  5426 + gen_load_gpr(cpu_T[0], rt);
5535 5427 gen_op_dmtc1();
5536 5428 GEN_STORE_FTN_FREG(fs, DT0);
5537 5429 opn = "dmtc1";
... ... @@ -5539,11 +5431,11 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5539 5431 case OPC_MFHC1:
5540 5432 GEN_LOAD_FREG_FTN(WTH0, fs);
5541 5433 gen_op_mfhc1();
5542   - GEN_STORE_T0_REG(rt);
  5434 + gen_store_gpr(cpu_T[0], rt);
5543 5435 opn = "mfhc1";
5544 5436 break;
5545 5437 case OPC_MTHC1:
5546   - GEN_LOAD_REG_T0(rt);
  5438 + gen_load_gpr(cpu_T[0], rt);
5547 5439 gen_op_mthc1();
5548 5440 GEN_STORE_FTN_FREG(fs, WTH0);
5549 5441 opn = "mthc1";
... ... @@ -5560,8 +5452,8 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
5560 5452 {
5561 5453 uint32_t ccbit;
5562 5454  
5563   - GEN_LOAD_REG_T0(rd);
5564   - GEN_LOAD_REG_T1(rs);
  5455 + gen_load_gpr(cpu_T[0], rd);
  5456 + gen_load_gpr(cpu_T[1], rs);
5565 5457 if (cc) {
5566 5458 ccbit = 1 << (24 + cc);
5567 5459 } else
... ... @@ -5570,7 +5462,7 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
5570 5462 gen_op_movf(ccbit);
5571 5463 else
5572 5464 gen_op_movt(ccbit);
5573   - GEN_STORE_T0_REG(rd);
  5465 + gen_store_gpr(cpu_T[0], rd);
5574 5466 }
5575 5467  
5576 5468 #define GEN_MOVCF(fmt) \
... ... @@ -5745,7 +5637,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5745 5637 opn = "floor.w.s";
5746 5638 break;
5747 5639 case FOP(17, 16):
5748   - GEN_LOAD_REG_T0(ft);
  5640 + gen_load_gpr(cpu_T[0], ft);
5749 5641 GEN_LOAD_FREG_FTN(WT0, fs);
5750 5642 GEN_LOAD_FREG_FTN(WT2, fd);
5751 5643 gen_movcf_s(ctx, (ft >> 2) & 0x7, ft & 0x1);
... ... @@ -5753,7 +5645,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5753 5645 opn = "movcf.s";
5754 5646 break;
5755 5647 case FOP(18, 16):
5756   - GEN_LOAD_REG_T0(ft);
  5648 + gen_load_gpr(cpu_T[0], ft);
5757 5649 GEN_LOAD_FREG_FTN(WT0, fs);
5758 5650 GEN_LOAD_FREG_FTN(WT2, fd);
5759 5651 gen_op_float_movz_s();
... ... @@ -5761,7 +5653,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5761 5653 opn = "movz.s";
5762 5654 break;
5763 5655 case FOP(19, 16):
5764   - GEN_LOAD_REG_T0(ft);
  5656 + gen_load_gpr(cpu_T[0], ft);
5765 5657 GEN_LOAD_FREG_FTN(WT0, fs);
5766 5658 GEN_LOAD_FREG_FTN(WT2, fd);
5767 5659 gen_op_float_movn_s();
... ... @@ -5988,7 +5880,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5988 5880 opn = "floor.w.d";
5989 5881 break;
5990 5882 case FOP(17, 17):
5991   - GEN_LOAD_REG_T0(ft);
  5883 + gen_load_gpr(cpu_T[0], ft);
5992 5884 GEN_LOAD_FREG_FTN(DT0, fs);
5993 5885 GEN_LOAD_FREG_FTN(DT2, fd);
5994 5886 gen_movcf_d(ctx, (ft >> 2) & 0x7, ft & 0x1);
... ... @@ -5996,7 +5888,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5996 5888 opn = "movcf.d";
5997 5889 break;
5998 5890 case FOP(18, 17):
5999   - GEN_LOAD_REG_T0(ft);
  5891 + gen_load_gpr(cpu_T[0], ft);
6000 5892 GEN_LOAD_FREG_FTN(DT0, fs);
6001 5893 GEN_LOAD_FREG_FTN(DT2, fd);
6002 5894 gen_op_float_movz_d();
... ... @@ -6004,7 +5896,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6004 5896 opn = "movz.d";
6005 5897 break;
6006 5898 case FOP(19, 17):
6007   - GEN_LOAD_REG_T0(ft);
  5899 + gen_load_gpr(cpu_T[0], ft);
6008 5900 GEN_LOAD_FREG_FTN(DT0, fs);
6009 5901 GEN_LOAD_FREG_FTN(DT2, fd);
6010 5902 gen_op_float_movn_d();
... ... @@ -6203,7 +6095,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6203 6095 break;
6204 6096 case FOP(17, 22):
6205 6097 check_cp1_64bitmode(ctx);
6206   - GEN_LOAD_REG_T0(ft);
  6098 + gen_load_gpr(cpu_T[0], ft);
6207 6099 GEN_LOAD_FREG_FTN(WT0, fs);
6208 6100 GEN_LOAD_FREG_FTN(WTH0, fs);
6209 6101 GEN_LOAD_FREG_FTN(WT2, fd);
... ... @@ -6215,7 +6107,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6215 6107 break;
6216 6108 case FOP(18, 22):
6217 6109 check_cp1_64bitmode(ctx);
6218   - GEN_LOAD_REG_T0(ft);
  6110 + gen_load_gpr(cpu_T[0], ft);
6219 6111 GEN_LOAD_FREG_FTN(WT0, fs);
6220 6112 GEN_LOAD_FREG_FTN(WTH0, fs);
6221 6113 GEN_LOAD_FREG_FTN(WT2, fd);
... ... @@ -6227,7 +6119,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6227 6119 break;
6228 6120 case FOP(19, 22):
6229 6121 check_cp1_64bitmode(ctx);
6230   - GEN_LOAD_REG_T0(ft);
  6122 + gen_load_gpr(cpu_T[0], ft);
6231 6123 GEN_LOAD_FREG_FTN(WT0, fs);
6232 6124 GEN_LOAD_FREG_FTN(WTH0, fs);
6233 6125 GEN_LOAD_FREG_FTN(WT2, fd);
... ... @@ -6409,15 +6301,12 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
6409 6301 int store = 0;
6410 6302  
6411 6303 if (base == 0) {
6412   - if (index == 0)
6413   - gen_op_reset_T0();
6414   - else
6415   - GEN_LOAD_REG_T0(index);
  6304 + gen_load_gpr(cpu_T[0], index);
6416 6305 } else if (index == 0) {
6417   - GEN_LOAD_REG_T0(base);
  6306 + gen_load_gpr(cpu_T[0], base);
6418 6307 } else {
6419   - GEN_LOAD_REG_T0(base);
6420   - GEN_LOAD_REG_T1(index);
  6308 + gen_load_gpr(cpu_T[0], base);
  6309 + gen_load_gpr(cpu_T[1], index);
6421 6310 gen_op_addr_add();
6422 6311 }
6423 6312 /* Don't do NOP if destination is zero: we must perform the actual
... ... @@ -6481,7 +6370,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
6481 6370 switch (opc) {
6482 6371 case OPC_ALNV_PS:
6483 6372 check_cp1_64bitmode(ctx);
6484   - GEN_LOAD_REG_T0(fr);
  6373 + gen_load_gpr(cpu_T[0], fr);
6485 6374 GEN_LOAD_FREG_FTN(DT0, fs);
6486 6375 GEN_LOAD_FREG_FTN(DT1, ft);
6487 6376 gen_op_float_alnv_ps();
... ... @@ -6649,12 +6538,14 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6649 6538 return;
6650 6539 }
6651 6540  
  6541 + /* Handle blikely not taken case */
6652 6542 if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
6653   - int l1;
6654   - /* Handle blikely not taken case */
  6543 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
  6544 + int l1 = gen_new_label();
  6545 +
6655 6546 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
6656   - l1 = gen_new_label();
6657   - tcg_gen_jnz_bcond(l1);
  6547 + tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
  6548 + tcg_gen_brcond_tl(TCG_COND_NE, r_tmp, tcg_const_tl(0), l1);
6658 6549 gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
6659 6550 gen_goto_tb(ctx, 1, ctx->pc + 4);
6660 6551 gen_set_label(l1);
... ... @@ -6826,15 +6717,15 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6826 6717 op2 = MASK_BSHFL(ctx->opcode);
6827 6718 switch (op2) {
6828 6719 case OPC_WSBH:
6829   - GEN_LOAD_REG_T1(rt);
  6720 + gen_load_gpr(cpu_T[1], rt);
6830 6721 gen_op_wsbh();
6831 6722 break;
6832 6723 case OPC_SEB:
6833   - GEN_LOAD_REG_T1(rt);
  6724 + gen_load_gpr(cpu_T[1], rt);
6834 6725 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[1]);
6835 6726 break;
6836 6727 case OPC_SEH:
6837   - GEN_LOAD_REG_T1(rt);
  6728 + gen_load_gpr(cpu_T[1], rt);
6838 6729 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[1]);
6839 6730 break;
6840 6731 default: /* Invalid */
... ... @@ -6842,7 +6733,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6842 6733 generate_exception(ctx, EXCP_RI);
6843 6734 break;
6844 6735 }
6845   - GEN_STORE_T0_REG(rd);
  6736 + gen_store_gpr(cpu_T[0], rd);
6846 6737 break;
6847 6738 case OPC_RDHWR:
6848 6739 check_insn(env, ctx, ISA_MIPS32R2);
... ... @@ -6873,19 +6764,19 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6873 6764 generate_exception(ctx, EXCP_RI);
6874 6765 break;
6875 6766 }
6876   - GEN_STORE_T0_REG(rt);
  6767 + gen_store_gpr(cpu_T[0], rt);
6877 6768 break;
6878 6769 case OPC_FORK:
6879 6770 check_insn(env, ctx, ASE_MT);
6880   - GEN_LOAD_REG_T0(rt);
6881   - GEN_LOAD_REG_T1(rs);
  6771 + gen_load_gpr(cpu_T[0], rt);
  6772 + gen_load_gpr(cpu_T[1], rs);
6882 6773 gen_op_fork();
6883 6774 break;
6884 6775 case OPC_YIELD:
6885 6776 check_insn(env, ctx, ASE_MT);
6886   - GEN_LOAD_REG_T0(rs);
  6777 + gen_load_gpr(cpu_T[0], rs);
6887 6778 gen_op_yield();
6888   - GEN_STORE_T0_REG(rd);
  6779 + gen_store_gpr(cpu_T[0], rd);
6889 6780 break;
6890 6781 #if defined(TARGET_MIPS64)
6891 6782 case OPC_DEXTM ... OPC_DEXT:
... ... @@ -6900,11 +6791,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6900 6791 op2 = MASK_DBSHFL(ctx->opcode);
6901 6792 switch (op2) {
6902 6793 case OPC_DSBH:
6903   - GEN_LOAD_REG_T1(rt);
  6794 + gen_load_gpr(cpu_T[1], rt);
6904 6795 gen_op_dsbh();
6905 6796 break;
6906 6797 case OPC_DSHD:
6907   - GEN_LOAD_REG_T1(rt);
  6798 + gen_load_gpr(cpu_T[1], rt);
6908 6799 gen_op_dshd();
6909 6800 break;
6910 6801 default: /* Invalid */
... ... @@ -6912,7 +6803,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6912 6803 generate_exception(ctx, EXCP_RI);
6913 6804 break;
6914 6805 }
6915   - GEN_STORE_T0_REG(rd);
  6806 + gen_store_gpr(cpu_T[0], rd);
6916 6807 break;
6917 6808 #endif
6918 6809 default: /* Invalid */
... ... @@ -6997,17 +6888,17 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6997 6888 generate_exception(ctx, EXCP_RI);
6998 6889 break;
6999 6890 }
7000   - GEN_STORE_T0_REG(rt);
  6891 + gen_store_gpr(cpu_T[0], rt);
7001 6892 break;
7002 6893 case OPC_RDPGPR:
7003 6894 check_insn(env, ctx, ISA_MIPS32R2);
7004   - GEN_LOAD_SRSREG_TN(T0, rt);
7005   - GEN_STORE_T0_REG(rd);
  6895 + gen_load_srsgpr(cpu_T[0], rt);
  6896 + gen_store_gpr(cpu_T[0], rd);
7006 6897 break;
7007 6898 case OPC_WRPGPR:
7008 6899 check_insn(env, ctx, ISA_MIPS32R2);
7009   - GEN_LOAD_REG_T0(rt);
7010   - GEN_STORE_TN_SRSREG(rd, T0);
  6900 + gen_load_gpr(cpu_T[0], rt);
  6901 + gen_store_srsgpr(cpu_T[0], rd);
7011 6902 break;
7012 6903 default:
7013 6904 MIPS_INVAL("cp0");
... ... @@ -7208,18 +7099,20 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7208 7099 /* Conditional branch */
7209 7100 MIPS_DEBUG("conditional branch");
7210 7101 {
7211   - int l1;
7212   - l1 = gen_new_label();
7213   - tcg_gen_jnz_bcond(l1);
7214   - gen_goto_tb(ctx, 1, ctx->pc + 4);
7215   - gen_set_label(l1);
7216   - gen_goto_tb(ctx, 0, ctx->btarget);
  7102 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
  7103 + int l1 = gen_new_label();
  7104 +
  7105 + tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
  7106 + tcg_gen_brcond_tl(TCG_COND_NE, r_tmp, tcg_const_tl(0), l1);
  7107 + gen_goto_tb(ctx, 1, ctx->pc + 4);
  7108 + gen_set_label(l1);
  7109 + gen_goto_tb(ctx, 0, ctx->btarget);
7217 7110 }
7218 7111 break;
7219 7112 case MIPS_HFLAG_BR:
7220 7113 /* unconditional branch to register */
7221 7114 MIPS_DEBUG("branch to register");
7222   - gen_op_breg();
  7115 + gen_breg_pc();
7223 7116 tcg_gen_exit_tb(0);
7224 7117 break;
7225 7118 default:
... ... @@ -7342,7 +7235,6 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
7342 7235 }
7343 7236 }
7344 7237 done_generating:
7345   - ctx.last_T0_store = NULL;
7346 7238 *gen_opc_ptr = INDEX_op_end;
7347 7239 if (search_pc) {
7348 7240 j = gen_opc_ptr - gen_opc_buf;
... ...