gwj / at91sam9263 · Commits

Commit 8e1c85e37277be8e0f1e273297a1dc19eb898a01

Authored by bellard
1 parent 5ecae2ba

converted conditional jumps, SET and CMOVx to TCG 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4518 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 421 additions and 840 deletions
target-i386/op.c deleted 100644 → 0
  View file @5ecae2b
1 -/*  
2 - * i386 micro operations  
3 - *  
4 - * Copyright (c) 2003 Fabrice Bellard  
5 - *  
6 - * This library is free software; you can redistribute it and/or  
7 - * modify it under the terms of the GNU Lesser General Public  
8 - * License as published by the Free Software Foundation; either  
9 - * version 2 of the License, or (at your option) any later version.  
10 - *  
11 - * This library is distributed in the hope that it will be useful,  
12 - * but WITHOUT ANY WARRANTY; without even the implied warranty of  
13 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU  
14 - * Lesser General Public License for more details.  
15 - *  
16 - * You should have received a copy of the GNU Lesser General Public  
17 - * License along with this library; if not, write to the Free Software  
18 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  
19 - */  
20 -  
21 -#define ASM_SOFTMMU  
22 -#include "exec.h"  
23 -  
24 -/* we define the various pieces of code used by the JIT */  
25 -  
26 -#define REG EAX  
27 -#define REGNAME _EAX  
28 -#include "opreg_template.h"  
29 -#undef REG  
30 -#undef REGNAME  
31 -  
32 -#define REG ECX  
33 -#define REGNAME _ECX  
34 -#include "opreg_template.h"  
35 -#undef REG  
36 -#undef REGNAME  
37 -  
38 -#define REG EDX  
39 -#define REGNAME _EDX  
40 -#include "opreg_template.h"  
41 -#undef REG  
42 -#undef REGNAME  
43 -  
44 -#define REG EBX  
45 -#define REGNAME _EBX  
46 -#include "opreg_template.h"  
47 -#undef REG  
48 -#undef REGNAME  
49 -  
50 -#define REG ESP  
51 -#define REGNAME _ESP  
52 -#include "opreg_template.h"  
53 -#undef REG  
54 -#undef REGNAME  
55 -  
56 -#define REG EBP  
57 -#define REGNAME _EBP  
58 -#include "opreg_template.h"  
59 -#undef REG  
60 -#undef REGNAME  
61 -  
62 -#define REG ESI  
63 -#define REGNAME _ESI  
64 -#include "opreg_template.h"  
65 -#undef REG  
66 -#undef REGNAME  
67 -  
68 -#define REG EDI  
69 -#define REGNAME _EDI  
70 -#include "opreg_template.h"  
71 -#undef REG  
72 -#undef REGNAME  
73 -  
74 -#ifdef TARGET_X86_64  
75 -  
76 -#define REG (env->regs[8])  
77 -#define REGNAME _R8  
78 -#include "opreg_template.h"  
79 -#undef REG  
80 -#undef REGNAME  
81 -  
82 -#define REG (env->regs[9])  
83 -#define REGNAME _R9  
84 -#include "opreg_template.h"  
85 -#undef REG  
86 -#undef REGNAME  
87 -  
88 -#define REG (env->regs[10])  
89 -#define REGNAME _R10  
90 -#include "opreg_template.h"  
91 -#undef REG  
92 -#undef REGNAME  
93 -  
94 -#define REG (env->regs[11])  
95 -#define REGNAME _R11  
96 -#include "opreg_template.h"  
97 -#undef REG  
98 -#undef REGNAME  
99 -  
100 -#define REG (env->regs[12])  
101 -#define REGNAME _R12  
102 -#include "opreg_template.h"  
103 -#undef REG  
104 -#undef REGNAME  
105 -  
106 -#define REG (env->regs[13])  
107 -#define REGNAME _R13  
108 -#include "opreg_template.h"  
109 -#undef REG  
110 -#undef REGNAME  
111 -  
112 -#define REG (env->regs[14])  
113 -#define REGNAME _R14  
114 -#include "opreg_template.h"  
115 -#undef REG  
116 -#undef REGNAME  
117 -  
118 -#define REG (env->regs[15])  
119 -#define REGNAME _R15  
120 -#include "opreg_template.h"  
121 -#undef REG  
122 -#undef REGNAME  
123 -  
124 -#endif  
125 -  
126 -/* multiple size ops */  
127 -  
128 -#define ldul ldl  
129 -  
130 -#define SHIFT 0  
131 -#include "ops_template.h"  
132 -#undef SHIFT  
133 -  
134 -#define SHIFT 1  
135 -#include "ops_template.h"  
136 -#undef SHIFT  
137 -  
138 -#define SHIFT 2  
139 -#include "ops_template.h"  
140 -#undef SHIFT  
141 -  
142 -#ifdef TARGET_X86_64  
143 -  
144 -#define SHIFT 3  
145 -#include "ops_template.h"  
146 -#undef SHIFT  
147 -  
148 -#endif  
149 -  
150 -/* flags handling */  
151 -  
152 -void OPPROTO op_jmp_label(void)  
153 -{  
154 - GOTO_LABEL_PARAM(1);  
155 -}  
156 -  
157 -void OPPROTO op_jnz_T0_label(void)  
158 -{  
159 - if (T0)  
160 - GOTO_LABEL_PARAM(1);  
161 - FORCE_RET();  
162 -}  
163 -  
164 -/* slow set cases (compute x86 flags) */  
165 -void OPPROTO op_seto_T0_cc(void)  
166 -{  
167 - int eflags;  
168 - eflags = cc_table[CC_OP].compute_all();  
169 - T0 = (eflags >> 11) & 1;  
170 -}  
171 -  
172 -void OPPROTO op_setb_T0_cc(void)  
173 -{  
174 - T0 = cc_table[CC_OP].compute_c();  
175 -}  
176 -  
177 -void OPPROTO op_setz_T0_cc(void)  
178 -{  
179 - int eflags;  
180 - eflags = cc_table[CC_OP].compute_all();  
181 - T0 = (eflags >> 6) & 1;  
182 -}  
183 -  
184 -void OPPROTO op_setbe_T0_cc(void)  
185 -{  
186 - int eflags;  
187 - eflags = cc_table[CC_OP].compute_all();  
188 - T0 = (eflags & (CC_Z | CC_C)) != 0;  
189 -}  
190 -  
191 -void OPPROTO op_sets_T0_cc(void)  
192 -{  
193 - int eflags;  
194 - eflags = cc_table[CC_OP].compute_all();  
195 - T0 = (eflags >> 7) & 1;  
196 -}  
197 -  
198 -void OPPROTO op_setp_T0_cc(void)  
199 -{  
200 - int eflags;  
201 - eflags = cc_table[CC_OP].compute_all();  
202 - T0 = (eflags >> 2) & 1;  
203 -}  
204 -  
205 -void OPPROTO op_setl_T0_cc(void)  
206 -{  
207 - int eflags;  
208 - eflags = cc_table[CC_OP].compute_all();  
209 - T0 = ((eflags ^ (eflags >> 4)) >> 7) & 1;  
210 -}  
211 -  
212 -void OPPROTO op_setle_T0_cc(void)  
213 -{  
214 - int eflags;  
215 - eflags = cc_table[CC_OP].compute_all();  
216 - T0 = (((eflags ^ (eflags >> 4)) & 0x80) || (eflags & CC_Z)) != 0;  
217 -}  
218 -  
219 -void OPPROTO op_xor_T0_1(void)  
220 -{  
221 - T0 ^= 1;  
222 -}  
target-i386/opreg_template.h deleted 100644 → 0
  View file @5ecae2b
1 -/*  
2 - * i386 micro operations (templates for various register related  
3 - * operations)  
4 - *  
5 - * Copyright (c) 2003 Fabrice Bellard  
6 - *  
7 - * This library is free software; you can redistribute it and/or  
8 - * modify it under the terms of the GNU Lesser General Public  
9 - * License as published by the Free Software Foundation; either  
10 - * version 2 of the License, or (at your option) any later version.  
11 - *  
12 - * This library is distributed in the hope that it will be useful,  
13 - * but WITHOUT ANY WARRANTY; without even the implied warranty of  
14 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU  
15 - * Lesser General Public License for more details.  
16 - *  
17 - * You should have received a copy of the GNU Lesser General Public  
18 - * License along with this library; if not, write to the Free Software  
19 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  
20 - */  
21 -/* mov T1 to REG if T0 is true */  
22 -void OPPROTO glue(glue(op_cmovw,REGNAME),_T1_T0)(void)  
23 -{  
24 - if (T0)  
25 - REG = (REG & ~0xffff) | (T1 & 0xffff);  
26 - FORCE_RET();  
27 -}  
28 -  
29 -void OPPROTO glue(glue(op_cmovl,REGNAME),_T1_T0)(void)  
30 -{  
31 -#ifdef TARGET_X86_64  
32 - if (T0)  
33 - REG = (uint32_t)T1;  
34 - else  
35 - REG = (uint32_t)REG;  
36 -#else  
37 - if (T0)  
38 - REG = (uint32_t)T1;  
39 -#endif  
40 - FORCE_RET();  
41 -}  
42 -  
43 -#ifdef TARGET_X86_64  
44 -void OPPROTO glue(glue(op_cmovq,REGNAME),_T1_T0)(void)  
45 -{  
46 - if (T0)  
47 - REG = T1;  
48 - FORCE_RET();  
49 -}  
50 -#endif  
target-i386/ops_template.h deleted 100644 → 0
  View file @5ecae2b
1 -/*  
2 - * i386 micro operations (included several times to generate  
3 - * different operand sizes)  
4 - *  
5 - * Copyright (c) 2003 Fabrice Bellard  
6 - *  
7 - * This library is free software; you can redistribute it and/or  
8 - * modify it under the terms of the GNU Lesser General Public  
9 - * License as published by the Free Software Foundation; either  
10 - * version 2 of the License, or (at your option) any later version.  
11 - *  
12 - * This library is distributed in the hope that it will be useful,  
13 - * but WITHOUT ANY WARRANTY; without even the implied warranty of  
14 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU  
15 - * Lesser General Public License for more details.  
16 - *  
17 - * You should have received a copy of the GNU Lesser General Public  
18 - * License along with this library; if not, write to the Free Software  
19 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  
20 - */  
21 -#define DATA_BITS (1 << (3 + SHIFT))  
22 -#define SHIFT_MASK (DATA_BITS - 1)  
23 -#define SIGN_MASK (((target_ulong)1) << (DATA_BITS - 1))  
24 -#if DATA_BITS <= 32  
25 -#define SHIFT1_MASK 0x1f  
26 -#else  
27 -#define SHIFT1_MASK 0x3f  
28 -#endif  
29 -  
30 -#if DATA_BITS == 8  
31 -#define SUFFIX b  
32 -#define DATA_TYPE uint8_t  
33 -#define DATA_STYPE int8_t  
34 -#define DATA_MASK 0xff  
35 -#elif DATA_BITS == 16  
36 -#define SUFFIX w  
37 -#define DATA_TYPE uint16_t  
38 -#define DATA_STYPE int16_t  
39 -#define DATA_MASK 0xffff  
40 -#elif DATA_BITS == 32  
41 -#define SUFFIX l  
42 -#define DATA_TYPE uint32_t  
43 -#define DATA_STYPE int32_t  
44 -#define DATA_MASK 0xffffffff  
45 -#elif DATA_BITS == 64  
46 -#define SUFFIX q  
47 -#define DATA_TYPE uint64_t  
48 -#define DATA_STYPE int64_t  
49 -#define DATA_MASK 0xffffffffffffffffULL  
50 -#else  
51 -#error unhandled operand size  
52 -#endif  
53 -  
54 -/* various optimized jumps cases */  
55 -  
56 -void OPPROTO glue(op_jb_sub, SUFFIX)(void)  
57 -{  
58 - target_long src1, src2;  
59 - src1 = CC_DST + CC_SRC;  
60 - src2 = CC_SRC;  
61 -  
62 - if ((DATA_TYPE)src1 < (DATA_TYPE)src2)  
63 - GOTO_LABEL_PARAM(1);  
64 - FORCE_RET();  
65 -}  
66 -  
67 -void OPPROTO glue(op_jz_sub, SUFFIX)(void)  
68 -{  
69 - if ((DATA_TYPE)CC_DST == 0)  
70 - GOTO_LABEL_PARAM(1);  
71 - FORCE_RET();  
72 -}  
73 -  
74 -void OPPROTO glue(op_jnz_sub, SUFFIX)(void)  
75 -{  
76 - if ((DATA_TYPE)CC_DST != 0)  
77 - GOTO_LABEL_PARAM(1);  
78 - FORCE_RET();  
79 -}  
80 -  
81 -void OPPROTO glue(op_jbe_sub, SUFFIX)(void)  
82 -{  
83 - target_long src1, src2;  
84 - src1 = CC_DST + CC_SRC;  
85 - src2 = CC_SRC;  
86 -  
87 - if ((DATA_TYPE)src1 <= (DATA_TYPE)src2)  
88 - GOTO_LABEL_PARAM(1);  
89 - FORCE_RET();  
90 -}  
91 -  
92 -void OPPROTO glue(op_js_sub, SUFFIX)(void)  
93 -{  
94 - if (CC_DST & SIGN_MASK)  
95 - GOTO_LABEL_PARAM(1);  
96 - FORCE_RET();  
97 -}  
98 -  
99 -void OPPROTO glue(op_jl_sub, SUFFIX)(void)  
100 -{  
101 - target_long src1, src2;  
102 - src1 = CC_DST + CC_SRC;  
103 - src2 = CC_SRC;  
104 -  
105 - if ((DATA_STYPE)src1 < (DATA_STYPE)src2)  
106 - GOTO_LABEL_PARAM(1);  
107 - FORCE_RET();  
108 -}  
109 -  
110 -void OPPROTO glue(op_jle_sub, SUFFIX)(void)  
111 -{  
112 - target_long src1, src2;  
113 - src1 = CC_DST + CC_SRC;  
114 - src2 = CC_SRC;  
115 -  
116 - if ((DATA_STYPE)src1 <= (DATA_STYPE)src2)  
117 - GOTO_LABEL_PARAM(1);  
118 - FORCE_RET();  
119 -}  
120 -  
121 -/* various optimized set cases */  
122 -  
123 -void OPPROTO glue(op_setb_T0_sub, SUFFIX)(void)  
124 -{  
125 - target_long src1, src2;  
126 - src1 = CC_DST + CC_SRC;  
127 - src2 = CC_SRC;  
128 -  
129 - T0 = ((DATA_TYPE)src1 < (DATA_TYPE)src2);  
130 -}  
131 -  
132 -void OPPROTO glue(op_setz_T0_sub, SUFFIX)(void)  
133 -{  
134 - T0 = ((DATA_TYPE)CC_DST == 0);  
135 -}  
136 -  
137 -void OPPROTO glue(op_setbe_T0_sub, SUFFIX)(void)  
138 -{  
139 - target_long src1, src2;  
140 - src1 = CC_DST + CC_SRC;  
141 - src2 = CC_SRC;  
142 -  
143 - T0 = ((DATA_TYPE)src1 <= (DATA_TYPE)src2);  
144 -}  
145 -  
146 -void OPPROTO glue(op_sets_T0_sub, SUFFIX)(void)  
147 -{  
148 - T0 = lshift(CC_DST, -(DATA_BITS - 1)) & 1;  
149 -}  
150 -  
151 -void OPPROTO glue(op_setl_T0_sub, SUFFIX)(void)  
152 -{  
153 - target_long src1, src2;  
154 - src1 = CC_DST + CC_SRC;  
155 - src2 = CC_SRC;  
156 -  
157 - T0 = ((DATA_STYPE)src1 < (DATA_STYPE)src2);  
158 -}  
159 -  
160 -void OPPROTO glue(op_setle_T0_sub, SUFFIX)(void)  
161 -{  
162 - target_long src1, src2;  
163 - src1 = CC_DST + CC_SRC;  
164 - src2 = CC_SRC;  
165 -  
166 - T0 = ((DATA_STYPE)src1 <= (DATA_STYPE)src2);  
167 -}  
168 -  
169 -#undef DATA_BITS  
170 -#undef SHIFT_MASK  
171 -#undef SHIFT1_MASK  
172 -#undef SIGN_MASK  
173 -#undef DATA_TYPE  
174 -#undef DATA_STYPE  
175 -#undef DATA_MASK  
176 -#undef SUFFIX  
target-i386/translate.c
  View file @8e1c85e
@@ -133,6 +133,17 @@ enum { @@ -133,6 +133,17 @@ enum {
133 OP_SAR = 7, 133 OP_SAR = 7,
134 }; 134 };
135 135
  136 +enum {
  137 + JCC_O,
  138 + JCC_B,
  139 + JCC_Z,
  140 + JCC_BE,
  141 + JCC_S,
  142 + JCC_P,
  143 + JCC_L,
  144 + JCC_LE,
  145 +};
  146 +
136 /* operand size */ 147 /* operand size */
137 enum { 148 enum {
138 OT_BYTE = 0, 149 OT_BYTE = 0,
@@ -228,38 +239,10 @@ static inline void gen_op_andl_A0_ffff(void) @@ -228,38 +239,10 @@ static inline void gen_op_andl_A0_ffff(void)
228 239
229 #define NB_OP_SIZES 4 240 #define NB_OP_SIZES 4
230 241
231 -#define DEF_REGS(prefix, suffix) \  
232 - prefix ## EAX ## suffix,\  
233 - prefix ## ECX ## suffix,\  
234 - prefix ## EDX ## suffix,\  
235 - prefix ## EBX ## suffix,\  
236 - prefix ## ESP ## suffix,\  
237 - prefix ## EBP ## suffix,\  
238 - prefix ## ESI ## suffix,\  
239 - prefix ## EDI ## suffix,\  
240 - prefix ## R8 ## suffix,\  
241 - prefix ## R9 ## suffix,\  
242 - prefix ## R10 ## suffix,\  
243 - prefix ## R11 ## suffix,\  
244 - prefix ## R12 ## suffix,\  
245 - prefix ## R13 ## suffix,\  
246 - prefix ## R14 ## suffix,\  
247 - prefix ## R15 ## suffix,  
248 -  
249 #else /* !TARGET_X86_64 */ 242 #else /* !TARGET_X86_64 */
250 243
251 #define NB_OP_SIZES 3 244 #define NB_OP_SIZES 3
252 245
253 -#define DEF_REGS(prefix, suffix) \  
254 - prefix ## EAX ## suffix,\  
255 - prefix ## ECX ## suffix,\  
256 - prefix ## EDX ## suffix,\  
257 - prefix ## EBX ## suffix,\  
258 - prefix ## ESP ## suffix,\  
259 - prefix ## EBP ## suffix,\  
260 - prefix ## ESI ## suffix,\  
261 - prefix ## EDI ## suffix,  
262 -  
263 #endif /* !TARGET_X86_64 */ 246 #endif /* !TARGET_X86_64 */
264 247
265 #if defined(WORDS_BIGENDIAN) 248 #if defined(WORDS_BIGENDIAN)
@@ -510,20 +493,6 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg) @@ -510,20 +493,6 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
510 } 493 }
511 #endif 494 #endif
512 495
513 -static GenOpFunc *gen_op_cmov_reg_T1_T0[NB_OP_SIZES - 1][CPU_NB_REGS] = {  
514 - [0] = {  
515 - DEF_REGS(gen_op_cmovw_, _T1_T0)  
516 - },  
517 - [1] = {  
518 - DEF_REGS(gen_op_cmovl_, _T1_T0)  
519 - },  
520 -#ifdef TARGET_X86_64  
521 - [2] = {  
522 - DEF_REGS(gen_op_cmovq_, _T1_T0)  
523 - },  
524 -#endif  
525 -};  
526 -  
527 static inline void gen_op_lds_T0_A0(int idx) 496 static inline void gen_op_lds_T0_A0(int idx)
528 { 497 {
529 int mem_index = (idx >> 2) - 1; 498 int mem_index = (idx >> 2) - 1;
@@ -743,21 +712,6 @@ static inline void gen_op_jz_ecx(int size, int label1) @@ -743,21 +712,6 @@ static inline void gen_op_jz_ecx(int size, int label1)
743 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), label1); 712 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), label1);
744 } 713 }
745 714
746 -static GenOpFunc1 *gen_op_string_jnz_sub[2][4] = {  
747 - {  
748 - gen_op_jnz_subb,  
749 - gen_op_jnz_subw,  
750 - gen_op_jnz_subl,  
751 - X86_64_ONLY(gen_op_jnz_subq),  
752 - },  
753 - {  
754 - gen_op_jz_subb,  
755 - gen_op_jz_subw,  
756 - gen_op_jz_subl,  
757 - X86_64_ONLY(gen_op_jz_subq),  
758 - },  
759 -};  
760 -  
761 static void *helper_in_func[3] = { 715 static void *helper_in_func[3] = {
762 helper_inb, 716 helper_inb,
763 helper_inw, 717 helper_inw,
@@ -858,6 +812,352 @@ static void gen_op_update_neg_cc(void) @@ -858,6 +812,352 @@ static void gen_op_update_neg_cc(void)
858 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); 812 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
859 } 813 }
860 814
  815 +/* compute eflags.C to reg */
  816 +static void gen_compute_eflags_c(TCGv reg)
  817 +{
  818 +#if TCG_TARGET_REG_BITS == 32
  819 + tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
  820 + tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
  821 + (long)cc_table + offsetof(CCTable, compute_c));
  822 + tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
  823 + tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
  824 + 1, &cpu_tmp2_i32, 0, NULL);
  825 +#else
  826 + tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
  827 + tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
  828 + tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
  829 + (long)cc_table + offsetof(CCTable, compute_c));
  830 + tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
  831 + tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
  832 + 1, &cpu_tmp2_i32, 0, NULL);
  833 +#endif
  834 + tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
  835 +}
  836 +
  837 +/* compute all eflags to cc_src */
  838 +static void gen_compute_eflags(TCGv reg)
  839 +{
  840 +#if TCG_TARGET_REG_BITS == 32
  841 + tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
  842 + tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
  843 + (long)cc_table + offsetof(CCTable, compute_all));
  844 + tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
  845 + tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
  846 + 1, &cpu_tmp2_i32, 0, NULL);
  847 +#else
  848 + tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
  849 + tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
  850 + tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
  851 + (long)cc_table + offsetof(CCTable, compute_all));
  852 + tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
  853 + tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
  854 + 1, &cpu_tmp2_i32, 0, NULL);
  855 +#endif
  856 + tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
  857 +}
  858 +
  859 +static inline void gen_setcc_slow_T0(int op)
  860 +{
  861 + switch(op) {
  862 + case JCC_O:
  863 + gen_compute_eflags(cpu_T[0]);
  864 + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
  865 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
  866 + break;
  867 + case JCC_B:
  868 + gen_compute_eflags_c(cpu_T[0]);
  869 + break;
  870 + case JCC_Z:
  871 + gen_compute_eflags(cpu_T[0]);
  872 + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
  873 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
  874 + break;
  875 + case JCC_BE:
  876 + gen_compute_eflags(cpu_tmp0);
  877 + tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
  878 + tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
  879 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
  880 + break;
  881 + case JCC_S:
  882 + gen_compute_eflags(cpu_T[0]);
  883 + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
  884 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
  885 + break;
  886 + case JCC_P:
  887 + gen_compute_eflags(cpu_T[0]);
  888 + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
  889 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
  890 + break;
  891 + case JCC_L:
  892 + gen_compute_eflags(cpu_tmp0);
  893 + tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
  894 + tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
  895 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
  896 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
  897 + break;
  898 + default:
  899 + case JCC_LE:
  900 + gen_compute_eflags(cpu_tmp0);
  901 + tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
  902 + tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
  903 + tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
  904 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
  905 + tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
  906 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
  907 + break;
  908 + }
  909 +}
  910 +
  911 +/* return true if setcc_slow is not needed (WARNING: must be kept in
  912 + sync with gen_jcc1) */
  913 +static int is_fast_jcc_case(DisasContext *s, int b)
  914 +{
  915 + int jcc_op;
  916 + jcc_op = (b >> 1) & 7;
  917 + switch(s->cc_op) {
  918 + /* we optimize the cmp/jcc case */
  919 + case CC_OP_SUBB:
  920 + case CC_OP_SUBW:
  921 + case CC_OP_SUBL:
  922 + case CC_OP_SUBQ:
  923 + if (jcc_op == JCC_O || jcc_op == JCC_P)
  924 + goto slow_jcc;
  925 + break;
  926 +
  927 + /* some jumps are easy to compute */
  928 + case CC_OP_ADDB:
  929 + case CC_OP_ADDW:
  930 + case CC_OP_ADDL:
  931 + case CC_OP_ADDQ:
  932 +
  933 + case CC_OP_LOGICB:
  934 + case CC_OP_LOGICW:
  935 + case CC_OP_LOGICL:
  936 + case CC_OP_LOGICQ:
  937 +
  938 + case CC_OP_INCB:
  939 + case CC_OP_INCW:
  940 + case CC_OP_INCL:
  941 + case CC_OP_INCQ:
  942 +
  943 + case CC_OP_DECB:
  944 + case CC_OP_DECW:
  945 + case CC_OP_DECL:
  946 + case CC_OP_DECQ:
  947 +
  948 + case CC_OP_SHLB:
  949 + case CC_OP_SHLW:
  950 + case CC_OP_SHLL:
  951 + case CC_OP_SHLQ:
  952 + if (jcc_op != JCC_Z && jcc_op != JCC_S)
  953 + goto slow_jcc;
  954 + break;
  955 + default:
  956 + slow_jcc:
  957 + return 0;
  958 + }
  959 + return 1;
  960 +}
  961 +
  962 +/* generate a conditional jump to label 'l1' according to jump opcode
  963 + value 'b'. In the fast case, T0 is guaranted not to be used. */
  964 +static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
  965 +{
  966 + int inv, jcc_op, size, cond;
  967 + TCGv t0;
  968 +
  969 + inv = b & 1;
  970 + jcc_op = (b >> 1) & 7;
  971 +
  972 + switch(cc_op) {
  973 + /* we optimize the cmp/jcc case */
  974 + case CC_OP_SUBB:
  975 + case CC_OP_SUBW:
  976 + case CC_OP_SUBL:
  977 + case CC_OP_SUBQ:
  978 +
  979 + size = cc_op - CC_OP_SUBB;
  980 + switch(jcc_op) {
  981 + case JCC_Z:
  982 + fast_jcc_z:
  983 + switch(size) {
  984 + case 0:
  985 + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
  986 + t0 = cpu_tmp0;
  987 + break;
  988 + case 1:
  989 + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
  990 + t0 = cpu_tmp0;
  991 + break;
  992 +#ifdef TARGET_X86_64
  993 + case 2:
  994 + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
  995 + t0 = cpu_tmp0;
  996 + break;
  997 +#endif
  998 + default:
  999 + t0 = cpu_cc_dst;
  1000 + break;
  1001 + }
  1002 + tcg_gen_brcond_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0,
  1003 + tcg_const_tl(0), l1);
  1004 + break;
  1005 + case JCC_S:
  1006 + fast_jcc_s:
  1007 + switch(size) {
  1008 + case 0:
  1009 + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
  1010 + tcg_gen_brcond_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
  1011 + tcg_const_tl(0), l1);
  1012 + break;
  1013 + case 1:
  1014 + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
  1015 + tcg_gen_brcond_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
  1016 + tcg_const_tl(0), l1);
  1017 + break;
  1018 +#ifdef TARGET_X86_64
  1019 + case 2:
  1020 + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
  1021 + tcg_gen_brcond_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
  1022 + tcg_const_tl(0), l1);
  1023 + break;
  1024 +#endif
  1025 + default:
  1026 + tcg_gen_brcond_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
  1027 + tcg_const_tl(0), l1);
  1028 + break;
  1029 + }
  1030 + break;
  1031 +
  1032 + case JCC_B:
  1033 + cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
  1034 + goto fast_jcc_b;
  1035 + case JCC_BE:
  1036 + cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
  1037 + fast_jcc_b:
  1038 + tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
  1039 + switch(size) {
  1040 + case 0:
  1041 + t0 = cpu_tmp0;
  1042 + tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
  1043 + tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
  1044 + break;
  1045 + case 1:
  1046 + t0 = cpu_tmp0;
  1047 + tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
  1048 + tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
  1049 + break;
  1050 +#ifdef TARGET_X86_64
  1051 + case 2:
  1052 + t0 = cpu_tmp0;
  1053 + tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
  1054 + tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
  1055 + break;
  1056 +#endif
  1057 + default:
  1058 + t0 = cpu_cc_src;
  1059 + break;
  1060 + }
  1061 + tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
  1062 + break;
  1063 +
  1064 + case JCC_L:
  1065 + cond = inv ? TCG_COND_GE : TCG_COND_LT;
  1066 + goto fast_jcc_l;
  1067 + case JCC_LE:
  1068 + cond = inv ? TCG_COND_GT : TCG_COND_LE;
  1069 + fast_jcc_l:
  1070 + tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
  1071 + switch(size) {
  1072 + case 0:
  1073 + t0 = cpu_tmp0;
  1074 + tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
  1075 + tcg_gen_ext8s_tl(t0, cpu_cc_src);
  1076 + break;
  1077 + case 1:
  1078 + t0 = cpu_tmp0;
  1079 + tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
  1080 + tcg_gen_ext16s_tl(t0, cpu_cc_src);
  1081 + break;
  1082 +#ifdef TARGET_X86_64
  1083 + case 2:
  1084 + t0 = cpu_tmp0;
  1085 + tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
  1086 + tcg_gen_ext32s_tl(t0, cpu_cc_src);
  1087 + break;
  1088 +#endif
  1089 + default:
  1090 + t0 = cpu_cc_src;
  1091 + break;
  1092 + }
  1093 + tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
  1094 + break;
  1095 +
  1096 + default:
  1097 + goto slow_jcc;
  1098 + }
  1099 + break;
  1100 +
  1101 + /* some jumps are easy to compute */
  1102 + case CC_OP_ADDB:
  1103 + case CC_OP_ADDW:
  1104 + case CC_OP_ADDL:
  1105 + case CC_OP_ADDQ:
  1106 +
  1107 + case CC_OP_ADCB:
  1108 + case CC_OP_ADCW:
  1109 + case CC_OP_ADCL:
  1110 + case CC_OP_ADCQ:
  1111 +
  1112 + case CC_OP_SBBB:
  1113 + case CC_OP_SBBW:
  1114 + case CC_OP_SBBL:
  1115 + case CC_OP_SBBQ:
  1116 +
  1117 + case CC_OP_LOGICB:
  1118 + case CC_OP_LOGICW:
  1119 + case CC_OP_LOGICL:
  1120 + case CC_OP_LOGICQ:
  1121 +
  1122 + case CC_OP_INCB:
  1123 + case CC_OP_INCW:
  1124 + case CC_OP_INCL:
  1125 + case CC_OP_INCQ:
  1126 +
  1127 + case CC_OP_DECB:
  1128 + case CC_OP_DECW:
  1129 + case CC_OP_DECL:
  1130 + case CC_OP_DECQ:
  1131 +
  1132 + case CC_OP_SHLB:
  1133 + case CC_OP_SHLW:
  1134 + case CC_OP_SHLL:
  1135 + case CC_OP_SHLQ:
  1136 +
  1137 + case CC_OP_SARB:
  1138 + case CC_OP_SARW:
  1139 + case CC_OP_SARL:
  1140 + case CC_OP_SARQ:
  1141 + switch(jcc_op) {
  1142 + case JCC_Z:
  1143 + size = (cc_op - CC_OP_ADDB) & 3;
  1144 + goto fast_jcc_z;
  1145 + case JCC_S:
  1146 + size = (cc_op - CC_OP_ADDB) & 3;
  1147 + goto fast_jcc_s;
  1148 + default:
  1149 + goto slow_jcc;
  1150 + }
  1151 + break;
  1152 + default:
  1153 + slow_jcc:
  1154 + gen_setcc_slow_T0(jcc_op);
  1155 + tcg_gen_brcond_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
  1156 + cpu_T[0], tcg_const_tl(0), l1);
  1157 + break;
  1158 + }
  1159 +}
  1160 +
861 /* XXX: does not work with gdbstub "ice" single step - not a 1161 /* XXX: does not work with gdbstub "ice" single step - not a
862 serious problem */ 1162 serious problem */
863 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) 1163 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
@@ -974,7 +1274,7 @@ static inline void gen_repz_ ## op(DisasContext *s, int ot, \ @@ -974,7 +1274,7 @@ static inline void gen_repz_ ## op(DisasContext *s, int ot, \
974 gen_ ## op(s, ot); \ 1274 gen_ ## op(s, ot); \
975 gen_op_add_reg_im(s->aflag, R_ECX, -1); \ 1275 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
976 gen_op_set_cc_op(CC_OP_SUBB + ot); \ 1276 gen_op_set_cc_op(CC_OP_SUBB + ot); \
977 - gen_op_string_jnz_sub[nz][ot](l2);\ 1277 + gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
978 if (!s->jmp_opt) \ 1278 if (!s->jmp_opt) \
979 gen_op_jz_ecx(s->aflag, l2); \ 1279 gen_op_jz_ecx(s->aflag, l2); \
980 gen_jmp(s, cur_eip); \ 1280 gen_jmp(s, cur_eip); \
@@ -988,118 +1288,6 @@ GEN_REPZ(outs) @@ -988,118 +1288,6 @@ GEN_REPZ(outs)
988 GEN_REPZ2(scas) 1288 GEN_REPZ2(scas)
989 GEN_REPZ2(cmps) 1289 GEN_REPZ2(cmps)
990 1290
991 -enum {  
992 - JCC_O,  
993 - JCC_B,  
994 - JCC_Z,  
995 - JCC_BE,  
996 - JCC_S,  
997 - JCC_P,  
998 - JCC_L,  
999 - JCC_LE,  
1000 -};  
1001 -  
1002 -static GenOpFunc1 *gen_jcc_sub[4][8] = {  
1003 - [OT_BYTE] = {  
1004 - NULL,  
1005 - gen_op_jb_subb,  
1006 - gen_op_jz_subb,  
1007 - gen_op_jbe_subb,  
1008 - gen_op_js_subb,  
1009 - NULL,  
1010 - gen_op_jl_subb,  
1011 - gen_op_jle_subb,  
1012 - },  
1013 - [OT_WORD] = {  
1014 - NULL,  
1015 - gen_op_jb_subw,  
1016 - gen_op_jz_subw,  
1017 - gen_op_jbe_subw,  
1018 - gen_op_js_subw,  
1019 - NULL,  
1020 - gen_op_jl_subw,  
1021 - gen_op_jle_subw,  
1022 - },  
1023 - [OT_LONG] = {  
1024 - NULL,  
1025 - gen_op_jb_subl,  
1026 - gen_op_jz_subl,  
1027 - gen_op_jbe_subl,  
1028 - gen_op_js_subl,  
1029 - NULL,  
1030 - gen_op_jl_subl,  
1031 - gen_op_jle_subl,  
1032 - },  
1033 -#ifdef TARGET_X86_64  
1034 - [OT_QUAD] = {  
1035 - NULL,  
1036 - BUGGY_64(gen_op_jb_subq),  
1037 - gen_op_jz_subq,  
1038 - BUGGY_64(gen_op_jbe_subq),  
1039 - gen_op_js_subq,  
1040 - NULL,  
1041 - BUGGY_64(gen_op_jl_subq),  
1042 - BUGGY_64(gen_op_jle_subq),  
1043 - },  
1044 -#endif  
1045 -};  
1046 -  
1047 -static GenOpFunc *gen_setcc_slow[8] = {  
1048 - gen_op_seto_T0_cc,  
1049 - gen_op_setb_T0_cc,  
1050 - gen_op_setz_T0_cc,  
1051 - gen_op_setbe_T0_cc,  
1052 - gen_op_sets_T0_cc,  
1053 - gen_op_setp_T0_cc,  
1054 - gen_op_setl_T0_cc,  
1055 - gen_op_setle_T0_cc,  
1056 -};  
1057 -  
1058 -static GenOpFunc *gen_setcc_sub[4][8] = {  
1059 - [OT_BYTE] = {  
1060 - NULL,  
1061 - gen_op_setb_T0_subb,  
1062 - gen_op_setz_T0_subb,  
1063 - gen_op_setbe_T0_subb,  
1064 - gen_op_sets_T0_subb,  
1065 - NULL,  
1066 - gen_op_setl_T0_subb,  
1067 - gen_op_setle_T0_subb,  
1068 - },  
1069 - [OT_WORD] = {  
1070 - NULL,  
1071 - gen_op_setb_T0_subw,  
1072 - gen_op_setz_T0_subw,  
1073 - gen_op_setbe_T0_subw,  
1074 - gen_op_sets_T0_subw,  
1075 - NULL,  
1076 - gen_op_setl_T0_subw,  
1077 - gen_op_setle_T0_subw,  
1078 - },  
1079 - [OT_LONG] = {  
1080 - NULL,  
1081 - gen_op_setb_T0_subl,  
1082 - gen_op_setz_T0_subl,  
1083 - gen_op_setbe_T0_subl,  
1084 - gen_op_sets_T0_subl,  
1085 - NULL,  
1086 - gen_op_setl_T0_subl,  
1087 - gen_op_setle_T0_subl,  
1088 - },  
1089 -#ifdef TARGET_X86_64  
1090 - [OT_QUAD] = {  
1091 - NULL,  
1092 - gen_op_setb_T0_subq,  
1093 - gen_op_setz_T0_subq,  
1094 - gen_op_setbe_T0_subq,  
1095 - gen_op_sets_T0_subq,  
1096 - NULL,  
1097 - gen_op_setl_T0_subq,  
1098 - gen_op_setle_T0_subq,  
1099 - },  
1100 -#endif  
1101 -};  
1102 -  
1103 static void *helper_fp_arith_ST0_FT0[8] = { 1291 static void *helper_fp_arith_ST0_FT0[8] = {
1104 helper_fadd_ST0_FT0, 1292 helper_fadd_ST0_FT0,
1105 helper_fmul_ST0_FT0, 1293 helper_fmul_ST0_FT0,
@@ -1123,50 +1311,6 @@ static void *helper_fp_arith_STN_ST0[8] = { @@ -1123,50 +1311,6 @@ static void *helper_fp_arith_STN_ST0[8] = {
1123 helper_fdiv_STN_ST0, 1311 helper_fdiv_STN_ST0,
1124 }; 1312 };
1125 1313
1126 -/* compute eflags.C to reg */  
1127 -static void gen_compute_eflags_c(TCGv reg)  
1128 -{  
1129 -#if TCG_TARGET_REG_BITS == 32  
1130 - tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);  
1131 - tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,  
1132 - (long)cc_table + offsetof(CCTable, compute_c));  
1133 - tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);  
1134 - tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,  
1135 - 1, &cpu_tmp2_i32, 0, NULL);  
1136 -#else  
1137 - tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);  
1138 - tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);  
1139 - tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,  
1140 - (long)cc_table + offsetof(CCTable, compute_c));  
1141 - tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);  
1142 - tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,  
1143 - 1, &cpu_tmp2_i32, 0, NULL);  
1144 -#endif  
1145 - tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);  
1146 -}  
1147 -  
1148 -/* compute all eflags to cc_src */  
1149 -static void gen_compute_eflags(TCGv reg)  
1150 -{  
1151 -#if TCG_TARGET_REG_BITS == 32  
1152 - tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);  
1153 - tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,  
1154 - (long)cc_table + offsetof(CCTable, compute_all));  
1155 - tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);  
1156 - tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,  
1157 - 1, &cpu_tmp2_i32, 0, NULL);  
1158 -#else  
1159 - tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);  
1160 - tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);  
1161 - tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,  
1162 - (long)cc_table + offsetof(CCTable, compute_all));  
1163 - tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);  
1164 - tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,  
1165 - 1, &cpu_tmp2_i32, 0, NULL);  
1166 -#endif  
1167 - tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);  
1168 -}  
1169 -  
1170 /* if d == OR_TMP0, it means memory operand (address in A0) */ 1314 /* if d == OR_TMP0, it means memory operand (address in A0) */
1171 static void gen_op(DisasContext *s1, int op, int ot, int d) 1315 static void gen_op(DisasContext *s1, int op, int ot, int d)
1172 { 1316 {
@@ -1974,125 +2118,31 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) @@ -1974,125 +2118,31 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
1974 static inline void gen_jcc(DisasContext *s, int b, 2118 static inline void gen_jcc(DisasContext *s, int b,
1975 target_ulong val, target_ulong next_eip) 2119 target_ulong val, target_ulong next_eip)
1976 { 2120 {
1977 - TranslationBlock *tb;  
1978 - int inv, jcc_op;  
1979 - GenOpFunc1 *func;  
1980 - target_ulong tmp;  
1981 - int l1, l2;  
1982 -  
1983 - inv = b & 1;  
1984 - jcc_op = (b >> 1) & 7; 2121 + int l1, l2, cc_op;
1985 2122
  2123 + cc_op = s->cc_op;
  2124 + if (s->cc_op != CC_OP_DYNAMIC) {
  2125 + gen_op_set_cc_op(s->cc_op);
  2126 + s->cc_op = CC_OP_DYNAMIC;
  2127 + }
1986 if (s->jmp_opt) { 2128 if (s->jmp_opt) {
1987 - switch(s->cc_op) {  
1988 - /* we optimize the cmp/jcc case */  
1989 - case CC_OP_SUBB:  
1990 - case CC_OP_SUBW:  
1991 - case CC_OP_SUBL:  
1992 - case CC_OP_SUBQ:  
1993 - func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];  
1994 - break;  
1995 -  
1996 - /* some jumps are easy to compute */  
1997 - case CC_OP_ADDB:  
1998 - case CC_OP_ADDW:  
1999 - case CC_OP_ADDL:  
2000 - case CC_OP_ADDQ:  
2001 -  
2002 - case CC_OP_ADCB:  
2003 - case CC_OP_ADCW:  
2004 - case CC_OP_ADCL:  
2005 - case CC_OP_ADCQ:  
2006 -  
2007 - case CC_OP_SBBB:  
2008 - case CC_OP_SBBW:  
2009 - case CC_OP_SBBL:  
2010 - case CC_OP_SBBQ:  
2011 -  
2012 - case CC_OP_LOGICB:  
2013 - case CC_OP_LOGICW:  
2014 - case CC_OP_LOGICL:  
2015 - case CC_OP_LOGICQ:  
2016 -  
2017 - case CC_OP_INCB:  
2018 - case CC_OP_INCW:  
2019 - case CC_OP_INCL:  
2020 - case CC_OP_INCQ:  
2021 -  
2022 - case CC_OP_DECB:  
2023 - case CC_OP_DECW:  
2024 - case CC_OP_DECL:  
2025 - case CC_OP_DECQ:  
2026 -  
2027 - case CC_OP_SHLB:  
2028 - case CC_OP_SHLW:  
2029 - case CC_OP_SHLL:  
2030 - case CC_OP_SHLQ:  
2031 -  
2032 - case CC_OP_SARB:  
2033 - case CC_OP_SARW:  
2034 - case CC_OP_SARL:  
2035 - case CC_OP_SARQ:  
2036 - switch(jcc_op) {  
2037 - case JCC_Z:  
2038 - func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];  
2039 - break;  
2040 - case JCC_S:  
2041 - func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];  
2042 - break;  
2043 - default:  
2044 - func = NULL;  
2045 - break;  
2046 - }  
2047 - break;  
2048 - default:  
2049 - func = NULL;  
2050 - break;  
2051 - }  
2052 -  
2053 - if (s->cc_op != CC_OP_DYNAMIC) {  
2054 - gen_op_set_cc_op(s->cc_op);  
2055 - s->cc_op = CC_OP_DYNAMIC;  
2056 - }  
2057 -  
2058 - if (!func) {  
2059 - gen_setcc_slow[jcc_op]();  
2060 - func = gen_op_jnz_T0_label;  
2061 - }  
2062 -  
2063 - if (inv) {  
2064 - tmp = val;  
2065 - val = next_eip;  
2066 - next_eip = tmp;  
2067 - }  
2068 - tb = s->tb;  
2069 -  
2070 l1 = gen_new_label(); 2129 l1 = gen_new_label();
2071 - func(l1);  
2072 - 2130 + gen_jcc1(s, cc_op, b, l1);
  2131 +
2073 gen_goto_tb(s, 0, next_eip); 2132 gen_goto_tb(s, 0, next_eip);
2074 2133
2075 gen_set_label(l1); 2134 gen_set_label(l1);
2076 gen_goto_tb(s, 1, val); 2135 gen_goto_tb(s, 1, val);
2077 -  
2078 s->is_jmp = 3; 2136 s->is_jmp = 3;
2079 } else { 2137 } else {
2080 2138
2081 - if (s->cc_op != CC_OP_DYNAMIC) {  
2082 - gen_op_set_cc_op(s->cc_op);  
2083 - s->cc_op = CC_OP_DYNAMIC;  
2084 - }  
2085 - gen_setcc_slow[jcc_op]();  
2086 - if (inv) {  
2087 - tmp = val;  
2088 - val = next_eip;  
2089 - next_eip = tmp;  
2090 - }  
2091 l1 = gen_new_label(); 2139 l1 = gen_new_label();
2092 l2 = gen_new_label(); 2140 l2 = gen_new_label();
2093 - gen_op_jnz_T0_label(l1); 2141 + gen_jcc1(s, cc_op, b, l1);
  2142 +
2094 gen_jmp_im(next_eip); 2143 gen_jmp_im(next_eip);
2095 - gen_op_jmp_label(l2); 2144 + tcg_gen_br(l2);
  2145 +
2096 gen_set_label(l1); 2146 gen_set_label(l1);
2097 gen_jmp_im(val); 2147 gen_jmp_im(val);
2098 gen_set_label(l2); 2148 gen_set_label(l2);
@@ -2102,68 +2152,27 @@ static inline void gen_jcc(DisasContext *s, int b, @@ -2102,68 +2152,27 @@ static inline void gen_jcc(DisasContext *s, int b,
2102 2152
2103 static void gen_setcc(DisasContext *s, int b) 2153 static void gen_setcc(DisasContext *s, int b)
2104 { 2154 {
2105 - int inv, jcc_op;  
2106 - GenOpFunc *func;  
2107 -  
2108 - inv = b & 1;  
2109 - jcc_op = (b >> 1) & 7;  
2110 - switch(s->cc_op) {  
2111 - /* we optimize the cmp/jcc case */  
2112 - case CC_OP_SUBB:  
2113 - case CC_OP_SUBW:  
2114 - case CC_OP_SUBL:  
2115 - case CC_OP_SUBQ:  
2116 - func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];  
2117 - if (!func)  
2118 - goto slow_jcc;  
2119 - break;  
2120 -  
2121 - /* some jumps are easy to compute */  
2122 - case CC_OP_ADDB:  
2123 - case CC_OP_ADDW:  
2124 - case CC_OP_ADDL:  
2125 - case CC_OP_ADDQ:  
2126 -  
2127 - case CC_OP_LOGICB:  
2128 - case CC_OP_LOGICW:  
2129 - case CC_OP_LOGICL:  
2130 - case CC_OP_LOGICQ:  
2131 -  
2132 - case CC_OP_INCB:  
2133 - case CC_OP_INCW:  
2134 - case CC_OP_INCL:  
2135 - case CC_OP_INCQ:  
2136 -  
2137 - case CC_OP_DECB:  
2138 - case CC_OP_DECW:  
2139 - case CC_OP_DECL:  
2140 - case CC_OP_DECQ: 2155 + int inv, jcc_op, l1;
2141 2156
2142 - case CC_OP_SHLB:  
2143 - case CC_OP_SHLW:  
2144 - case CC_OP_SHLL:  
2145 - case CC_OP_SHLQ:  
2146 - switch(jcc_op) {  
2147 - case JCC_Z:  
2148 - func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];  
2149 - break;  
2150 - case JCC_S:  
2151 - func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];  
2152 - break;  
2153 - default:  
2154 - goto slow_jcc;  
2155 - }  
2156 - break;  
2157 - default:  
2158 - slow_jcc: 2157 + if (is_fast_jcc_case(s, b)) {
  2158 + /* nominal case: we use a jump */
  2159 + tcg_gen_movi_tl(cpu_T[0], 0);
  2160 + l1 = gen_new_label();
  2161 + gen_jcc1(s, s->cc_op, b ^ 1, l1);
  2162 + tcg_gen_movi_tl(cpu_T[0], 1);
  2163 + gen_set_label(l1);
  2164 + } else {
  2165 + /* slow case: it is more efficient not to generate a jump,
  2166 + although it is questionnable whether this optimization is
  2167 + worth to */
  2168 + inv = b & 1;
  2169 + jcc_op = (b >> 1) & 7;
2159 if (s->cc_op != CC_OP_DYNAMIC) 2170 if (s->cc_op != CC_OP_DYNAMIC)
2160 gen_op_set_cc_op(s->cc_op); 2171 gen_op_set_cc_op(s->cc_op);
2161 - func = gen_setcc_slow[jcc_op];  
2162 - break;  
2163 - }  
2164 - func();  
2165 - if (inv) {  
2166 - gen_op_xor_T0_1(); 2172 + gen_setcc_slow_T0(jcc_op);
  2173 + if (inv) {
  2174 + tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
  2175 + }
2167 } 2176 }
2168 } 2177 }
2169 2178
@@ -5708,19 +5717,39 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) @@ -5708,19 +5717,39 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
5708 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1); 5717 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
5709 break; 5718 break;
5710 case 0x140 ... 0x14f: /* cmov Gv, Ev */ 5719 case 0x140 ... 0x14f: /* cmov Gv, Ev */
5711 - ot = dflag + OT_WORD;  
5712 - modrm = ldub_code(s->pc++);  
5713 - reg = ((modrm >> 3) & 7) | rex_r;  
5714 - mod = (modrm >> 6) & 3;  
5715 - gen_setcc(s, b);  
5716 - if (mod != 3) {  
5717 - gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);  
5718 - gen_op_ld_T1_A0(ot + s->mem_index);  
5719 - } else {  
5720 - rm = (modrm & 7) | REX_B(s);  
5721 - gen_op_mov_TN_reg(ot, 1, rm); 5720 + {
  5721 + int l1;
  5722 + ot = dflag + OT_WORD;
  5723 + modrm = ldub_code(s->pc++);
  5724 + reg = ((modrm >> 3) & 7) | rex_r;
  5725 + mod = (modrm >> 6) & 3;
  5726 + if (mod != 3) {
  5727 + gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
  5728 + gen_op_ld_T1_A0(ot + s->mem_index);
  5729 + } else {
  5730 + rm = (modrm & 7) | REX_B(s);
  5731 + gen_op_mov_TN_reg(ot, 1, rm);
  5732 + }
  5733 + if (s->cc_op != CC_OP_DYNAMIC)
  5734 + gen_op_set_cc_op(s->cc_op);
  5735 +#ifdef TARGET_X86_64
  5736 + if (ot == OT_LONG) {
  5737 + /* XXX: specific Intel behaviour ? */
  5738 + l1 = gen_new_label();
  5739 + gen_jcc1(s, s->cc_op, b ^ 1, l1);
  5740 + tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
  5741 + gen_set_label(l1);
  5742 + tcg_gen_movi_tl(cpu_tmp0, 0);
  5743 + tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
  5744 + } else
  5745 +#endif
  5746 + {
  5747 + l1 = gen_new_label();
  5748 + gen_jcc1(s, s->cc_op, b ^ 1, l1);
  5749 + gen_op_mov_reg_T1(ot, reg);
  5750 + gen_set_label(l1);
  5751 + }
5722 } 5752 }
5723 - gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();  
5724 break; 5753 break;
5725 5754
5726 /************************/ 5755 /************************/
@@ -6191,7 +6220,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) @@ -6191,7 +6220,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
6191 6220
6192 gen_set_label(l3); 6221 gen_set_label(l3);
6193 gen_jmp_im(next_eip); 6222 gen_jmp_im(next_eip);
6194 - gen_op_jmp_label(l2); 6223 + tcg_gen_br(l2);
6195 6224
6196 gen_set_label(l1); 6225 gen_set_label(l1);
6197 gen_jmp_im(tval); 6226 gen_jmp_im(tval);