Commit 8e129e0748f866d730f1e39bff296219fedac244
1 parent
38a34e1d
Handle MMC card insertion/removal/readonly signals.
Hook them up to Palm T|E GPIOs. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3471 c046a42c-6fe2-441c-8c8c-71466251a162
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4 changed files
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57 additions
and
2 deletions
hw/omap.c
| ... | ... | @@ -2882,7 +2882,9 @@ static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr) |
| 2882 | 2882 | |
| 2883 | 2883 | case 0x24: /* GPIO_INT */ |
| 2884 | 2884 | ret = s->ints; |
| 2885 | - s->ints &= ~s->mask; | |
| 2885 | + s->ints &= s->mask; | |
| 2886 | + if (ret) | |
| 2887 | + qemu_irq_lower(s->irq); | |
| 2886 | 2888 | return ret; |
| 2887 | 2889 | |
| 2888 | 2890 | case 0x28: /* KBD_MASKIT */ | ... | ... |
hw/omap.h
| ... | ... | @@ -470,6 +470,7 @@ struct omap_mmc_s; |
| 470 | 470 | struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base, |
| 471 | 471 | qemu_irq irq, qemu_irq dma[], omap_clk clk); |
| 472 | 472 | void omap_mmc_reset(struct omap_mmc_s *s); |
| 473 | +void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); | |
| 473 | 474 | |
| 474 | 475 | # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) |
| 475 | 476 | # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) | ... | ... |
hw/omap_mmc.c
| ... | ... | @@ -25,6 +25,7 @@ struct omap_mmc_s { |
| 25 | 25 | target_phys_addr_t base; |
| 26 | 26 | qemu_irq irq; |
| 27 | 27 | qemu_irq *dma; |
| 28 | + qemu_irq handler[2]; | |
| 28 | 29 | omap_clk clk; |
| 29 | 30 | SDState *card; |
| 30 | 31 | uint16_t last_cmd; |
| ... | ... | @@ -506,6 +507,22 @@ void omap_mmc_reset(struct omap_mmc_s *host) |
| 506 | 507 | host->transfer = 0; |
| 507 | 508 | } |
| 508 | 509 | |
| 510 | +static void omap_mmc_ro_cb(void *opaque, int level) | |
| 511 | +{ | |
| 512 | + struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; | |
| 513 | + | |
| 514 | + if (s->handler[0]) | |
| 515 | + qemu_set_irq(s->handler[0], level); | |
| 516 | +} | |
| 517 | + | |
| 518 | +static void omap_mmc_cover_cb(void *opaque, int level) | |
| 519 | +{ | |
| 520 | + struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; | |
| 521 | + | |
| 522 | + if (s->handler[1]) | |
| 523 | + qemu_set_irq(s->handler[1], level); | |
| 524 | +} | |
| 525 | + | |
| 509 | 526 | struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base, |
| 510 | 527 | qemu_irq irq, qemu_irq dma[], omap_clk clk) |
| 511 | 528 | { |
| ... | ... | @@ -525,7 +542,13 @@ struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base, |
| 525 | 542 | /* Instantiate the storage */ |
| 526 | 543 | s->card = sd_init(sd_bdrv); |
| 527 | 544 | |
| 545 | + sd_set_cb(s->card, s, omap_mmc_ro_cb, omap_mmc_cover_cb); | |
| 546 | + | |
| 528 | 547 | return s; |
| 529 | 548 | } |
| 530 | 549 | |
| 531 | -/* TODO: insertion and read-only handlers */ | |
| 550 | +void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover) | |
| 551 | +{ | |
| 552 | + s->handler[0] = ro; | |
| 553 | + s->handler[1] = cover; | |
| 554 | +} | ... | ... |
hw/palm.c
| ... | ... | @@ -57,6 +57,24 @@ static CPUWriteMemoryFunc *static_writefn[] = { |
| 57 | 57 | }; |
| 58 | 58 | |
| 59 | 59 | /* Palm Tunsgten|E support */ |
| 60 | + | |
| 61 | +/* Shared GPIOs */ | |
| 62 | +#define PALMTE_USBDETECT_GPIO 0 | |
| 63 | +#define PALMTE_USB_OR_DC_GPIO 1 | |
| 64 | +#define PALMTE_TSC_GPIO 4 | |
| 65 | +#define PALMTE_PINTDAV_GPIO 6 | |
| 66 | +#define PALMTE_MMC_WP_GPIO 8 | |
| 67 | +#define PALMTE_MMC_POWER_GPIO 9 | |
| 68 | +#define PALMTE_HDQ_GPIO 11 | |
| 69 | +#define PALMTE_HEADPHONES_GPIO 14 | |
| 70 | +#define PALMTE_SPEAKER_GPIO 15 | |
| 71 | +/* MPU private GPIOs */ | |
| 72 | +#define PALMTE_DC_GPIO 2 | |
| 73 | +#define PALMTE_MMC_SWITCH_GPIO 4 | |
| 74 | +#define PALMTE_MMC1_GPIO 6 | |
| 75 | +#define PALMTE_MMC2_GPIO 7 | |
| 76 | +#define PALMTE_MMC3_GPIO 11 | |
| 77 | + | |
| 60 | 78 | static void palmte_microwire_setup(struct omap_mpu_state_s *cpu) |
| 61 | 79 | { |
| 62 | 80 | } |
| ... | ... | @@ -90,6 +108,14 @@ static void palmte_button_event(void *opaque, int keycode) |
| 90 | 108 | !(keycode & 0x80)); |
| 91 | 109 | } |
| 92 | 110 | |
| 111 | +static void palmte_mmc_cover(void *opaque, int line, int level) | |
| 112 | +{ | |
| 113 | + struct omap_mpu_state_s *cpu = (struct omap_mpu_state_s *) opaque; | |
| 114 | + | |
| 115 | + qemu_set_irq(omap_mpuio_in_get(cpu->mpuio)[PALMTE_MMC_SWITCH_GPIO], | |
| 116 | + !level); | |
| 117 | +} | |
| 118 | + | |
| 93 | 119 | static void palmte_init(int ram_size, int vga_ram_size, int boot_device, |
| 94 | 120 | DisplayState *ds, const char **fd_filename, int snapshot, |
| 95 | 121 | const char *kernel_filename, const char *kernel_cmdline, |
| ... | ... | @@ -132,6 +158,9 @@ static void palmte_init(int ram_size, int vga_ram_size, int boot_device, |
| 132 | 158 | |
| 133 | 159 | qemu_add_kbd_event_handler(palmte_button_event, cpu); |
| 134 | 160 | |
| 161 | + omap_mmc_handlers(cpu->mmc, 0, | |
| 162 | + qemu_allocate_irqs(palmte_mmc_cover, cpu, 1)[0]); | |
| 163 | + | |
| 135 | 164 | /* Setup initial (reset) machine state */ |
| 136 | 165 | if (nb_option_roms) { |
| 137 | 166 | rom_size = get_image_size(option_rom[0]); | ... | ... |