Commit 8dea1dd406189dae6108104faf27f397835ae871
1 parent
ce802585
Misc fixes (Herve Poussineau)
- Fix internal fifo size (16 bytes), according to http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt - Fix values of STAT_MI and STAT_MO - Give a scsi ID to adapter, and prevent this ID to be used by devices - Prevent fifo overrun in esp_mem_writeb - Add a ESP_ERROR macro, and use it where appropriate git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5811 c046a42c-6fe2-441c-8c8c-71466251a162
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21 additions
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14 deletions
hw/esp.c
| @@ -44,8 +44,11 @@ do { printf("ESP: " fmt , ##args); } while (0) | @@ -44,8 +44,11 @@ do { printf("ESP: " fmt , ##args); } while (0) | ||
| 44 | #define DPRINTF(fmt, args...) do {} while (0) | 44 | #define DPRINTF(fmt, args...) do {} while (0) |
| 45 | #endif | 45 | #endif |
| 46 | 46 | ||
| 47 | +#define ESP_ERROR(fmt, args...) \ | ||
| 48 | +do { printf("ESP ERROR: %s: " fmt, __func__ , ##args); } while (0) | ||
| 49 | + | ||
| 47 | #define ESP_REGS 16 | 50 | #define ESP_REGS 16 |
| 48 | -#define TI_BUFSZ 32 | 51 | +#define TI_BUFSZ 16 |
| 49 | 52 | ||
| 50 | typedef struct ESPState ESPState; | 53 | typedef struct ESPState ESPState; |
| 51 | 54 | ||
| @@ -120,8 +123,8 @@ struct ESPState { | @@ -120,8 +123,8 @@ struct ESPState { | ||
| 120 | #define STAT_DI 0x01 | 123 | #define STAT_DI 0x01 |
| 121 | #define STAT_CD 0x02 | 124 | #define STAT_CD 0x02 |
| 122 | #define STAT_ST 0x03 | 125 | #define STAT_ST 0x03 |
| 123 | -#define STAT_MI 0x06 | ||
| 124 | -#define STAT_MO 0x07 | 126 | +#define STAT_MO 0x06 |
| 127 | +#define STAT_MI 0x07 | ||
| 125 | #define STAT_PIO_MASK 0x06 | 128 | #define STAT_PIO_MASK 0x06 |
| 126 | 129 | ||
| 127 | #define STAT_TC 0x10 | 130 | #define STAT_TC 0x10 |
| @@ -129,6 +132,8 @@ struct ESPState { | @@ -129,6 +132,8 @@ struct ESPState { | ||
| 129 | #define STAT_GE 0x40 | 132 | #define STAT_GE 0x40 |
| 130 | #define STAT_INT 0x80 | 133 | #define STAT_INT 0x80 |
| 131 | 134 | ||
| 135 | +#define BUSID_DID 0x07 | ||
| 136 | + | ||
| 132 | #define INTR_FC 0x08 | 137 | #define INTR_FC 0x08 |
| 133 | #define INTR_BS 0x10 | 138 | #define INTR_BS 0x10 |
| 134 | #define INTR_DC 0x20 | 139 | #define INTR_DC 0x20 |
| @@ -165,7 +170,7 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf) | @@ -165,7 +170,7 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf) | ||
| 165 | int target; | 170 | int target; |
| 166 | 171 | ||
| 167 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); | 172 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); |
| 168 | - target = s->wregs[ESP_WBUSID] & 7; | 173 | + target = s->wregs[ESP_WBUSID] & BUSID_DID; |
| 169 | DPRINTF("get_cmd: len %d target %d\n", dmalen, target); | 174 | DPRINTF("get_cmd: len %d target %d\n", dmalen, target); |
| 170 | if (s->dma) { | 175 | if (s->dma) { |
| 171 | s->dma_memory_read(s->dma_opaque, buf, dmalen); | 176 | s->dma_memory_read(s->dma_opaque, buf, dmalen); |
| @@ -318,7 +323,7 @@ static void esp_do_dma(ESPState *s) | @@ -318,7 +323,7 @@ static void esp_do_dma(ESPState *s) | ||
| 318 | } else { | 323 | } else { |
| 319 | s->current_dev->read_data(s->current_dev, 0); | 324 | s->current_dev->read_data(s->current_dev, 0); |
| 320 | /* If there is still data to be read from the device then | 325 | /* If there is still data to be read from the device then |
| 321 | - complete the DMA operation immeriately. Otherwise defer | 326 | + complete the DMA operation immediately. Otherwise defer |
| 322 | until the scsi layer has completed. */ | 327 | until the scsi layer has completed. */ |
| 323 | if (s->dma_left == 0 && s->ti_size > 0) { | 328 | if (s->dma_left == 0 && s->ti_size > 0) { |
| 324 | esp_dma_done(s); | 329 | esp_dma_done(s); |
| @@ -407,6 +412,8 @@ static void esp_reset(void *opaque) | @@ -407,6 +412,8 @@ static void esp_reset(void *opaque) | ||
| 407 | s->ti_wptr = 0; | 412 | s->ti_wptr = 0; |
| 408 | s->dma = 0; | 413 | s->dma = 0; |
| 409 | s->do_cmd = 0; | 414 | s->do_cmd = 0; |
| 415 | + | ||
| 416 | + s->rregs[ESP_CFG1] = 7; | ||
| 410 | } | 417 | } |
| 411 | 418 | ||
| 412 | static void parent_esp_reset(void *opaque, int irq, int level) | 419 | static void parent_esp_reset(void *opaque, int irq, int level) |
| @@ -427,8 +434,8 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) | @@ -427,8 +434,8 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) | ||
| 427 | if (s->ti_size > 0) { | 434 | if (s->ti_size > 0) { |
| 428 | s->ti_size--; | 435 | s->ti_size--; |
| 429 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { | 436 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
| 430 | - /* Data in/out. */ | ||
| 431 | - fprintf(stderr, "esp: PIO data read not implemented\n"); | 437 | + /* Data out. */ |
| 438 | + ESP_ERROR("PIO data read not implemented\n"); | ||
| 432 | s->rregs[ESP_FIFO] = 0; | 439 | s->rregs[ESP_FIFO] = 0; |
| 433 | } else { | 440 | } else { |
| 434 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; | 441 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
| @@ -467,11 +474,8 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | @@ -467,11 +474,8 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | ||
| 467 | case ESP_FIFO: | 474 | case ESP_FIFO: |
| 468 | if (s->do_cmd) { | 475 | if (s->do_cmd) { |
| 469 | s->cmdbuf[s->cmdlen++] = val & 0xff; | 476 | s->cmdbuf[s->cmdlen++] = val & 0xff; |
| 470 | - } else if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { | ||
| 471 | - uint8_t buf; | ||
| 472 | - buf = val & 0xff; | ||
| 473 | - s->ti_size--; | ||
| 474 | - fprintf(stderr, "esp: PIO data write not implemented\n"); | 477 | + } else if (s->ti_size == TI_BUFSZ - 1) { |
| 478 | + ESP_ERROR("fifo overrun\n"); | ||
| 475 | } else { | 479 | } else { |
| 476 | s->ti_size++; | 480 | s->ti_size++; |
| 477 | s->ti_buf[s->ti_wptr++] = val & 0xff; | 481 | s->ti_buf[s->ti_wptr++] = val & 0xff; |
| @@ -537,7 +541,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | @@ -537,7 +541,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | ||
| 537 | DPRINTF("Enable selection (%2.2x)\n", val); | 541 | DPRINTF("Enable selection (%2.2x)\n", val); |
| 538 | break; | 542 | break; |
| 539 | default: | 543 | default: |
| 540 | - DPRINTF("Unhandled ESP command (%2.2x)\n", val); | 544 | + ESP_ERROR("Unhandled ESP command (%2.2x)\n", val); |
| 541 | break; | 545 | break; |
| 542 | } | 546 | } |
| 543 | break; | 547 | break; |
| @@ -555,7 +559,8 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | @@ -555,7 +559,8 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | ||
| 555 | s->rregs[saddr] = val; | 559 | s->rregs[saddr] = val; |
| 556 | break; | 560 | break; |
| 557 | default: | 561 | default: |
| 558 | - break; | 562 | + ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr); |
| 563 | + return; | ||
| 559 | } | 564 | } |
| 560 | s->wregs[saddr] = val; | 565 | s->wregs[saddr] = val; |
| 561 | } | 566 | } |
| @@ -620,6 +625,8 @@ void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id) | @@ -620,6 +625,8 @@ void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id) | ||
| 620 | 625 | ||
| 621 | if (id < 0) { | 626 | if (id < 0) { |
| 622 | for (id = 0; id < ESP_MAX_DEVS; id++) { | 627 | for (id = 0; id < ESP_MAX_DEVS; id++) { |
| 628 | + if (id == (s->rregs[ESP_CFG1] & 0x7)) | ||
| 629 | + continue; | ||
| 623 | if (s->scsi_dev[id] == NULL) | 630 | if (s->scsi_dev[id] == NULL) |
| 624 | break; | 631 | break; |
| 625 | } | 632 | } |