gwj / at91sam9263 · Commits

Commit 8dd640e49daeba4a47c1f9e75e0f09aeb5578644

Authored by malc
1 parent 66c7c806

Fix mtcrf/mfcr 

Noticed by Alexander Graf

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6667 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 13 additions and 9 deletions
target-ppc/translate.c
  View file @8dd640e
@@ -3843,9 +3843,11 @@ GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC) @@ -3843,9 +3843,11 @@ GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3843 3843
3844 if (likely(ctx->opcode & 0x00100000)) { 3844 if (likely(ctx->opcode & 0x00100000)) {
3845 crm = CRM(ctx->opcode); 3845 crm = CRM(ctx->opcode);
3846 - if (likely((crm ^ (crm - 1)) == 0)) {  
3847 - crn = ffs(crm); 3846 + if (likely(crm && ((crm & (crm - 1)) == 0))) {
  3847 + crn = ffs (crm) - 1;
3848 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 3848 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
  3849 + tcg_gen_shli_i32(cpu_gpr[rD(ctx->opcode)],
  3850 + cpu_gpr[rD(ctx->opcode)], crn * 4);
3849 } 3851 }
3850 } else { 3852 } else {
3851 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]); 3853 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
@@ -3935,13 +3937,15 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) @@ -3935,13 +3937,15 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3935 uint32_t crm, crn; 3937 uint32_t crm, crn;
3936 3938
3937 crm = CRM(ctx->opcode); 3939 crm = CRM(ctx->opcode);
3938 - if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {  
3939 - TCGv_i32 temp = tcg_temp_new_i32();  
3940 - crn = ffs(crm);  
3941 - tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);  
3942 - tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);  
3943 - tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);  
3944 - tcg_temp_free_i32(temp); 3940 + if (likely((ctx->opcode & 0x00100000))) {
  3941 + if (crm && ((crm & (crm - 1)) == 0)) {
  3942 + TCGv_i32 temp = tcg_temp_new_i32();
  3943 + crn = ffs (crm) - 1;
  3944 + tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
  3945 + tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
  3946 + tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
  3947 + tcg_temp_free_i32(temp);
  3948 + }
3945 } else { 3949 } else {
3946 TCGv_i32 temp = tcg_const_i32(crm); 3950 TCGv_i32 temp = tcg_const_i32(crm);
3947 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp); 3951 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);