gwj / at91sam9263 · Commits

Commit 8dd3dca351738769f804dcb0feda4b39f3530826

Authored by aurel32
1 parent 91834991

remove target ifdefs from vl.c 

(Glauber Costa)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4327 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 11 changed files with 650 additions and 620 deletions
Makefile.target
  View file @8dd3dca
@@ -311,6 +311,9 @@ gen-op.h: op.o $(DYNGEN) @@ -311,6 +311,9 @@ gen-op.h: op.o $(DYNGEN)
311 op.o: op.c 311 op.o: op.c
312 $(CC) $(OP_CFLAGS) $(CPPFLAGS) -c -o $@ $< 312 $(CC) $(OP_CFLAGS) $(CPPFLAGS) -c -o $@ $<
313 313
  314 +machine.o: machine.c
  315 + $(CC) $(OP_CFLAGS) $(CPPFLAGS) -c -o $@ $<
  316 +
314 # HELPER_CFLAGS is used for all the code compiled with static register 317 # HELPER_CFLAGS is used for all the code compiled with static register
315 # variables 318 # variables
316 ifeq ($(TARGET_BASE_ARCH), i386) 319 ifeq ($(TARGET_BASE_ARCH), i386)
@@ -490,7 +493,7 @@ endif #CONFIG_DARWIN_USER @@ -490,7 +493,7 @@ endif #CONFIG_DARWIN_USER
490 # System emulator target 493 # System emulator target
491 ifndef CONFIG_USER_ONLY 494 ifndef CONFIG_USER_ONLY
492 495
493 -OBJS=vl.o osdep.o monitor.o pci.o loader.o isa_mmio.o 496 +OBJS=vl.o osdep.o monitor.o pci.o loader.o isa_mmio.o machine.o
494 ifdef CONFIG_WIN32 497 ifdef CONFIG_WIN32
495 OBJS+=block-raw-win32.o 498 OBJS+=block-raw-win32.o
496 else 499 else
hw/boards.h
  View file @8dd3dca
@@ -20,6 +20,7 @@ typedef struct QEMUMachine { @@ -20,6 +20,7 @@ typedef struct QEMUMachine {
20 } QEMUMachine; 20 } QEMUMachine;
21 21
22 int qemu_register_machine(QEMUMachine *m); 22 int qemu_register_machine(QEMUMachine *m);
  23 +void register_machines(void);
23 24
24 /* Axis ETRAX. */ 25 /* Axis ETRAX. */
25 extern QEMUMachine bareetraxfs_machine; 26 extern QEMUMachine bareetraxfs_machine;
target-arm/machine.c 0 → 100644
  View file @8dd3dca
  1 +#include "hw/hw.h"
  2 +#include "hw/boards.h"
  3 +
  4 +void register_machines(void)
  5 +{
  6 + qemu_register_machine(&integratorcp_machine);
  7 + qemu_register_machine(&versatilepb_machine);
  8 + qemu_register_machine(&versatileab_machine);
  9 + qemu_register_machine(&realview_machine);
  10 + qemu_register_machine(&akitapda_machine);
  11 + qemu_register_machine(&spitzpda_machine);
  12 + qemu_register_machine(&borzoipda_machine);
  13 + qemu_register_machine(&terrierpda_machine);
  14 + qemu_register_machine(&palmte_machine);
  15 + qemu_register_machine(&n800_machine);
  16 + qemu_register_machine(&lm3s811evb_machine);
  17 + qemu_register_machine(&lm3s6965evb_machine);
  18 + qemu_register_machine(&connex_machine);
  19 + qemu_register_machine(&verdex_machine);
  20 + qemu_register_machine(&mainstone2_machine);
  21 + qemu_register_machine(&musicpal_machine);
  22 +}
  23 +
  24 +void cpu_save(QEMUFile *f, void *opaque)
  25 +{
  26 + int i;
  27 + CPUARMState *env = (CPUARMState *)opaque;
  28 +
  29 + for (i = 0; i < 16; i++) {
  30 + qemu_put_be32(f, env->regs[i]);
  31 + }
  32 + qemu_put_be32(f, cpsr_read(env));
  33 + qemu_put_be32(f, env->spsr);
  34 + for (i = 0; i < 6; i++) {
  35 + qemu_put_be32(f, env->banked_spsr[i]);
  36 + qemu_put_be32(f, env->banked_r13[i]);
  37 + qemu_put_be32(f, env->banked_r14[i]);
  38 + }
  39 + for (i = 0; i < 5; i++) {
  40 + qemu_put_be32(f, env->usr_regs[i]);
  41 + qemu_put_be32(f, env->fiq_regs[i]);
  42 + }
  43 + qemu_put_be32(f, env->cp15.c0_cpuid);
  44 + qemu_put_be32(f, env->cp15.c0_cachetype);
  45 + qemu_put_be32(f, env->cp15.c1_sys);
  46 + qemu_put_be32(f, env->cp15.c1_coproc);
  47 + qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
  48 + qemu_put_be32(f, env->cp15.c2_base0);
  49 + qemu_put_be32(f, env->cp15.c2_base1);
  50 + qemu_put_be32(f, env->cp15.c2_mask);
  51 + qemu_put_be32(f, env->cp15.c2_data);
  52 + qemu_put_be32(f, env->cp15.c2_insn);
  53 + qemu_put_be32(f, env->cp15.c3);
  54 + qemu_put_be32(f, env->cp15.c5_insn);
  55 + qemu_put_be32(f, env->cp15.c5_data);
  56 + for (i = 0; i < 8; i++) {
  57 + qemu_put_be32(f, env->cp15.c6_region[i]);
  58 + }
  59 + qemu_put_be32(f, env->cp15.c6_insn);
  60 + qemu_put_be32(f, env->cp15.c6_data);
  61 + qemu_put_be32(f, env->cp15.c9_insn);
  62 + qemu_put_be32(f, env->cp15.c9_data);
  63 + qemu_put_be32(f, env->cp15.c13_fcse);
  64 + qemu_put_be32(f, env->cp15.c13_context);
  65 + qemu_put_be32(f, env->cp15.c13_tls1);
  66 + qemu_put_be32(f, env->cp15.c13_tls2);
  67 + qemu_put_be32(f, env->cp15.c13_tls3);
  68 + qemu_put_be32(f, env->cp15.c15_cpar);
  69 +
  70 + qemu_put_be32(f, env->features);
  71 +
  72 + if (arm_feature(env, ARM_FEATURE_VFP)) {
  73 + for (i = 0; i < 16; i++) {
  74 + CPU_DoubleU u;
  75 + u.d = env->vfp.regs[i];
  76 + qemu_put_be32(f, u.l.upper);
  77 + qemu_put_be32(f, u.l.lower);
  78 + }
  79 + for (i = 0; i < 16; i++) {
  80 + qemu_put_be32(f, env->vfp.xregs[i]);
  81 + }
  82 +
  83 + /* TODO: Should use proper FPSCR access functions. */
  84 + qemu_put_be32(f, env->vfp.vec_len);
  85 + qemu_put_be32(f, env->vfp.vec_stride);
  86 +
  87 + if (arm_feature(env, ARM_FEATURE_VFP3)) {
  88 + for (i = 16; i < 32; i++) {
  89 + CPU_DoubleU u;
  90 + u.d = env->vfp.regs[i];
  91 + qemu_put_be32(f, u.l.upper);
  92 + qemu_put_be32(f, u.l.lower);
  93 + }
  94 + }
  95 + }
  96 +
  97 + if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  98 + for (i = 0; i < 16; i++) {
  99 + qemu_put_be64(f, env->iwmmxt.regs[i]);
  100 + }
  101 + for (i = 0; i < 16; i++) {
  102 + qemu_put_be32(f, env->iwmmxt.cregs[i]);
  103 + }
  104 + }
  105 +
  106 + if (arm_feature(env, ARM_FEATURE_M)) {
  107 + qemu_put_be32(f, env->v7m.other_sp);
  108 + qemu_put_be32(f, env->v7m.vecbase);
  109 + qemu_put_be32(f, env->v7m.basepri);
  110 + qemu_put_be32(f, env->v7m.control);
  111 + qemu_put_be32(f, env->v7m.current_sp);
  112 + qemu_put_be32(f, env->v7m.exception);
  113 + }
  114 +}
  115 +
  116 +int cpu_load(QEMUFile *f, void *opaque, int version_id)
  117 +{
  118 + CPUARMState *env = (CPUARMState *)opaque;
  119 + int i;
  120 +
  121 + if (version_id != ARM_CPU_SAVE_VERSION)
  122 + return -EINVAL;
  123 +
  124 + for (i = 0; i < 16; i++) {
  125 + env->regs[i] = qemu_get_be32(f);
  126 + }
  127 + cpsr_write(env, qemu_get_be32(f), 0xffffffff);
  128 + env->spsr = qemu_get_be32(f);
  129 + for (i = 0; i < 6; i++) {
  130 + env->banked_spsr[i] = qemu_get_be32(f);
  131 + env->banked_r13[i] = qemu_get_be32(f);
  132 + env->banked_r14[i] = qemu_get_be32(f);
  133 + }
  134 + for (i = 0; i < 5; i++) {
  135 + env->usr_regs[i] = qemu_get_be32(f);
  136 + env->fiq_regs[i] = qemu_get_be32(f);
  137 + }
  138 + env->cp15.c0_cpuid = qemu_get_be32(f);
  139 + env->cp15.c0_cachetype = qemu_get_be32(f);
  140 + env->cp15.c1_sys = qemu_get_be32(f);
  141 + env->cp15.c1_coproc = qemu_get_be32(f);
  142 + env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
  143 + env->cp15.c2_base0 = qemu_get_be32(f);
  144 + env->cp15.c2_base1 = qemu_get_be32(f);
  145 + env->cp15.c2_mask = qemu_get_be32(f);
  146 + env->cp15.c2_data = qemu_get_be32(f);
  147 + env->cp15.c2_insn = qemu_get_be32(f);
  148 + env->cp15.c3 = qemu_get_be32(f);
  149 + env->cp15.c5_insn = qemu_get_be32(f);
  150 + env->cp15.c5_data = qemu_get_be32(f);
  151 + for (i = 0; i < 8; i++) {
  152 + env->cp15.c6_region[i] = qemu_get_be32(f);
  153 + }
  154 + env->cp15.c6_insn = qemu_get_be32(f);
  155 + env->cp15.c6_data = qemu_get_be32(f);
  156 + env->cp15.c9_insn = qemu_get_be32(f);
  157 + env->cp15.c9_data = qemu_get_be32(f);
  158 + env->cp15.c13_fcse = qemu_get_be32(f);
  159 + env->cp15.c13_context = qemu_get_be32(f);
  160 + env->cp15.c13_tls1 = qemu_get_be32(f);
  161 + env->cp15.c13_tls2 = qemu_get_be32(f);
  162 + env->cp15.c13_tls3 = qemu_get_be32(f);
  163 + env->cp15.c15_cpar = qemu_get_be32(f);
  164 +
  165 + env->features = qemu_get_be32(f);
  166 +
  167 + if (arm_feature(env, ARM_FEATURE_VFP)) {
  168 + for (i = 0; i < 16; i++) {
  169 + CPU_DoubleU u;
  170 + u.l.upper = qemu_get_be32(f);
  171 + u.l.lower = qemu_get_be32(f);
  172 + env->vfp.regs[i] = u.d;
  173 + }
  174 + for (i = 0; i < 16; i++) {
  175 + env->vfp.xregs[i] = qemu_get_be32(f);
  176 + }
  177 +
  178 + /* TODO: Should use proper FPSCR access functions. */
  179 + env->vfp.vec_len = qemu_get_be32(f);
  180 + env->vfp.vec_stride = qemu_get_be32(f);
  181 +
  182 + if (arm_feature(env, ARM_FEATURE_VFP3)) {
  183 + for (i = 0; i < 16; i++) {
  184 + CPU_DoubleU u;
  185 + u.l.upper = qemu_get_be32(f);
  186 + u.l.lower = qemu_get_be32(f);
  187 + env->vfp.regs[i] = u.d;
  188 + }
  189 + }
  190 + }
  191 +
  192 + if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  193 + for (i = 0; i < 16; i++) {
  194 + env->iwmmxt.regs[i] = qemu_get_be64(f);
  195 + }
  196 + for (i = 0; i < 16; i++) {
  197 + env->iwmmxt.cregs[i] = qemu_get_be32(f);
  198 + }
  199 + }
  200 +
  201 + if (arm_feature(env, ARM_FEATURE_M)) {
  202 + env->v7m.other_sp = qemu_get_be32(f);
  203 + env->v7m.vecbase = qemu_get_be32(f);
  204 + env->v7m.basepri = qemu_get_be32(f);
  205 + env->v7m.control = qemu_get_be32(f);
  206 + env->v7m.current_sp = qemu_get_be32(f);
  207 + env->v7m.exception = qemu_get_be32(f);
  208 + }
  209 +
  210 + return 0;
  211 +}
  212 +
  213 +
target-cris/machine.c 0 → 100644
  View file @8dd3dca
  1 +#include "hw/hw.h"
  2 +#include "hw/boards.h"
  3 +
  4 +void register_machines(void)
  5 +{
  6 + qemu_register_machine(&bareetraxfs_machine);
  7 +}
target-i386/machine.c 0 → 100644
  View file @8dd3dca
  1 +#include "hw/hw.h"
  2 +#include "hw/boards.h"
  3 +#include "hw/pc.h"
  4 +#include "hw/isa.h"
  5 +
  6 +#include "exec-all.h"
  7 +
  8 +void register_machines(void)
  9 +{
  10 + qemu_register_machine(&pc_machine);
  11 + qemu_register_machine(&isapc_machine);
  12 +}
  13 +
  14 +static void cpu_put_seg(QEMUFile *f, SegmentCache *dt)
  15 +{
  16 + qemu_put_be32(f, dt->selector);
  17 + qemu_put_betl(f, dt->base);
  18 + qemu_put_be32(f, dt->limit);
  19 + qemu_put_be32(f, dt->flags);
  20 +}
  21 +
  22 +static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)
  23 +{
  24 + dt->selector = qemu_get_be32(f);
  25 + dt->base = qemu_get_betl(f);
  26 + dt->limit = qemu_get_be32(f);
  27 + dt->flags = qemu_get_be32(f);
  28 +}
  29 +
  30 +void cpu_save(QEMUFile *f, void *opaque)
  31 +{
  32 + CPUState *env = opaque;
  33 + uint16_t fptag, fpus, fpuc, fpregs_format;
  34 + uint32_t hflags;
  35 + int i;
  36 +
  37 + for(i = 0; i < CPU_NB_REGS; i++)
  38 + qemu_put_betls(f, &env->regs[i]);
  39 + qemu_put_betls(f, &env->eip);
  40 + qemu_put_betls(f, &env->eflags);
  41 + hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
  42 + qemu_put_be32s(f, &hflags);
  43 +
  44 + /* FPU */
  45 + fpuc = env->fpuc;
  46 + fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
  47 + fptag = 0;
  48 + for(i = 0; i < 8; i++) {
  49 + fptag |= ((!env->fptags[i]) << i);
  50 + }
  51 +
  52 + qemu_put_be16s(f, &fpuc);
  53 + qemu_put_be16s(f, &fpus);
  54 + qemu_put_be16s(f, &fptag);
  55 +
  56 +#ifdef USE_X86LDOUBLE
  57 + fpregs_format = 0;
  58 +#else
  59 + fpregs_format = 1;
  60 +#endif
  61 + qemu_put_be16s(f, &fpregs_format);
  62 +
  63 + for(i = 0; i < 8; i++) {
  64 +#ifdef USE_X86LDOUBLE
  65 + {
  66 + uint64_t mant;
  67 + uint16_t exp;
  68 + /* we save the real CPU data (in case of MMX usage only 'mant'
  69 + contains the MMX register */
  70 + cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
  71 + qemu_put_be64(f, mant);
  72 + qemu_put_be16(f, exp);
  73 + }
  74 +#else
  75 + /* if we use doubles for float emulation, we save the doubles to
  76 + avoid losing information in case of MMX usage. It can give
  77 + problems if the image is restored on a CPU where long
  78 + doubles are used instead. */
  79 + qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
  80 +#endif
  81 + }
  82 +
  83 + for(i = 0; i < 6; i++)
  84 + cpu_put_seg(f, &env->segs[i]);
  85 + cpu_put_seg(f, &env->ldt);
  86 + cpu_put_seg(f, &env->tr);
  87 + cpu_put_seg(f, &env->gdt);
  88 + cpu_put_seg(f, &env->idt);
  89 +
  90 + qemu_put_be32s(f, &env->sysenter_cs);
  91 + qemu_put_be32s(f, &env->sysenter_esp);
  92 + qemu_put_be32s(f, &env->sysenter_eip);
  93 +
  94 + qemu_put_betls(f, &env->cr[0]);
  95 + qemu_put_betls(f, &env->cr[2]);
  96 + qemu_put_betls(f, &env->cr[3]);
  97 + qemu_put_betls(f, &env->cr[4]);
  98 +
  99 + for(i = 0; i < 8; i++)
  100 + qemu_put_betls(f, &env->dr[i]);
  101 +
  102 + /* MMU */
  103 + qemu_put_be32s(f, &env->a20_mask);
  104 +
  105 + /* XMM */
  106 + qemu_put_be32s(f, &env->mxcsr);
  107 + for(i = 0; i < CPU_NB_REGS; i++) {
  108 + qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
  109 + qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
  110 + }
  111 +
  112 +#ifdef TARGET_X86_64
  113 + qemu_put_be64s(f, &env->efer);
  114 + qemu_put_be64s(f, &env->star);
  115 + qemu_put_be64s(f, &env->lstar);
  116 + qemu_put_be64s(f, &env->cstar);
  117 + qemu_put_be64s(f, &env->fmask);
  118 + qemu_put_be64s(f, &env->kernelgsbase);
  119 +#endif
  120 + qemu_put_be32s(f, &env->smbase);
  121 +}
  122 +
  123 +#ifdef USE_X86LDOUBLE
  124 +/* XXX: add that in a FPU generic layer */
  125 +union x86_longdouble {
  126 + uint64_t mant;
  127 + uint16_t exp;
  128 +};
  129 +
  130 +#define MANTD1(fp) (fp & ((1LL << 52) - 1))
  131 +#define EXPBIAS1 1023
  132 +#define EXPD1(fp) ((fp >> 52) & 0x7FF)
  133 +#define SIGND1(fp) ((fp >> 32) & 0x80000000)
  134 +
  135 +static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
  136 +{
  137 + int e;
  138 + /* mantissa */
  139 + p->mant = (MANTD1(temp) << 11) | (1LL << 63);
  140 + /* exponent + sign */
  141 + e = EXPD1(temp) - EXPBIAS1 + 16383;
  142 + e |= SIGND1(temp) >> 16;
  143 + p->exp = e;
  144 +}
  145 +#endif
  146 +
  147 +int cpu_load(QEMUFile *f, void *opaque, int version_id)
  148 +{
  149 + CPUState *env = opaque;
  150 + int i, guess_mmx;
  151 + uint32_t hflags;
  152 + uint16_t fpus, fpuc, fptag, fpregs_format;
  153 +
  154 + if (version_id != 3 && version_id != 4)
  155 + return -EINVAL;
  156 + for(i = 0; i < CPU_NB_REGS; i++)
  157 + qemu_get_betls(f, &env->regs[i]);
  158 + qemu_get_betls(f, &env->eip);
  159 + qemu_get_betls(f, &env->eflags);
  160 + qemu_get_be32s(f, &hflags);
  161 +
  162 + qemu_get_be16s(f, &fpuc);
  163 + qemu_get_be16s(f, &fpus);
  164 + qemu_get_be16s(f, &fptag);
  165 + qemu_get_be16s(f, &fpregs_format);
  166 +
  167 + /* NOTE: we cannot always restore the FPU state if the image come
  168 + from a host with a different 'USE_X86LDOUBLE' define. We guess
  169 + if we are in an MMX state to restore correctly in that case. */
  170 + guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
  171 + for(i = 0; i < 8; i++) {
  172 + uint64_t mant;
  173 + uint16_t exp;
  174 +
  175 + switch(fpregs_format) {
  176 + case 0:
  177 + mant = qemu_get_be64(f);
  178 + exp = qemu_get_be16(f);
  179 +#ifdef USE_X86LDOUBLE
  180 + env->fpregs[i].d = cpu_set_fp80(mant, exp);
  181 +#else
  182 + /* difficult case */
  183 + if (guess_mmx)
  184 + env->fpregs[i].mmx.MMX_Q(0) = mant;
  185 + else
  186 + env->fpregs[i].d = cpu_set_fp80(mant, exp);
  187 +#endif
  188 + break;
  189 + case 1:
  190 + mant = qemu_get_be64(f);
  191 +#ifdef USE_X86LDOUBLE
  192 + {
  193 + union x86_longdouble *p;
  194 + /* difficult case */
  195 + p = (void *)&env->fpregs[i];
  196 + if (guess_mmx) {
  197 + p->mant = mant;
  198 + p->exp = 0xffff;
  199 + } else {
  200 + fp64_to_fp80(p, mant);
  201 + }
  202 + }
  203 +#else
  204 + env->fpregs[i].mmx.MMX_Q(0) = mant;
  205 +#endif
  206 + break;
  207 + default:
  208 + return -EINVAL;
  209 + }
  210 + }
  211 +
  212 + env->fpuc = fpuc;
  213 + /* XXX: restore FPU round state */
  214 + env->fpstt = (fpus >> 11) & 7;
  215 + env->fpus = fpus & ~0x3800;
  216 + fptag ^= 0xff;
  217 + for(i = 0; i < 8; i++) {
  218 + env->fptags[i] = (fptag >> i) & 1;
  219 + }
  220 +
  221 + for(i = 0; i < 6; i++)
  222 + cpu_get_seg(f, &env->segs[i]);
  223 + cpu_get_seg(f, &env->ldt);
  224 + cpu_get_seg(f, &env->tr);
  225 + cpu_get_seg(f, &env->gdt);
  226 + cpu_get_seg(f, &env->idt);
  227 +
  228 + qemu_get_be32s(f, &env->sysenter_cs);
  229 + qemu_get_be32s(f, &env->sysenter_esp);
  230 + qemu_get_be32s(f, &env->sysenter_eip);
  231 +
  232 + qemu_get_betls(f, &env->cr[0]);
  233 + qemu_get_betls(f, &env->cr[2]);
  234 + qemu_get_betls(f, &env->cr[3]);
  235 + qemu_get_betls(f, &env->cr[4]);
  236 +
  237 + for(i = 0; i < 8; i++)
  238 + qemu_get_betls(f, &env->dr[i]);
  239 +
  240 + /* MMU */
  241 + qemu_get_be32s(f, &env->a20_mask);
  242 +
  243 + qemu_get_be32s(f, &env->mxcsr);
  244 + for(i = 0; i < CPU_NB_REGS; i++) {
  245 + qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
  246 + qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
  247 + }
  248 +
  249 +#ifdef TARGET_X86_64
  250 + qemu_get_be64s(f, &env->efer);
  251 + qemu_get_be64s(f, &env->star);
  252 + qemu_get_be64s(f, &env->lstar);
  253 + qemu_get_be64s(f, &env->cstar);
  254 + qemu_get_be64s(f, &env->fmask);
  255 + qemu_get_be64s(f, &env->kernelgsbase);
  256 +#endif
  257 + if (version_id >= 4)
  258 + qemu_get_be32s(f, &env->smbase);
  259 +
  260 + /* XXX: compute hflags from scratch, except for CPL and IIF */
  261 + env->hflags = hflags;
  262 + tlb_flush(env, 1);
  263 + return 0;
  264 +}
target-m68k/machine.c 0 → 100644
  View file @8dd3dca
  1 +#include "hw/hw.h"
  2 +#include "hw/boards.h"
  3 +
  4 +void register_machines(void)
  5 +{
  6 + qemu_register_machine(&mcf5208evb_machine);
  7 + qemu_register_machine(&an5206_machine);
  8 + qemu_register_machine(&dummy_m68k_machine);
  9 +}
target-mips/machine.c 0 → 100644
  View file @8dd3dca
  1 +#include "hw/hw.h"
  2 +#include "hw/boards.h"
  3 +
  4 +void register_machines(void)
  5 +{
  6 + qemu_register_machine(&mips_machine);
  7 + qemu_register_machine(&mips_magnum_machine);
  8 + qemu_register_machine(&mips_malta_machine);
  9 + qemu_register_machine(&mips_pica61_machine);
  10 + qemu_register_machine(&mips_mipssim_machine);
  11 +}
  12 +
  13 +void cpu_save(QEMUFile *f, void *opaque)
  14 +{
  15 +}
  16 +
  17 +int cpu_load(QEMUFile *f, void *opaque, int version_id)
  18 +{
  19 + return 0;
  20 +}
  21 +
  22 +
target-ppc/machine.c 0 → 100644
  View file @8dd3dca
  1 +#include "hw/hw.h"
  2 +#include "hw/boards.h"
  3 +
  4 +void register_machines(void)
  5 +{
  6 + qemu_register_machine(&heathrow_machine);
  7 + qemu_register_machine(&core99_machine);
  8 + qemu_register_machine(&prep_machine);
  9 + qemu_register_machine(&ref405ep_machine);
  10 + qemu_register_machine(&taihu_machine);
  11 +}
  12 +
  13 +void cpu_save(QEMUFile *f, void *opaque)
  14 +{
  15 +}
  16 +
  17 +int cpu_load(QEMUFile *f, void *opaque, int version_id)
  18 +{
  19 + return 0;
  20 +}
target-sh4/machine.c 0 → 100644
  View file @8dd3dca
  1 +#include "hw/hw.h"
  2 +#include "hw/boards.h"
  3 +
  4 +void register_machines(void)
  5 +{
  6 + qemu_register_machine(&shix_machine);
  7 + qemu_register_machine(&r2d_machine);
  8 +}
target-sparc/machine.c 0 → 100644
  View file @8dd3dca
  1 +#include "hw/hw.h"
  2 +#include "hw/boards.h"
  3 +
  4 +#include "exec-all.h"
  5 +
  6 +void register_machines(void)
  7 +{
  8 +#ifdef TARGET_SPARC64
  9 + qemu_register_machine(&sun4u_machine);
  10 +#else
  11 + qemu_register_machine(&ss5_machine);
  12 + qemu_register_machine(&ss10_machine);
  13 + qemu_register_machine(&ss600mp_machine);
  14 + qemu_register_machine(&ss20_machine);
  15 + qemu_register_machine(&ss2_machine);
  16 + qemu_register_machine(&voyager_machine);
  17 + qemu_register_machine(&ss_lx_machine);
  18 + qemu_register_machine(&ss4_machine);
  19 + qemu_register_machine(&scls_machine);
  20 + qemu_register_machine(&sbook_machine);
  21 + qemu_register_machine(&ss1000_machine);
  22 + qemu_register_machine(&ss2000_machine);
  23 +#endif
  24 +}
  25 +
  26 +void cpu_save(QEMUFile *f, void *opaque)
  27 +{
  28 + CPUState *env = opaque;
  29 + int i;
  30 + uint32_t tmp;
  31 +
  32 + for(i = 0; i < 8; i++)
  33 + qemu_put_betls(f, &env->gregs[i]);
  34 + for(i = 0; i < NWINDOWS * 16; i++)
  35 + qemu_put_betls(f, &env->regbase[i]);
  36 +
  37 + /* FPU */
  38 + for(i = 0; i < TARGET_FPREGS; i++) {
  39 + union {
  40 + float32 f;
  41 + uint32_t i;
  42 + } u;
  43 + u.f = env->fpr[i];
  44 + qemu_put_be32(f, u.i);
  45 + }
  46 +
  47 + qemu_put_betls(f, &env->pc);
  48 + qemu_put_betls(f, &env->npc);
  49 + qemu_put_betls(f, &env->y);
  50 + tmp = GET_PSR(env);
  51 + qemu_put_be32(f, tmp);
  52 + qemu_put_betls(f, &env->fsr);
  53 + qemu_put_betls(f, &env->tbr);
  54 +#ifndef TARGET_SPARC64
  55 + qemu_put_be32s(f, &env->wim);
  56 + /* MMU */
  57 + for(i = 0; i < 16; i++)
  58 + qemu_put_be32s(f, &env->mmuregs[i]);
  59 +#endif
  60 +}
  61 +
  62 +int cpu_load(QEMUFile *f, void *opaque, int version_id)
  63 +{
  64 + CPUState *env = opaque;
  65 + int i;
  66 + uint32_t tmp;
  67 +
  68 + for(i = 0; i < 8; i++)
  69 + qemu_get_betls(f, &env->gregs[i]);
  70 + for(i = 0; i < NWINDOWS * 16; i++)
  71 + qemu_get_betls(f, &env->regbase[i]);
  72 +
  73 + /* FPU */
  74 + for(i = 0; i < TARGET_FPREGS; i++) {
  75 + union {
  76 + float32 f;
  77 + uint32_t i;
  78 + } u;
  79 + u.i = qemu_get_be32(f);
  80 + env->fpr[i] = u.f;
  81 + }
  82 +
  83 + qemu_get_betls(f, &env->pc);
  84 + qemu_get_betls(f, &env->npc);
  85 + qemu_get_betls(f, &env->y);
  86 + tmp = qemu_get_be32(f);
  87 + env->cwp = 0; /* needed to ensure that the wrapping registers are
  88 + correctly updated */
  89 + PUT_PSR(env, tmp);
  90 + qemu_get_betls(f, &env->fsr);
  91 + qemu_get_betls(f, &env->tbr);
  92 +#ifndef TARGET_SPARC64
  93 + qemu_get_be32s(f, &env->wim);
  94 + /* MMU */
  95 + for(i = 0; i < 16; i++)
  96 + qemu_get_be32s(f, &env->mmuregs[i]);
  97 +#endif
  98 + tlb_flush(env, 1);
  99 + return 0;
  100 +}
  101 +
  102 +
@@ -6320,557 +6320,6 @@ void do_info_snapshots(void) @@ -6320,557 +6320,6 @@ void do_info_snapshots(void)
6320 } 6320 }
6321 6321
6322 /***********************************************************/ 6322 /***********************************************************/
6323 -/* cpu save/restore */  
6324 -  
6325 -#if defined(TARGET_I386)  
6326 -  
6327 -static void cpu_put_seg(QEMUFile *f, SegmentCache *dt)  
6328 -{  
6329 - qemu_put_be32(f, dt->selector);  
6330 - qemu_put_betl(f, dt->base);  
6331 - qemu_put_be32(f, dt->limit);  
6332 - qemu_put_be32(f, dt->flags);  
6333 -}  
6334 -  
6335 -static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)  
6336 -{  
6337 - dt->selector = qemu_get_be32(f);  
6338 - dt->base = qemu_get_betl(f);  
6339 - dt->limit = qemu_get_be32(f);  
6340 - dt->flags = qemu_get_be32(f);  
6341 -}  
6342 -  
6343 -void cpu_save(QEMUFile *f, void *opaque)  
6344 -{  
6345 - CPUState *env = opaque;  
6346 - uint16_t fptag, fpus, fpuc, fpregs_format;  
6347 - uint32_t hflags;  
6348 - int i;  
6349 -  
6350 - for(i = 0; i < CPU_NB_REGS; i++)  
6351 - qemu_put_betls(f, &env->regs[i]);  
6352 - qemu_put_betls(f, &env->eip);  
6353 - qemu_put_betls(f, &env->eflags);  
6354 - hflags = env->hflags; /* XXX: suppress most of the redundant hflags */  
6355 - qemu_put_be32s(f, &hflags);  
6356 -  
6357 - /* FPU */  
6358 - fpuc = env->fpuc;  
6359 - fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;  
6360 - fptag = 0;  
6361 - for(i = 0; i < 8; i++) {  
6362 - fptag |= ((!env->fptags[i]) << i);  
6363 - }  
6364 -  
6365 - qemu_put_be16s(f, &fpuc);  
6366 - qemu_put_be16s(f, &fpus);  
6367 - qemu_put_be16s(f, &fptag);  
6368 -  
6369 -#ifdef USE_X86LDOUBLE  
6370 - fpregs_format = 0;  
6371 -#else  
6372 - fpregs_format = 1;  
6373 -#endif  
6374 - qemu_put_be16s(f, &fpregs_format);  
6375 -  
6376 - for(i = 0; i < 8; i++) {  
6377 -#ifdef USE_X86LDOUBLE  
6378 - {  
6379 - uint64_t mant;  
6380 - uint16_t exp;  
6381 - /* we save the real CPU data (in case of MMX usage only 'mant'  
6382 - contains the MMX register */  
6383 - cpu_get_fp80(&mant, &exp, env->fpregs[i].d);  
6384 - qemu_put_be64(f, mant);  
6385 - qemu_put_be16(f, exp);  
6386 - }  
6387 -#else  
6388 - /* if we use doubles for float emulation, we save the doubles to  
6389 - avoid losing information in case of MMX usage. It can give  
6390 - problems if the image is restored on a CPU where long  
6391 - doubles are used instead. */  
6392 - qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));  
6393 -#endif  
6394 - }  
6395 -  
6396 - for(i = 0; i < 6; i++)  
6397 - cpu_put_seg(f, &env->segs[i]);  
6398 - cpu_put_seg(f, &env->ldt);  
6399 - cpu_put_seg(f, &env->tr);  
6400 - cpu_put_seg(f, &env->gdt);  
6401 - cpu_put_seg(f, &env->idt);  
6402 -  
6403 - qemu_put_be32s(f, &env->sysenter_cs);  
6404 - qemu_put_be32s(f, &env->sysenter_esp);  
6405 - qemu_put_be32s(f, &env->sysenter_eip);  
6406 -  
6407 - qemu_put_betls(f, &env->cr[0]);  
6408 - qemu_put_betls(f, &env->cr[2]);  
6409 - qemu_put_betls(f, &env->cr[3]);  
6410 - qemu_put_betls(f, &env->cr[4]);  
6411 -  
6412 - for(i = 0; i < 8; i++)  
6413 - qemu_put_betls(f, &env->dr[i]);  
6414 -  
6415 - /* MMU */  
6416 - qemu_put_be32s(f, &env->a20_mask);  
6417 -  
6418 - /* XMM */  
6419 - qemu_put_be32s(f, &env->mxcsr);  
6420 - for(i = 0; i < CPU_NB_REGS; i++) {  
6421 - qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));  
6422 - qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));  
6423 - }  
6424 -  
6425 -#ifdef TARGET_X86_64  
6426 - qemu_put_be64s(f, &env->efer);  
6427 - qemu_put_be64s(f, &env->star);  
6428 - qemu_put_be64s(f, &env->lstar);  
6429 - qemu_put_be64s(f, &env->cstar);  
6430 - qemu_put_be64s(f, &env->fmask);  
6431 - qemu_put_be64s(f, &env->kernelgsbase);  
6432 -#endif  
6433 - qemu_put_be32s(f, &env->smbase);  
6434 -}  
6435 -  
6436 -#ifdef USE_X86LDOUBLE  
6437 -/* XXX: add that in a FPU generic layer */  
6438 -union x86_longdouble {  
6439 - uint64_t mant;  
6440 - uint16_t exp;  
6441 -};  
6442 -  
6443 -#define MANTD1(fp) (fp & ((1LL << 52) - 1))  
6444 -#define EXPBIAS1 1023  
6445 -#define EXPD1(fp) ((fp >> 52) & 0x7FF)  
6446 -#define SIGND1(fp) ((fp >> 32) & 0x80000000)  
6447 -  
6448 -static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)  
6449 -{  
6450 - int e;  
6451 - /* mantissa */  
6452 - p->mant = (MANTD1(temp) << 11) | (1LL << 63);  
6453 - /* exponent + sign */  
6454 - e = EXPD1(temp) - EXPBIAS1 + 16383;  
6455 - e |= SIGND1(temp) >> 16;  
6456 - p->exp = e;  
6457 -}  
6458 -#endif  
6459 -  
6460 -int cpu_load(QEMUFile *f, void *opaque, int version_id)  
6461 -{  
6462 - CPUState *env = opaque;  
6463 - int i, guess_mmx;  
6464 - uint32_t hflags;  
6465 - uint16_t fpus, fpuc, fptag, fpregs_format;  
6466 -  
6467 - if (version_id != 3 && version_id != 4)  
6468 - return -EINVAL;  
6469 - for(i = 0; i < CPU_NB_REGS; i++)  
6470 - qemu_get_betls(f, &env->regs[i]);  
6471 - qemu_get_betls(f, &env->eip);  
6472 - qemu_get_betls(f, &env->eflags);  
6473 - qemu_get_be32s(f, &hflags);  
6474 -  
6475 - qemu_get_be16s(f, &fpuc);  
6476 - qemu_get_be16s(f, &fpus);  
6477 - qemu_get_be16s(f, &fptag);  
6478 - qemu_get_be16s(f, &fpregs_format);  
6479 -  
6480 - /* NOTE: we cannot always restore the FPU state if the image come  
6481 - from a host with a different 'USE_X86LDOUBLE' define. We guess  
6482 - if we are in an MMX state to restore correctly in that case. */  
6483 - guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);  
6484 - for(i = 0; i < 8; i++) {  
6485 - uint64_t mant;  
6486 - uint16_t exp;  
6487 -  
6488 - switch(fpregs_format) {  
6489 - case 0:  
6490 - mant = qemu_get_be64(f);  
6491 - exp = qemu_get_be16(f);  
6492 -#ifdef USE_X86LDOUBLE  
6493 - env->fpregs[i].d = cpu_set_fp80(mant, exp);  
6494 -#else  
6495 - /* difficult case */  
6496 - if (guess_mmx)  
6497 - env->fpregs[i].mmx.MMX_Q(0) = mant;  
6498 - else  
6499 - env->fpregs[i].d = cpu_set_fp80(mant, exp);  
6500 -#endif  
6501 - break;  
6502 - case 1:  
6503 - mant = qemu_get_be64(f);  
6504 -#ifdef USE_X86LDOUBLE  
6505 - {  
6506 - union x86_longdouble *p;  
6507 - /* difficult case */  
6508 - p = (void *)&env->fpregs[i];  
6509 - if (guess_mmx) {  
6510 - p->mant = mant;  
6511 - p->exp = 0xffff;  
6512 - } else {  
6513 - fp64_to_fp80(p, mant);  
6514 - }  
6515 - }  
6516 -#else  
6517 - env->fpregs[i].mmx.MMX_Q(0) = mant;  
6518 -#endif  
6519 - break;  
6520 - default:  
6521 - return -EINVAL;  
6522 - }  
6523 - }  
6524 -  
6525 - env->fpuc = fpuc;  
6526 - /* XXX: restore FPU round state */  
6527 - env->fpstt = (fpus >> 11) & 7;  
6528 - env->fpus = fpus & ~0x3800;  
6529 - fptag ^= 0xff;  
6530 - for(i = 0; i < 8; i++) {  
6531 - env->fptags[i] = (fptag >> i) & 1;  
6532 - }  
6533 -  
6534 - for(i = 0; i < 6; i++)  
6535 - cpu_get_seg(f, &env->segs[i]);  
6536 - cpu_get_seg(f, &env->ldt);  
6537 - cpu_get_seg(f, &env->tr);  
6538 - cpu_get_seg(f, &env->gdt);  
6539 - cpu_get_seg(f, &env->idt);  
6540 -  
6541 - qemu_get_be32s(f, &env->sysenter_cs);  
6542 - qemu_get_be32s(f, &env->sysenter_esp);  
6543 - qemu_get_be32s(f, &env->sysenter_eip);  
6544 -  
6545 - qemu_get_betls(f, &env->cr[0]);  
6546 - qemu_get_betls(f, &env->cr[2]);  
6547 - qemu_get_betls(f, &env->cr[3]);  
6548 - qemu_get_betls(f, &env->cr[4]);  
6549 -  
6550 - for(i = 0; i < 8; i++)  
6551 - qemu_get_betls(f, &env->dr[i]);  
6552 -  
6553 - /* MMU */  
6554 - qemu_get_be32s(f, &env->a20_mask);  
6555 -  
6556 - qemu_get_be32s(f, &env->mxcsr);  
6557 - for(i = 0; i < CPU_NB_REGS; i++) {  
6558 - qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));  
6559 - qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));  
6560 - }  
6561 -  
6562 -#ifdef TARGET_X86_64  
6563 - qemu_get_be64s(f, &env->efer);  
6564 - qemu_get_be64s(f, &env->star);  
6565 - qemu_get_be64s(f, &env->lstar);  
6566 - qemu_get_be64s(f, &env->cstar);  
6567 - qemu_get_be64s(f, &env->fmask);  
6568 - qemu_get_be64s(f, &env->kernelgsbase);  
6569 -#endif  
6570 - if (version_id >= 4)  
6571 - qemu_get_be32s(f, &env->smbase);  
6572 -  
6573 - /* XXX: compute hflags from scratch, except for CPL and IIF */  
6574 - env->hflags = hflags;  
6575 - tlb_flush(env, 1);  
6576 - return 0;  
6577 -}  
6578 -  
6579 -#elif defined(TARGET_PPC)  
6580 -void cpu_save(QEMUFile *f, void *opaque)  
6581 -{  
6582 -}  
6583 -  
6584 -int cpu_load(QEMUFile *f, void *opaque, int version_id)  
6585 -{  
6586 - return 0;  
6587 -}  
6588 -  
6589 -#elif defined(TARGET_MIPS)  
6590 -void cpu_save(QEMUFile *f, void *opaque)  
6591 -{  
6592 -}  
6593 -  
6594 -int cpu_load(QEMUFile *f, void *opaque, int version_id)  
6595 -{  
6596 - return 0;  
6597 -}  
6598 -  
6599 -#elif defined(TARGET_SPARC)  
6600 -void cpu_save(QEMUFile *f, void *opaque)  
6601 -{  
6602 - CPUState *env = opaque;  
6603 - int i;  
6604 - uint32_t tmp;  
6605 -  
6606 - for(i = 0; i < 8; i++)  
6607 - qemu_put_betls(f, &env->gregs[i]);  
6608 - for(i = 0; i < NWINDOWS * 16; i++)  
6609 - qemu_put_betls(f, &env->regbase[i]);  
6610 -  
6611 - /* FPU */  
6612 - for(i = 0; i < TARGET_FPREGS; i++) {  
6613 - union {  
6614 - float32 f;  
6615 - uint32_t i;  
6616 - } u;  
6617 - u.f = env->fpr[i];  
6618 - qemu_put_be32(f, u.i);  
6619 - }  
6620 -  
6621 - qemu_put_betls(f, &env->pc);  
6622 - qemu_put_betls(f, &env->npc);  
6623 - qemu_put_betls(f, &env->y);  
6624 - tmp = GET_PSR(env);  
6625 - qemu_put_be32(f, tmp);  
6626 - qemu_put_betls(f, &env->fsr);  
6627 - qemu_put_betls(f, &env->tbr);  
6628 -#ifndef TARGET_SPARC64  
6629 - qemu_put_be32s(f, &env->wim);  
6630 - /* MMU */  
6631 - for(i = 0; i < 16; i++)  
6632 - qemu_put_be32s(f, &env->mmuregs[i]);  
6633 -#endif  
6634 -}  
6635 -  
6636 -int cpu_load(QEMUFile *f, void *opaque, int version_id)  
6637 -{  
6638 - CPUState *env = opaque;  
6639 - int i;  
6640 - uint32_t tmp;  
6641 -  
6642 - for(i = 0; i < 8; i++)  
6643 - qemu_get_betls(f, &env->gregs[i]);  
6644 - for(i = 0; i < NWINDOWS * 16; i++)  
6645 - qemu_get_betls(f, &env->regbase[i]);  
6646 -  
6647 - /* FPU */  
6648 - for(i = 0; i < TARGET_FPREGS; i++) {  
6649 - union {  
6650 - float32 f;  
6651 - uint32_t i;  
6652 - } u;  
6653 - u.i = qemu_get_be32(f);  
6654 - env->fpr[i] = u.f;  
6655 - }  
6656 -  
6657 - qemu_get_betls(f, &env->pc);  
6658 - qemu_get_betls(f, &env->npc);  
6659 - qemu_get_betls(f, &env->y);  
6660 - tmp = qemu_get_be32(f);  
6661 - env->cwp = 0; /* needed to ensure that the wrapping registers are  
6662 - correctly updated */  
6663 - PUT_PSR(env, tmp);  
6664 - qemu_get_betls(f, &env->fsr);  
6665 - qemu_get_betls(f, &env->tbr);  
6666 -#ifndef TARGET_SPARC64  
6667 - qemu_get_be32s(f, &env->wim);  
6668 - /* MMU */  
6669 - for(i = 0; i < 16; i++)  
6670 - qemu_get_be32s(f, &env->mmuregs[i]);  
6671 -#endif  
6672 - tlb_flush(env, 1);  
6673 - return 0;  
6674 -}  
6675 -  
6676 -#elif defined(TARGET_ARM)  
6677 -  
6678 -void cpu_save(QEMUFile *f, void *opaque)  
6679 -{  
6680 - int i;  
6681 - CPUARMState *env = (CPUARMState *)opaque;  
6682 -  
6683 - for (i = 0; i < 16; i++) {  
6684 - qemu_put_be32(f, env->regs[i]);  
6685 - }  
6686 - qemu_put_be32(f, cpsr_read(env));  
6687 - qemu_put_be32(f, env->spsr);  
6688 - for (i = 0; i < 6; i++) {  
6689 - qemu_put_be32(f, env->banked_spsr[i]);  
6690 - qemu_put_be32(f, env->banked_r13[i]);  
6691 - qemu_put_be32(f, env->banked_r14[i]);  
6692 - }  
6693 - for (i = 0; i < 5; i++) {  
6694 - qemu_put_be32(f, env->usr_regs[i]);  
6695 - qemu_put_be32(f, env->fiq_regs[i]);  
6696 - }  
6697 - qemu_put_be32(f, env->cp15.c0_cpuid);  
6698 - qemu_put_be32(f, env->cp15.c0_cachetype);  
6699 - qemu_put_be32(f, env->cp15.c1_sys);  
6700 - qemu_put_be32(f, env->cp15.c1_coproc);  
6701 - qemu_put_be32(f, env->cp15.c1_xscaleauxcr);  
6702 - qemu_put_be32(f, env->cp15.c2_base0);  
6703 - qemu_put_be32(f, env->cp15.c2_base1);  
6704 - qemu_put_be32(f, env->cp15.c2_mask);  
6705 - qemu_put_be32(f, env->cp15.c2_data);  
6706 - qemu_put_be32(f, env->cp15.c2_insn);  
6707 - qemu_put_be32(f, env->cp15.c3);  
6708 - qemu_put_be32(f, env->cp15.c5_insn);  
6709 - qemu_put_be32(f, env->cp15.c5_data);  
6710 - for (i = 0; i < 8; i++) {  
6711 - qemu_put_be32(f, env->cp15.c6_region[i]);  
6712 - }  
6713 - qemu_put_be32(f, env->cp15.c6_insn);  
6714 - qemu_put_be32(f, env->cp15.c6_data);  
6715 - qemu_put_be32(f, env->cp15.c9_insn);  
6716 - qemu_put_be32(f, env->cp15.c9_data);  
6717 - qemu_put_be32(f, env->cp15.c13_fcse);  
6718 - qemu_put_be32(f, env->cp15.c13_context);  
6719 - qemu_put_be32(f, env->cp15.c13_tls1);  
6720 - qemu_put_be32(f, env->cp15.c13_tls2);  
6721 - qemu_put_be32(f, env->cp15.c13_tls3);  
6722 - qemu_put_be32(f, env->cp15.c15_cpar);  
6723 -  
6724 - qemu_put_be32(f, env->features);  
6725 -  
6726 - if (arm_feature(env, ARM_FEATURE_VFP)) {  
6727 - for (i = 0; i < 16; i++) {  
6728 - CPU_DoubleU u;  
6729 - u.d = env->vfp.regs[i];  
6730 - qemu_put_be32(f, u.l.upper);  
6731 - qemu_put_be32(f, u.l.lower);  
6732 - }  
6733 - for (i = 0; i < 16; i++) {  
6734 - qemu_put_be32(f, env->vfp.xregs[i]);  
6735 - }  
6736 -  
6737 - /* TODO: Should use proper FPSCR access functions. */  
6738 - qemu_put_be32(f, env->vfp.vec_len);  
6739 - qemu_put_be32(f, env->vfp.vec_stride);  
6740 -  
6741 - if (arm_feature(env, ARM_FEATURE_VFP3)) {  
6742 - for (i = 16; i < 32; i++) {  
6743 - CPU_DoubleU u;  
6744 - u.d = env->vfp.regs[i];  
6745 - qemu_put_be32(f, u.l.upper);  
6746 - qemu_put_be32(f, u.l.lower);  
6747 - }  
6748 - }  
6749 - }  
6750 -  
6751 - if (arm_feature(env, ARM_FEATURE_IWMMXT)) {  
6752 - for (i = 0; i < 16; i++) {  
6753 - qemu_put_be64(f, env->iwmmxt.regs[i]);  
6754 - }  
6755 - for (i = 0; i < 16; i++) {  
6756 - qemu_put_be32(f, env->iwmmxt.cregs[i]);  
6757 - }  
6758 - }  
6759 -  
6760 - if (arm_feature(env, ARM_FEATURE_M)) {  
6761 - qemu_put_be32(f, env->v7m.other_sp);  
6762 - qemu_put_be32(f, env->v7m.vecbase);  
6763 - qemu_put_be32(f, env->v7m.basepri);  
6764 - qemu_put_be32(f, env->v7m.control);  
6765 - qemu_put_be32(f, env->v7m.current_sp);  
6766 - qemu_put_be32(f, env->v7m.exception);  
6767 - }  
6768 -}  
6769 -  
6770 -int cpu_load(QEMUFile *f, void *opaque, int version_id)  
6771 -{  
6772 - CPUARMState *env = (CPUARMState *)opaque;  
6773 - int i;  
6774 -  
6775 - if (version_id != ARM_CPU_SAVE_VERSION)  
6776 - return -EINVAL;  
6777 -  
6778 - for (i = 0; i < 16; i++) {  
6779 - env->regs[i] = qemu_get_be32(f);  
6780 - }  
6781 - cpsr_write(env, qemu_get_be32(f), 0xffffffff);  
6782 - env->spsr = qemu_get_be32(f);  
6783 - for (i = 0; i < 6; i++) {  
6784 - env->banked_spsr[i] = qemu_get_be32(f);  
6785 - env->banked_r13[i] = qemu_get_be32(f);  
6786 - env->banked_r14[i] = qemu_get_be32(f);  
6787 - }  
6788 - for (i = 0; i < 5; i++) {  
6789 - env->usr_regs[i] = qemu_get_be32(f);  
6790 - env->fiq_regs[i] = qemu_get_be32(f);  
6791 - }  
6792 - env->cp15.c0_cpuid = qemu_get_be32(f);  
6793 - env->cp15.c0_cachetype = qemu_get_be32(f);  
6794 - env->cp15.c1_sys = qemu_get_be32(f);  
6795 - env->cp15.c1_coproc = qemu_get_be32(f);  
6796 - env->cp15.c1_xscaleauxcr = qemu_get_be32(f);  
6797 - env->cp15.c2_base0 = qemu_get_be32(f);  
6798 - env->cp15.c2_base1 = qemu_get_be32(f);  
6799 - env->cp15.c2_mask = qemu_get_be32(f);  
6800 - env->cp15.c2_data = qemu_get_be32(f);  
6801 - env->cp15.c2_insn = qemu_get_be32(f);  
6802 - env->cp15.c3 = qemu_get_be32(f);  
6803 - env->cp15.c5_insn = qemu_get_be32(f);  
6804 - env->cp15.c5_data = qemu_get_be32(f);  
6805 - for (i = 0; i < 8; i++) {  
6806 - env->cp15.c6_region[i] = qemu_get_be32(f);  
6807 - }  
6808 - env->cp15.c6_insn = qemu_get_be32(f);  
6809 - env->cp15.c6_data = qemu_get_be32(f);  
6810 - env->cp15.c9_insn = qemu_get_be32(f);  
6811 - env->cp15.c9_data = qemu_get_be32(f);  
6812 - env->cp15.c13_fcse = qemu_get_be32(f);  
6813 - env->cp15.c13_context = qemu_get_be32(f);  
6814 - env->cp15.c13_tls1 = qemu_get_be32(f);  
6815 - env->cp15.c13_tls2 = qemu_get_be32(f);  
6816 - env->cp15.c13_tls3 = qemu_get_be32(f);  
6817 - env->cp15.c15_cpar = qemu_get_be32(f);  
6818 -  
6819 - env->features = qemu_get_be32(f);  
6820 -  
6821 - if (arm_feature(env, ARM_FEATURE_VFP)) {  
6822 - for (i = 0; i < 16; i++) {  
6823 - CPU_DoubleU u;  
6824 - u.l.upper = qemu_get_be32(f);  
6825 - u.l.lower = qemu_get_be32(f);  
6826 - env->vfp.regs[i] = u.d;  
6827 - }  
6828 - for (i = 0; i < 16; i++) {  
6829 - env->vfp.xregs[i] = qemu_get_be32(f);  
6830 - }  
6831 -  
6832 - /* TODO: Should use proper FPSCR access functions. */  
6833 - env->vfp.vec_len = qemu_get_be32(f);  
6834 - env->vfp.vec_stride = qemu_get_be32(f);  
6835 -  
6836 - if (arm_feature(env, ARM_FEATURE_VFP3)) {  
6837 - for (i = 0; i < 16; i++) {  
6838 - CPU_DoubleU u;  
6839 - u.l.upper = qemu_get_be32(f);  
6840 - u.l.lower = qemu_get_be32(f);  
6841 - env->vfp.regs[i] = u.d;  
6842 - }  
6843 - }  
6844 - }  
6845 -  
6846 - if (arm_feature(env, ARM_FEATURE_IWMMXT)) {  
6847 - for (i = 0; i < 16; i++) {  
6848 - env->iwmmxt.regs[i] = qemu_get_be64(f);  
6849 - }  
6850 - for (i = 0; i < 16; i++) {  
6851 - env->iwmmxt.cregs[i] = qemu_get_be32(f);  
6852 - }  
6853 - }  
6854 -  
6855 - if (arm_feature(env, ARM_FEATURE_M)) {  
6856 - env->v7m.other_sp = qemu_get_be32(f);  
6857 - env->v7m.vecbase = qemu_get_be32(f);  
6858 - env->v7m.basepri = qemu_get_be32(f);  
6859 - env->v7m.control = qemu_get_be32(f);  
6860 - env->v7m.current_sp = qemu_get_be32(f);  
6861 - env->v7m.exception = qemu_get_be32(f);  
6862 - }  
6863 -  
6864 - return 0;  
6865 -}  
6866 -  
6867 -#else  
6868 -  
6869 -//#warning No CPU save/restore functions  
6870 -  
6871 -#endif  
6872 -  
6873 -/***********************************************************/  
6874 /* ram save/restore */ 6323 /* ram save/restore */
6875 6324
6876 static int ram_get_page(QEMUFile *f, uint8_t *buf, int len) 6325 static int ram_get_page(QEMUFile *f, uint8_t *buf, int len)
@@ -8025,74 +7474,6 @@ static void read_passwords(void) @@ -8025,74 +7474,6 @@ static void read_passwords(void)
8025 } 7474 }
8026 } 7475 }
8027 7476
8028 -/* XXX: currently we cannot use simultaneously different CPUs */  
8029 -static void register_machines(void)  
8030 -{  
8031 -#if defined(TARGET_I386)  
8032 - qemu_register_machine(&pc_machine);  
8033 - qemu_register_machine(&isapc_machine);  
8034 -#elif defined(TARGET_PPC)  
8035 - qemu_register_machine(&heathrow_machine);  
8036 - qemu_register_machine(&core99_machine);  
8037 - qemu_register_machine(&prep_machine);  
8038 - qemu_register_machine(&ref405ep_machine);  
8039 - qemu_register_machine(&taihu_machine);  
8040 -#elif defined(TARGET_MIPS)  
8041 - qemu_register_machine(&mips_machine);  
8042 - qemu_register_machine(&mips_magnum_machine);  
8043 - qemu_register_machine(&mips_malta_machine);  
8044 - qemu_register_machine(&mips_pica61_machine);  
8045 - qemu_register_machine(&mips_mipssim_machine);  
8046 -#elif defined(TARGET_SPARC)  
8047 -#ifdef TARGET_SPARC64  
8048 - qemu_register_machine(&sun4u_machine);  
8049 -#else  
8050 - qemu_register_machine(&ss5_machine);  
8051 - qemu_register_machine(&ss10_machine);  
8052 - qemu_register_machine(&ss600mp_machine);  
8053 - qemu_register_machine(&ss20_machine);  
8054 - qemu_register_machine(&ss2_machine);  
8055 - qemu_register_machine(&voyager_machine);  
8056 - qemu_register_machine(&ss_lx_machine);  
8057 - qemu_register_machine(&ss4_machine);  
8058 - qemu_register_machine(&scls_machine);  
8059 - qemu_register_machine(&sbook_machine);  
8060 - qemu_register_machine(&ss1000_machine);  
8061 - qemu_register_machine(&ss2000_machine);  
8062 -#endif  
8063 -#elif defined(TARGET_ARM)  
8064 - qemu_register_machine(&integratorcp_machine);  
8065 - qemu_register_machine(&versatilepb_machine);  
8066 - qemu_register_machine(&versatileab_machine);  
8067 - qemu_register_machine(&realview_machine);  
8068 - qemu_register_machine(&akitapda_machine);  
8069 - qemu_register_machine(&spitzpda_machine);  
8070 - qemu_register_machine(&borzoipda_machine);  
8071 - qemu_register_machine(&terrierpda_machine);  
8072 - qemu_register_machine(&palmte_machine);  
8073 - qemu_register_machine(&n800_machine);  
8074 - qemu_register_machine(&lm3s811evb_machine);  
8075 - qemu_register_machine(&lm3s6965evb_machine);  
8076 - qemu_register_machine(&connex_machine);  
8077 - qemu_register_machine(&verdex_machine);  
8078 - qemu_register_machine(&mainstone2_machine);  
8079 - qemu_register_machine(&musicpal_machine);  
8080 -#elif defined(TARGET_SH4)  
8081 - qemu_register_machine(&shix_machine);  
8082 - qemu_register_machine(&r2d_machine);  
8083 -#elif defined(TARGET_ALPHA)  
8084 - /* XXX: TODO */  
8085 -#elif defined(TARGET_M68K)  
8086 - qemu_register_machine(&mcf5208evb_machine);  
8087 - qemu_register_machine(&an5206_machine);  
8088 - qemu_register_machine(&dummy_m68k_machine);  
8089 -#elif defined(TARGET_CRIS)  
8090 - qemu_register_machine(&bareetraxfs_machine);  
8091 -#else  
8092 -#error unsupported CPU  
8093 -#endif  
8094 -}  
8095 -  
8096 #ifdef HAS_AUDIO 7477 #ifdef HAS_AUDIO
8097 struct soundhw soundhw[] = { 7478 struct soundhw soundhw[] = {
8098 #ifdef HAS_AUDIO_CHOICE 7479 #ifdef HAS_AUDIO_CHOICE