gwj / at91sam9263 · Commits

Commit 8c99506cfbf61da72fa007b972636b43db21fb2e

Authored by ths
1 parent 6e0d8677

Fix local register cache handling. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4495 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 13 additions and 4 deletions
target-mips/translate.c
  View file @8c99506
@@ -504,7 +504,7 @@ static inline void gen_op_store_gpr_T1(int reg) @@ -504,7 +504,7 @@ static inline void gen_op_store_gpr_T1(int reg)
504 /* Moves to/from shadow registers */ 504 /* Moves to/from shadow registers */
505 static inline void gen_op_load_srsgpr_T0(int reg) 505 static inline void gen_op_load_srsgpr_T0(int reg)
506 { 506 {
507 - int r_tmp = new_tmp(); 507 + TCGv r_tmp = new_tmp();
508 508
509 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl)); 509 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
510 tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS); 510 tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
@@ -518,7 +518,7 @@ static inline void gen_op_load_srsgpr_T0(int reg) @@ -518,7 +518,7 @@ static inline void gen_op_load_srsgpr_T0(int reg)
518 518
519 static inline void gen_op_store_srsgpr_T0(int reg) 519 static inline void gen_op_store_srsgpr_T0(int reg)
520 { 520 {
521 - int r_tmp = new_tmp(); 521 + TCGv r_tmp = new_tmp();
522 522
523 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl)); 523 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
524 tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS); 524 tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
@@ -1016,7 +1016,7 @@ OP_LD_ATOMIC(lld,ld64); @@ -1016,7 +1016,7 @@ OP_LD_ATOMIC(lld,ld64);
1016 #define OP_ST_ATOMIC(insn,fname,almask) \ 1016 #define OP_ST_ATOMIC(insn,fname,almask) \
1017 void inline op_ldst_##insn(DisasContext *ctx) \ 1017 void inline op_ldst_##insn(DisasContext *ctx) \
1018 { \ 1018 { \
1019 - int r_tmp = tcg_temp_new(TCG_TYPE_TL); \ 1019 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL); \
1020 int l1 = gen_new_label(); \ 1020 int l1 = gen_new_label(); \
1021 int l2 = gen_new_label(); \ 1021 int l2 = gen_new_label(); \
1022 int l3 = gen_new_label(); \ 1022 int l3 = gen_new_label(); \
@@ -1956,7 +1956,7 @@ static inline void tcg_gen_set_bcond(void) @@ -1956,7 +1956,7 @@ static inline void tcg_gen_set_bcond(void)
1956 1956
1957 static inline void tcg_gen_jnz_bcond(int label) 1957 static inline void tcg_gen_jnz_bcond(int label)
1958 { 1958 {
1959 - int r_tmp = tcg_temp_new(TCG_TYPE_TL); 1959 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
1960 1960
1961 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond)); 1961 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
1962 tcg_gen_brcond_tl(TCG_COND_NE, r_tmp, tcg_const_tl(0), label); 1962 tcg_gen_brcond_tl(TCG_COND_NE, r_tmp, tcg_const_tl(0), label);
@@ -6834,6 +6834,9 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, @@ -6834,6 +6834,9 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
6834 if (search_pc && loglevel) 6834 if (search_pc && loglevel)
6835 fprintf (logfile, "search pc %d\n", search_pc); 6835 fprintf (logfile, "search pc %d\n", search_pc);
6836 6836
  6837 + num_temps = 0;
  6838 + memset(temps, 0, sizeof(temps));
  6839 +
6837 pc_start = tb->pc; 6840 pc_start = tb->pc;
6838 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; 6841 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6839 ctx.pc = pc_start; 6842 ctx.pc = pc_start;
@@ -6888,6 +6891,12 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, @@ -6888,6 +6891,12 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
6888 } 6891 }
6889 ctx.opcode = ldl_code(ctx.pc); 6892 ctx.opcode = ldl_code(ctx.pc);
6890 decode_opc(env, &ctx); 6893 decode_opc(env, &ctx);
  6894 + if (num_temps) {
  6895 + fprintf(stderr,
  6896 + "Internal resource leak before " TARGET_FMT_lx "\n",
  6897 + ctx.pc);
  6898 + num_temps = 0;
  6899 + }
6891 ctx.pc += 4; 6900 ctx.pc += 4;
6892 6901
6893 if (env->singlestep_enabled) 6902 if (env->singlestep_enabled)