Commit 8a4c1cc4118720fb69f0e9aa3c15275e13294946
1 parent
330d0414
fixed ss segment load - added ICEBP instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@339 c046a42c-6fe2-441c-8c8c-71466251a162
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7 additions
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3 deletions
translate-i386.c
| ... | ... | @@ -1277,9 +1277,10 @@ static void gen_movl_seg_T0(DisasContext *s, int seg_reg, unsigned int cur_eip) |
| 1277 | 1277 | gen_op_movl_seg_T0(seg_reg, cur_eip); |
| 1278 | 1278 | else |
| 1279 | 1279 | gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg])); |
| 1280 | - if (!s->addseg && seg_reg < R_FS) | |
| 1281 | - s->is_jmp = 2; /* abort translation because the register may | |
| 1282 | - have a non zero base */ | |
| 1280 | + /* abort translation because the register may have a non zero base | |
| 1281 | + or because ss32 may change */ | |
| 1282 | + if (seg_reg == R_SS || (!s->addseg && seg_reg < R_FS)) | |
| 1283 | + s->is_jmp = 2; | |
| 1283 | 1284 | } |
| 1284 | 1285 | |
| 1285 | 1286 | /* generate a push. It depends on ss32, addseg and dflag */ |
| ... | ... | @@ -3420,6 +3421,9 @@ long disas_insn(DisasContext *s, uint8_t *pc_start) |
| 3420 | 3421 | gen_op_set_cc_op(s->cc_op); |
| 3421 | 3422 | gen_op_into(s->pc - s->cs_base); |
| 3422 | 3423 | break; |
| 3424 | + case 0xf1: /* icebp (undocumented, exits to external debugger) */ | |
| 3425 | + gen_debug(s, pc_start - s->cs_base); | |
| 3426 | + break; | |
| 3423 | 3427 | case 0xfa: /* cli */ |
| 3424 | 3428 | if (!s->vm86) { |
| 3425 | 3429 | if (s->cpl <= s->iopl) { | ... | ... |